URL https://opencores.org/ocsvn/plb2wbbridge/plb2wbbridge/trunk

Subversion Repositories plb2wbbridge

[/] [plb2wbbridge/] [trunk/] [systems/] [test_system_sim/] [wb_err_and_rst/] [system.mhs] - Blame information for rev 2

Details | Compare with Previous | View Log


 
# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 11.4 Build EDK_LS4.68
# Fri Mar  5 18:02:26 2010
# Target Board:  Xilinx Virtex 5 ML501 Evaluation Platform Rev 1
# Family:    virtex5
# Device:    xc5vlx50
# Package:   ff676
# Speed Grade:  -1
# Processor number: 1
# Processor 1: microblaze_0
# System clock frequency: 125.0
# Debug Interface: On-Chip HW Debug Module
# ##############################################################################
 PARAMETER VERSION = 2.1.0
 
 
 PORT sys_clk_pin = clk_100MHz, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
 PORT sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1
 PORT to_synch_in_pin = synch_in, DIR = I, VEC = [0:31]
 PORT from_synch_out_pin = synch_out, DIR = O, VEC = [0:31]
 PORT wb_clk_pin = wb_clk, DIR = I, SIGIS = CLK
 PORT wb_rst_pin = wb_rst, DIR = I, SIGIS = RST
 
 
BEGIN plb_v46
 PARAMETER INSTANCE = mb_plb
 PARAMETER HW_VER = 1.04.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER C_DCR_INTFCE = 1
 PARAMETER C_BASEADDR = 0b0000000000
 PARAMETER C_HIGHADDR = 0b1111111111
 PORT PLB_Clk = clk_100MHz
 PORT SYS_Rst = sys_rst_s
END
 
BEGIN plbv46_master_bfm
 PARAMETER INSTANCE = plb_bfm_master_32
 PARAMETER HW_VER = 1.00.a
 PARAMETER PLB_MASTER_SIZE = 0b10
 PARAMETER PLB_MASTER_NUM = 0b0000
 PARAMETER C_MPLB_NATIVE_DWIDTH = 128
 PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff
 BUS_INTERFACE MPLB = mb_plb
 PORT SYNCH_OUT = bfm_synch_out_0
 PORT SYNCH_IN = synch_in
END
 
BEGIN plbv46_master_bfm
 PARAMETER INSTANCE = plb_bfm_master_64
 PARAMETER HW_VER = 1.00.a
 PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff
 PARAMETER PLB_MASTER_SIZE = 0b10
 PARAMETER PLB_MASTER_NUM = 0b0001
 PARAMETER C_MPLB_NATIVE_DWIDTH = 128
 BUS_INTERFACE MPLB = mb_plb
 PORT SYNCH_OUT = bfm_synch_out_1
 PORT SYNCH_IN = synch_in
END
 
BEGIN plbv46_master_bfm
 PARAMETER INSTANCE = plb_bfm_master_128
 PARAMETER HW_VER = 1.00.a
 PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff
 PARAMETER C_MPLB_NATIVE_DWIDTH = 128
 PARAMETER PLB_MASTER_NUM = 0b0010
 BUS_INTERFACE MPLB = mb_plb
 PORT SYNCH_OUT = bfm_synch_out_2
 PORT SYNCH_IN = synch_in
END
 
BEGIN plbv46_monitor_bfm
 PARAMETER INSTANCE = plb_bfm_monitor
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE MON_PLB = mb_plb
 PORT SYNCH_OUT = bfm_synch_out_3
 PORT SYNCH_IN = synch_in
END
 
BEGIN plbv46_slave_bfm
 PARAMETER INSTANCE = plb_bfm_slave
 PARAMETER HW_VER = 1.00.a
 PARAMETER PLB_SLAVE_ADDR_LO_0 = 0x00020000
 PARAMETER PLB_SLAVE_ADDR_HI_0 = 0x0002ffff
 PARAMETER C_SPLB_NATIVE_DWIDTH = 32
 PARAMETER PLB_SLAVE_SIZE = 0b00
 BUS_INTERFACE SPLB = mb_plb
 PORT SYNCH_IN = synch_in
 PORT SYNCH_OUT = bfm_synch_out_4
END
 
BEGIN bfm_synch
 PARAMETER INSTANCE = plb_bfm_synch
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_NUM_SYNCH = 5
 PORT TO_SYNCH_IN = synch_out
 PORT FROM_SYNCH_OUT = bfm_synch_out_0 & bfm_synch_out_1 & bfm_synch_out_2 & bfm_synch_out_3 & bfm_synch_out_4
END
 
BEGIN plb2wb_bridge
 PARAMETER INSTANCE = plb2wb_bridge_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0xf0000000
 PARAMETER C_HIGHADDR = 0xf7ffffff
 PARAMETER WB_ADR_OFFSET = 0xf0000000
 PARAMETER WB_ADR_OFFSET_NEG = 1
 PARAMETER SYNCHRONY = false
 PARAMETER C_STATUS_BASEADDR = 0x00010000
 PARAMETER C_STATUS_HIGHADDR = 0x0001FFFF
 PARAMETER WB_PIC_INTS = 1
 BUS_INTERFACE SPLB = mb_plb
 BUS_INTERFACE MWB = wb_conbus_0
 PORT SPLB_Clk = clk_100MHz
 PORT wb_clk_i = wb_clk
 PORT wb_rst_i = wb_rst
 PORT wb_pic_int_i = net_gnd
END
 
BEGIN wb_conbus
 PARAMETER INSTANCE = wb_conbus_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER wb_s0_addr = 0x00
 PARAMETER wb_s27_addr_w = 8
 PARAMETER wb_s1_addr = 0x01
 PARAMETER wb_s2_addr = 0x02
 PARAMETER wb_s3_addr = 0x03
 PARAMETER wb_s4_addr = 0x04
 PARAMETER wb_s5_addr = 0x05
 PARAMETER wb_s6_addr = 0x06
 PARAMETER wb_s7_addr = 0x07
 PARAMETER wb_s0_addr_w = 8
 PARAMETER wb_s1_addr_w = 8
 PORT wb_rst_i = wb_rst
 PORT wb_clk_i = wb_clk
END
 
BEGIN testram
 PARAMETER INSTANCE = onchip_ram_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER RD_DELAY = 0
 PARAMETER WR_DELAY = 0
 PARAMETER WITH_ERR_OR_RTY = 0b01
# PARAMETER WITH_ERR_OR_RTY = 0b00
 PARAMETER ERR_RTY_INTERVAL = 2
 BUS_INTERFACE SWB = wb_conbus_0
 PORT wb_rst_i = wb_rst
 PORT wb_clk_i = wb_clk
END
 
BEGIN testram
 PARAMETER INSTANCE = onchip_ram_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER RD_DELAY = 1
 PARAMETER WR_DELAY = 1
 PARAMETER WITH_ERR_OR_RTY = 0b01
# PARAMETER WITH_ERR_OR_RTY = 0b00
 PARAMETER ERR_RTY_INTERVAL = 3
 BUS_INTERFACE SWB = wb_conbus_0
 PORT wb_clk_i = wb_clk
 PORT wb_rst_i = wb_rst
END
 
BEGIN testram
 PARAMETER INSTANCE = onchip_ram_2
 PARAMETER HW_VER = 1.00.a
 PARAMETER RD_DELAY = 3
 PARAMETER WR_DELAY = 3
 PARAMETER WITH_ERR_OR_RTY = 0b01
# PARAMETER WITH_ERR_OR_RTY = 0b00
 PARAMETER ERR_RTY_INTERVAL = 4
 BUS_INTERFACE SWB = wb_conbus_0
 PORT wb_clk_i = wb_clk
 PORT wb_rst_i = wb_rst
END
 
BEGIN testram
 PARAMETER INSTANCE = onchip_ram_3
 PARAMETER HW_VER = 1.00.a
 PARAMETER RD_DELAY = 5
 PARAMETER WR_DELAY = 5
 PARAMETER WITH_ERR_OR_RTY = 0b01
# PARAMETER WITH_ERR_OR_RTY = 0b00
 PARAMETER ERR_RTY_INTERVAL = 2
 BUS_INTERFACE SWB = wb_conbus_0
 PORT wb_clk_i = wb_clk
 PORT wb_rst_i = wb_rst
END
 
BEGIN testram
 PARAMETER INSTANCE = onchip_ram_4
 PARAMETER HW_VER = 1.00.a
 PARAMETER RD_DELAY = 11
 PARAMETER WR_DELAY = 8
 BUS_INTERFACE SWB = wb_conbus_0
 PORT wb_rst_i = wb_rst
 PORT wb_clk_i = wb_clk
END
 
BEGIN testram
 PARAMETER INSTANCE = onchip_ram_5
 PARAMETER HW_VER = 1.00.a
 PARAMETER RD_DELAY = 11
 PARAMETER WR_DELAY = 11
 BUS_INTERFACE SWB = wb_conbus_0
 PORT wb_rst_i = wb_rst
 PORT wb_clk_i = wb_clk
END
 

Browse

Tools

Subversion Repositories plb2wbbridge

[/] [plb2wbbridge/] [trunk/] [systems/] [test_system_sim/] [wb_err_and_rst/] [system.mhs] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	feddischso
2			`# ##############################################################################`
3			`# Created by Base System Builder Wizard for Xilinx EDK 11.4 Build EDK_LS4.68`
4			`# Fri Mar 5 18:02:26 2010`
5			`# Target Board: Xilinx Virtex 5 ML501 Evaluation Platform Rev 1`
6			`# Family: virtex5`
7			`# Device: xc5vlx50`
8			`# Package: ff676`
9			`# Speed Grade: -1`
10			`# Processor number: 1`
11			`# Processor 1: microblaze_0`
12			`# System clock frequency: 125.0`
13			`# Debug Interface: On-Chip HW Debug Module`
14			`# ##############################################################################`
15			`PARAMETER VERSION = 2.1.0`
16
17
18			`PORT sys_clk_pin = clk_100MHz, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000`
19			`PORT sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1`
20			`PORT to_synch_in_pin = synch_in, DIR = I, VEC = [0:31]`
21			`PORT from_synch_out_pin = synch_out, DIR = O, VEC = [0:31]`
22			`PORT wb_clk_pin = wb_clk, DIR = I, SIGIS = CLK`
23			`PORT wb_rst_pin = wb_rst, DIR = I, SIGIS = RST`
24
25
26			`BEGIN plb_v46`
27			`PARAMETER INSTANCE = mb_plb`
28			`PARAMETER HW_VER = 1.04.a`
29			`PARAMETER C_EXT_RESET_HIGH = 1`
30			`PARAMETER C_DCR_INTFCE = 1`
31			`PARAMETER C_BASEADDR = 0b0000000000`
32			`PARAMETER C_HIGHADDR = 0b1111111111`
33			`PORT PLB_Clk = clk_100MHz`
34			`PORT SYS_Rst = sys_rst_s`
35			`END`
36
37			`BEGIN plbv46_master_bfm`
38			`PARAMETER INSTANCE = plb_bfm_master_32`
39			`PARAMETER HW_VER = 1.00.a`
40			`PARAMETER PLB_MASTER_SIZE = 0b10`
41			`PARAMETER PLB_MASTER_NUM = 0b0000`
42			`PARAMETER C_MPLB_NATIVE_DWIDTH = 128`
43			`PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff`
44			`BUS_INTERFACE MPLB = mb_plb`
45			`PORT SYNCH_OUT = bfm_synch_out_0`
46			`PORT SYNCH_IN = synch_in`
47			`END`
48
49			`BEGIN plbv46_master_bfm`
50			`PARAMETER INSTANCE = plb_bfm_master_64`
51			`PARAMETER HW_VER = 1.00.a`
52			`PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff`
53			`PARAMETER PLB_MASTER_SIZE = 0b10`
54			`PARAMETER PLB_MASTER_NUM = 0b0001`
55			`PARAMETER C_MPLB_NATIVE_DWIDTH = 128`
56			`BUS_INTERFACE MPLB = mb_plb`
57			`PORT SYNCH_OUT = bfm_synch_out_1`
58			`PORT SYNCH_IN = synch_in`
59			`END`
60
61			`BEGIN plbv46_master_bfm`
62			`PARAMETER INSTANCE = plb_bfm_master_128`
63			`PARAMETER HW_VER = 1.00.a`
64			`PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff`
65			`PARAMETER C_MPLB_NATIVE_DWIDTH = 128`
66			`PARAMETER PLB_MASTER_NUM = 0b0010`
67			`BUS_INTERFACE MPLB = mb_plb`
68			`PORT SYNCH_OUT = bfm_synch_out_2`
69			`PORT SYNCH_IN = synch_in`
70			`END`
71
72			`BEGIN plbv46_monitor_bfm`
73			`PARAMETER INSTANCE = plb_bfm_monitor`
74			`PARAMETER HW_VER = 1.00.a`
75			`BUS_INTERFACE MON_PLB = mb_plb`
76			`PORT SYNCH_OUT = bfm_synch_out_3`
77			`PORT SYNCH_IN = synch_in`
78			`END`
79
80			`BEGIN plbv46_slave_bfm`
81			`PARAMETER INSTANCE = plb_bfm_slave`
82			`PARAMETER HW_VER = 1.00.a`
83			`PARAMETER PLB_SLAVE_ADDR_LO_0 = 0x00020000`
84			`PARAMETER PLB_SLAVE_ADDR_HI_0 = 0x0002ffff`
85			`PARAMETER C_SPLB_NATIVE_DWIDTH = 32`
86			`PARAMETER PLB_SLAVE_SIZE = 0b00`
87			`BUS_INTERFACE SPLB = mb_plb`
88			`PORT SYNCH_IN = synch_in`
89			`PORT SYNCH_OUT = bfm_synch_out_4`
90			`END`
91
92			`BEGIN bfm_synch`
93			`PARAMETER INSTANCE = plb_bfm_synch`
94			`PARAMETER HW_VER = 1.00.a`
95			`PARAMETER C_NUM_SYNCH = 5`
96			`PORT TO_SYNCH_IN = synch_out`
97			`PORT FROM_SYNCH_OUT = bfm_synch_out_0 & bfm_synch_out_1 & bfm_synch_out_2 & bfm_synch_out_3 & bfm_synch_out_4`
98			`END`
99
100			`BEGIN plb2wb_bridge`
101			`PARAMETER INSTANCE = plb2wb_bridge_0`
102			`PARAMETER HW_VER = 1.00.a`
103			`PARAMETER C_BASEADDR = 0xf0000000`
104			`PARAMETER C_HIGHADDR = 0xf7ffffff`
105			`PARAMETER WB_ADR_OFFSET = 0xf0000000`
106			`PARAMETER WB_ADR_OFFSET_NEG = 1`
107			`PARAMETER SYNCHRONY = false`
108			`PARAMETER C_STATUS_BASEADDR = 0x00010000`
109			`PARAMETER C_STATUS_HIGHADDR = 0x0001FFFF`
110			`PARAMETER WB_PIC_INTS = 1`
111			`BUS_INTERFACE SPLB = mb_plb`
112			`BUS_INTERFACE MWB = wb_conbus_0`
113			`PORT SPLB_Clk = clk_100MHz`
114			`PORT wb_clk_i = wb_clk`
115			`PORT wb_rst_i = wb_rst`
116			`PORT wb_pic_int_i = net_gnd`
117			`END`
118
119			`BEGIN wb_conbus`
120			`PARAMETER INSTANCE = wb_conbus_0`
121			`PARAMETER HW_VER = 1.00.a`
122			`PARAMETER wb_s0_addr = 0x00`
123			`PARAMETER wb_s27_addr_w = 8`
124			`PARAMETER wb_s1_addr = 0x01`
125			`PARAMETER wb_s2_addr = 0x02`
126			`PARAMETER wb_s3_addr = 0x03`
127			`PARAMETER wb_s4_addr = 0x04`
128			`PARAMETER wb_s5_addr = 0x05`
129			`PARAMETER wb_s6_addr = 0x06`
130			`PARAMETER wb_s7_addr = 0x07`
131			`PARAMETER wb_s0_addr_w = 8`
132			`PARAMETER wb_s1_addr_w = 8`
133			`PORT wb_rst_i = wb_rst`
134			`PORT wb_clk_i = wb_clk`
135			`END`
136
137			`BEGIN testram`
138			`PARAMETER INSTANCE = onchip_ram_0`
139			`PARAMETER HW_VER = 1.00.a`
140			`PARAMETER RD_DELAY = 0`
141			`PARAMETER WR_DELAY = 0`
142			`PARAMETER WITH_ERR_OR_RTY = 0b01`
143			`# PARAMETER WITH_ERR_OR_RTY = 0b00`
144			`PARAMETER ERR_RTY_INTERVAL = 2`
145			`BUS_INTERFACE SWB = wb_conbus_0`
146			`PORT wb_rst_i = wb_rst`
147			`PORT wb_clk_i = wb_clk`
148			`END`
149
150			`BEGIN testram`
151			`PARAMETER INSTANCE = onchip_ram_1`
152			`PARAMETER HW_VER = 1.00.a`
153			`PARAMETER RD_DELAY = 1`
154			`PARAMETER WR_DELAY = 1`
155			`PARAMETER WITH_ERR_OR_RTY = 0b01`
156			`# PARAMETER WITH_ERR_OR_RTY = 0b00`
157			`PARAMETER ERR_RTY_INTERVAL = 3`
158			`BUS_INTERFACE SWB = wb_conbus_0`
159			`PORT wb_clk_i = wb_clk`
160			`PORT wb_rst_i = wb_rst`
161			`END`
162
163			`BEGIN testram`
164			`PARAMETER INSTANCE = onchip_ram_2`
165			`PARAMETER HW_VER = 1.00.a`
166			`PARAMETER RD_DELAY = 3`
167			`PARAMETER WR_DELAY = 3`
168			`PARAMETER WITH_ERR_OR_RTY = 0b01`
169			`# PARAMETER WITH_ERR_OR_RTY = 0b00`
170			`PARAMETER ERR_RTY_INTERVAL = 4`
171			`BUS_INTERFACE SWB = wb_conbus_0`
172			`PORT wb_clk_i = wb_clk`
173			`PORT wb_rst_i = wb_rst`
174			`END`
175
176			`BEGIN testram`
177			`PARAMETER INSTANCE = onchip_ram_3`
178			`PARAMETER HW_VER = 1.00.a`
179			`PARAMETER RD_DELAY = 5`
180			`PARAMETER WR_DELAY = 5`
181			`PARAMETER WITH_ERR_OR_RTY = 0b01`
182			`# PARAMETER WITH_ERR_OR_RTY = 0b00`
183			`PARAMETER ERR_RTY_INTERVAL = 2`
184			`BUS_INTERFACE SWB = wb_conbus_0`
185			`PORT wb_clk_i = wb_clk`
186			`PORT wb_rst_i = wb_rst`
187			`END`
188
189			`BEGIN testram`
190			`PARAMETER INSTANCE = onchip_ram_4`
191			`PARAMETER HW_VER = 1.00.a`
192			`PARAMETER RD_DELAY = 11`
193			`PARAMETER WR_DELAY = 8`
194			`BUS_INTERFACE SWB = wb_conbus_0`
195			`PORT wb_rst_i = wb_rst`
196			`PORT wb_clk_i = wb_clk`
197			`END`
198
199			`BEGIN testram`
200			`PARAMETER INSTANCE = onchip_ram_5`
201			`PARAMETER HW_VER = 1.00.a`
202			`PARAMETER RD_DELAY = 11`
203			`PARAMETER WR_DELAY = 11`
204			`BUS_INTERFACE SWB = wb_conbus_0`
205			`PORT wb_rst_i = wb_rst`
206			`PORT wb_clk_i = wb_clk`
207			`END`
208