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[/] [plb2wbbridge/] [trunk/] [systems/] [test_system_sim/] [wb_retries/] [simulation/] [testbench/] [system_tb.vhd] - Blame information for rev 2

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1 2 feddischso
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library UNISIM;
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use UNISIM.VCOMPONENTS.ALL;
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entity system_tb is
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end system_tb;
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architecture STRUCTURE of system_tb is
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  constant sys_clk_period     : time    := 10.000000 ns;
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  constant wb_clk_period      : time    := 13.333333 ns;
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  constant sys_rst_length     : time    := 160 ns;
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  constant SYNCH_PART         : integer := 1;
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  constant SYNCH_SUBPART      : integer := 2;
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  constant SYNCH_SUBSUBPART   : integer := 3;
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  constant SUBSUBPART_LENGTH  : integer := 15;  -- 10 clock cycles
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  constant SUBPART_LENGTH     : integer := 5;  -- 7 times SUBSUBPART_LENGTH
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  constant PART_LENGTH        : integer := 5;  -- 6 times SUBPART_LENGTH
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  component system is
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    port (
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      sys_clk_pin          : in  std_logic;
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      sys_rst_pin          : in  std_logic;
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      to_synch_in_pin      : in  std_logic_vector( 0 to 31 );
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      from_synch_out_pin   : out std_logic_vector( 0 to 31 );
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      wb_clk_pin           : in  std_logic;
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      wb_rst_pin           : in  std_logic
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    );
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  end component;
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   signal sys_clk : std_logic;
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   signal sys_rst : std_logic := '1';
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   signal wb_clk  : std_logic;
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   signal wb_rst  : std_logic;
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   signal to_synch_in       : std_logic_vector( 0 to 31 );
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   signal from_synch_out    : std_logic_vector( 0 to 31 );
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   signal tb_synch_out      : std_logic_vector( 0 to 31 )   := ( others => '0' );
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   procedure SendSynch( signal synch_out : OUT std_logic_vector;
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                                COMMAND :     integer ) is
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   begin
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      synch_out( COMMAND ) <= '1';
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      wait for sys_clk_period*1;
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      synch_out( COMMAND ) <= '0';
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   end procedure SendSynch;
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begin
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   to_synch_in <= from_synch_out or tb_synch_out;
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   dut : system
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      port map (
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         sys_clk_pin          => sys_clk,
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         sys_rst_pin          => sys_rst,
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         to_synch_in_pin      => to_synch_in,
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         from_synch_out_pin   => from_synch_out,
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         wb_clk_pin           => wb_clk,
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         wb_rst_pin           => wb_rst
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      );
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   --
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   -- generate plb-clk
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   -- 
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   process
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   begin
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      sys_clk <= '0';
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      loop
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         wait for (sys_clk_period/2);
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         sys_clk <= not sys_clk;
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      end loop;
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   end process;
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   --
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   --
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   --
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   process
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   begin
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      wb_clk  <= '0';
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      loop
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         wait for (wb_clk_period/2);
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         wb_clk  <= not wb_clk;
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      end loop;
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   end process;
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   process
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   begin
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      sys_rst <= '1';
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      wb_rst  <= '1';
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      wait for ( sys_rst_length );
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      wb_rst  <= not wb_rst;
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      sys_rst <= not sys_rst;
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      wait;
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   end process;
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   process
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   begin
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    wait until sys_rst = '0';
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    -- wait until masters a ready
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    wait for sys_clk_period * 10;
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    while true loop
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      for i in 0 to PART_LENGTH-1 loop
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         SendSynch( tb_synch_out, SYNCH_PART );
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         for j in 0 to SUBPART_LENGTH-1 loop
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            SendSynch( tb_synch_out, SYNCH_SUBPART );
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            for k in 0 to SUBSUBPART_LENGTH loop
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               SendSynch( tb_synch_out, SYNCH_SUBSUBPART );
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               wait for (SUBSUBPART_LENGTH * sys_clk_period );
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            end loop;
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         end loop;
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      end loop;
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   end loop;
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   end process;
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end architecture STRUCTURE;
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