Subversion Repositories product_code_iterative_decoder

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-- Copyright (C) 2005 Arif Endro Nugroho

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library IEEE;

use IEEE.std_logic_1164.all;

entity bit_comparator is

   port (

      a_i   : in  bit;

      b_i   : in  bit;

      eq_i  : in  bit;

      gt_i  : in  bit;

      lt_i  : in  bit;

      eq_o  : out bit;

      gt_o  : out bit;

      lt_o  : out bit

      );

end bit_comparator;

architecture data_flow of bit_comparator is

begin

     lt_o <= (((not(a_i) and lt_i) or (b_i and lt_i)) or (not(a_i) and b_i));

     eq_o <= (((a_i and b_i) and eq_i) or ((not(a_i) and not(b_i)) and eq_i));

     gt_o <= (((a_i and gt_i) or (not(b_i) and gt_i)) or (a_i and not(b_i)));

end data_flow;