OpenCores
URL https://opencores.org/ocsvn/ps2_host_controller/ps2_host_controller/trunk

Subversion Repositories ps2_host_controller

[/] [ps2_host_controller/] [trunk/] [hdl/] [ps2_host_testbench.v] - Blame information for rev 4

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 tesla
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  ps2_host_testbench.v                                        ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  Testbench to verify core correctness                        ////
7
////                                                              ////
8
////  Author:                                                     ////
9
////      - Piotr Foltyn, piotr.foltyn@gmail.com                  ////
10
////                                                              ////
11
//////////////////////////////////////////////////////////////////////
12
////                                                              ////
13
//// Copyright (C) 2011 Author                                    ////
14
////                                                              ////
15
//// This source file may be used and distributed without         ////
16
//// restriction provided that this copyright statement is not    ////
17
//// removed from the file and that any derivative work contains  ////
18
//// the original copyright notice and the associated disclaimer. ////
19
////                                                              ////
20
//// This source file is free software; you can redistribute it   ////
21
//// and/or modify it under the terms of the GNU Lesser General   ////
22
//// Public License as published by the Free Software Foundation; ////
23
//// either version 2.1 of the License, or (at your option) any   ////
24
//// later version.                                               ////
25
////                                                              ////
26
//// This source is distributed in the hope that it will be       ////
27
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
28
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
29
//// PURPOSE.  See the GNU Lesser General Public License for more ////
30
//// details.                                                     ////
31
////                                                              ////
32
//// You should have received a copy of the GNU Lesser General    ////
33
//// Public License along with this source; if not, download it   ////
34
//// from http://www.opencores.org/lgpl.shtml                     ////
35
////                                                              ////
36
//////////////////////////////////////////////////////////////////////
37
 
38
// synopsys translate_off
39
`include "timescale.v"
40
// synopsys translate_on
41
`include "ps2_host.v"
42
 
43
`define SYS_PERIOD 1
44
`define PS2_PERIOD (`SYS_PERIOD*4)
45
 
46
module ps2_host_testbench;
47
 
48
reg sys_clk;
49
reg sys_rst;
50
 
51
reg ps2_clk_r;
52
reg ps2_data_r;
53
tri1 ps2_clk  = (ps2_clk_r)  ? 1'bz : 1'b0;
54
tri1 ps2_data = (ps2_data_r) ? 1'bz : 1'b0;
55
 
56
reg [7:0] tx_data;
57
reg send_req;
58
wire busy;
59
 
60
wire [7:0] rx_data;
61
wire ready;
62
wire error;
63
 
64
// System clock
65
always #`SYS_PERIOD sys_clk = ~sys_clk;
66
 
67
// System reset
68
initial begin
69
  sys_clk = 0;
70
  ps2_clk_r = 1;
71
  ps2_data_r = 1;
72
  send_req = 0;
73
 
74
  sys_rst = 1;
75
  sys_rst = #(`SYS_PERIOD*2) 0;
76
end
77
 
78
// Receiver test
79
task receiver_test;
80
  input start_bit;
81
  input [7:0] bits;
82
  input parity_bit;
83
  input stop_bit;
84
  input expect_error;
85
  reg [10:0] frame;
86
  integer bit_cnt;
87
begin
88
  frame = {start_bit,bits[0],bits[1],bits[2],bits[3],
89
                     bits[4],bits[5],bits[6],bits[7],parity_bit,stop_bit};
90
  for (bit_cnt = 0; bit_cnt < 11; bit_cnt = bit_cnt + 1) begin
91
    ps2_data_r = frame[10 - bit_cnt];
92
    ps2_clk_r = #`PS2_PERIOD 0;
93
    ps2_clk_r = #`PS2_PERIOD 1;
94
  end
95 4 tesla
  wait (ready);
96 2 tesla
  if ((bits != rx_data) | (error != expect_error)) begin
97
    $display("Failed: Frame:0x%x Rx:0x%x Err:%b", frame, rx_data, error);
98
  end
99
  ps2_data_r = 1;
100
end endtask
101
 
102
// Transmitter test
103
task transmitter_test;
104
  input [7:0] bits;
105
  integer bit_cnt;
106
  reg [10:0] frame;
107
begin
108
  frame = 0;
109
  tx_data = bits;
110
  send_req = #(`SYS_PERIOD*2) 1;
111
  send_req = #(`SYS_PERIOD*2) 0;
112
  wait (~ps2_data);
113
  for (bit_cnt = 0; bit_cnt < 11; bit_cnt = bit_cnt + 1) begin
114
    ps2_clk_r = #`PS2_PERIOD 0;
115
    frame = {frame[9:0], ps2_data};
116
    ps2_clk_r = #`PS2_PERIOD 1;
117
  end
118 4 tesla
  wait (~busy);
119 2 tesla
  if (({bits[0],bits[1],bits[2],bits[3],bits[4],bits[5],bits[6],bits[7]} != frame[9:2]) |
120
      frame[10] | (~^frame[9:2] != frame[1]) | ~frame[0]) begin
121
    $display("Failed: Frame:0x%x Tx:0x%x", frame, bits);
122
  end
123
end endtask
124
 
125
// Test runner
126
integer byte;
127
always @(negedge sys_rst) begin
128 4 tesla
  for (byte = 0; byte < 256; byte = byte + 1) begin
129 2 tesla
    // Transmitter test
130
    transmitter_test(byte);
131
 
132
    // Correct case - data ok and error low
133
    receiver_test(0, byte, ~^byte, 1, 0);
134
    // Invalid start bit case - data ok and error high
135
    receiver_test(1, byte, ~^byte, 1, 1);
136
    // Invalid parity bit case - data ok and error high
137
    receiver_test(0, byte, ^byte, 1, 1);
138
    // Invalid stop bit case - data ok and error high
139
    receiver_test(0, byte, ~^byte, 0, 1);
140
  end
141
  #`PS2_PERIOD $finish();
142
end
143
 
144
// Dump data for GTKWave
145
initial begin
146
  $dumpfile("ps2_host_testbench.lxt");
147
  $dumpvars(0, ps2_host_testbench);
148
end
149
 
150
// Device Under Test
151
ps2_host ps2_host(
152
  .sys_clk(sys_clk),
153
  .sys_rst(sys_rst),
154
  .ps2_clk(ps2_clk),
155
  .ps2_data(ps2_data),
156
 
157
  .tx_data(tx_data),
158
  .send_req(send_req),
159
  .busy(busy),
160
 
161
  .rx_data(rx_data),
162
  .ready(ready),
163
  .error(error)
164
);
165
 
166
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.