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[/] [psg16/] [trunk/] [rtl/] [verilog/] [PSGFilter.v] - Blame information for rev 2

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1 2 robfinch
`timescale 1ns / 1ps
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// ============================================================================
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//      (C) 2007,2012  Robert Finch
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//  robfinch<remove>@opencores.org
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//      All rights reserved.
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//
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//      PSGFilter.v
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//      Version 1.1
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//
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//
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//        16-tap digital filter
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//
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//    Currently this filter is only partially tested. The author believes that
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//    the approach used is valid however.
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//      The author opted to include the filter because it is part of the design,
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//      and even this untested component can provide an idea of the resource
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//      requirements, and device capabilities.
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//              This is a "how one might approach the problem" example, at least
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//      until the author is sure the filter is working correctly.
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//        
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//      Time division multiplexing is used to implement this filter in order to
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//      reduce the resource requirement. This should be okay because it is being
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//      used to filter audio signals. The effective operating frequency of the
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//      filter depends on the 'cnt' supplied (eg 1MHz)
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//
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//      Spartan3
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//      Webpack 9.1i xc3s1000-4ft256
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//      158 LUTs / 88 slices / 73.865MHz
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//      1 MULT
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//============================================================================
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//
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module PSGFilter(rst, clk, cnt, wr, adr, din, i, o);
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parameter pTaps = 16;
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input rst;
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input clk;
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input [7:0] cnt;
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input wr;
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input [3:0] adr;
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input [12:0] din;
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input [14:0] i;
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output [14:0] o;
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reg [14:0] o;
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reg [30:0] acc;                 // accumulator
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reg [14:0] tap [0:pTaps-1];     // tap registers
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integer n;
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// coefficient memory
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reg [11:0] coeff [0:pTaps-1];   // magnitude of coefficient
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reg [pTaps-1:0] sgn;            // sign of coefficient
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initial begin
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        for (n = 0; n < pTaps; n = n + 1)
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        begin
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                coeff[n] <= 0;
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                sgn[n] <= 0;
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        end
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end
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// update coefficient memory
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always @(posedge clk)
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    if (wr) begin
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        coeff[adr] <= din[11:0];
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        sgn[adr] <= din[12];
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    end
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// shift taps
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// Note: infer a dsr by NOT resetting the registers
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always @(posedge clk)
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    if (cnt==8'd0) begin
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        tap[0] <= i;
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        for (n = 1; n < pTaps; n = n + 1)
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                tap[n] <= tap[n-1];
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    end
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wire [26:0] mult = coeff[cnt[3:0]] * tap[cnt[3:0]];
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always @(posedge clk)
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    if (rst)
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        acc <= 0;
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    else if (cnt==8'd0)
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        acc <= sgn[cnt[3:0]] ? 0 - mult : 0 + mult;
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    else if (cnt < pTaps)
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        acc <= sgn[cnt[3:0]] ? acc - mult : acc + mult;
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always @(posedge clk)
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    if (rst)
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        o <= 0;
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    else if (cnt==8'd0)
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        o <= acc[30:16];
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endmodule
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