--********************************************************************* -- DDR 72 Bit Controller DATA PATH for LEFT RIGHT Pins -- In the current DATA PATH logic DATA CAPTURE part was modified. -- The below changes were made to reduce the resources in -- the data capture -- in the current architecture data ( dq ) from ddr memory -- directly stored into the FIFO's. -- Architectural changes : -- Used only TWO FIFOs ( instead of FOUR FIFOs ) -- Used Single col ( col0 ) dqs_delayed_col signals -- Used Gray Counters for write and read pointers of the FIFOs -- fbit stage is removed from ddr1_dqbit module ( in the data capture ) -- dq_clk stage was removed -- dqs_clk_div logic was removed -- ddr1_transfer_done logic was removed -- data valid signals registering in clk90 domain was removed -- fifo_0 and fifo_1 wr_addr was double registered in clk90 domain -- only fifo_0 and fifo_1 empty signals were used for read_data_valid_1 logic -- write enable for the FIFOs derived from rst_dqs_div signal --********************************************************************* library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; --library synplify; --use synplify.attributes.all; -- -- pragma translate_off library UNISIM; use UNISIM.VCOMPONENTS.ALL; -- pragma translate_on -- entity data_read_controller is port( clk90 : in std_logic; clk180 : in std_logic; reset_r : in std_logic; reset90_r : in std_logic; rst_dqs_div_in : in std_logic; delay_sel : in std_logic_vector(4 downto 0); dqs_int_delay_in0 : in std_logic; dqs_int_delay_in1 : in std_logic; fifo0_rd_addr : in std_logic_vector(3 downto 0); fifo1_rd_addr : in std_logic_vector(3 downto 0); u_data_val : out std_logic; read_valid_data_1_val : out std_logic; fifo_00_wr_en_val : out std_logic; fifo_10_wr_en_val : out std_logic; fifo_01_wr_en_val : out std_logic; fifo_11_wr_en_val : out std_logic; fifo_00_wr_addr_val : out std_logic_vector(3 downto 0); fifo_01_wr_addr_val : out std_logic_vector(3 downto 0); fifo_10_wr_addr_val : out std_logic_vector(3 downto 0); fifo_11_wr_addr_val : out std_logic_vector(3 downto 0); -- dqs0_delayed_col1_val : out std_logic; -- dqs1_delayed_col1_val : out std_logic dqs0_delayed_col0_val : out std_logic; dqs1_delayed_col0_val : out std_logic ); end data_read_controller; architecture arc_data_read_controller of data_read_controller is component LUT4 generic( INIT : bit_vector(15 downto 0) := x"0000" ); port( O : out STD_ULOGIC; I0 : in STD_ULOGIC; I1 : in STD_ULOGIC; I2 : in STD_ULOGIC; I3 : in STD_ULOGIC ); end component; component dqs_delay port ( clk_in : in std_logic; sel_in : in std_logic_vector(4 downto 0); clk_out : out std_logic ); end component; -- wr_gray_cntr is a gray counter with an ASYNC reset for fifo wr_addr component wr_gray_cntr port ( clk : in std_logic; reset : in std_logic; cnt_en : in std_logic; wgc_gcnt : out std_logic_vector(3 downto 0) ); end component; -- fifo_wr_en module generates fifo write enable signal -- enable is derived from rst_dqs_div signal component fifo_0_wr_en port ( clk : in std_logic; reset : in std_logic; din : in std_logic; rst_dqs_delay_n : out std_logic; dout : out std_logic ); end component; component fifo_1_wr_en port ( clk : in std_logic; rst_dqs_delay_n : in std_logic; reset : in std_logic; din : in std_logic; dout : out std_logic ); end component ; signal dqs_delayed_col0 : std_logic_vector(1 downto 0); --signal dqs_delayed_col1 : std_logic_vector(1 downto 0); signal fifo_00_empty : std_logic; signal fifo_01_empty : std_logic; signal fifo_00_wr_addr : std_logic_vector(3 downto 0); signal fifo_01_wr_addr : std_logic_vector(3 downto 0); signal fifo_10_wr_addr : std_logic_vector(3 downto 0); signal fifo_11_wr_addr : std_logic_vector(3 downto 0); --signal fifo_20_wr_addr : std_logic_vector(3 downto 0); --signal fifo_21_wr_addr : std_logic_vector(3 downto 0); --signal fifo_30_wr_addr : std_logic_vector(3 downto 0); --signal fifo_31_wr_addr : std_logic_vector(3 downto 0); --signal fifo_40_wr_addr : std_logic_vector(3 downto 0); --signal fifo_41_wr_addr : std_logic_vector(3 downto 0); --signal fifo_50_wr_addr : std_logic_vector(3 downto 0); --signal fifo_51_wr_addr : std_logic_vector(3 downto 0); --signal fifo_60_wr_addr : std_logic_vector(3 downto 0); --signal fifo_61_wr_addr : std_logic_vector(3 downto 0); --signal fifo_70_wr_addr : std_logic_vector(3 downto 0); --signal fifo_71_wr_addr : std_logic_vector(3 downto 0); signal read_valid_data_0_1 : std_logic; signal read_valid_data_r : std_logic; signal read_valid_data_r1 : std_logic; signal dqs0_delayed_col0 : std_logic; signal dqs1_delayed_col0 : std_logic; --signal dqs0_delayed_col1 : std_logic; --signal dqs1_delayed_col1 : std_logic; -- dqsx_delayed_col0 negated signals -- used for capturing negedge data into FIFO_*1 -- FIFO WRITE ENABLE SIGNALS signal fifo_00_wr_en : std_logic; signal fifo_10_wr_en : std_logic; signal fifo_01_wr_en : std_logic; signal fifo_11_wr_en : std_logic; -- FIFO_WR_POINTER Delayed signals in clk90 domain signal fifo_00_wr_addr_d : std_logic_vector(3 downto 0); signal fifo_00_wr_addr_2d : std_logic_vector(3 downto 0); signal fifo_00_wr_addr_3d : std_logic_vector(3 downto 0); signal fifo_01_wr_addr_d : std_logic_vector(3 downto 0); signal fifo_01_wr_addr_2d : std_logic_vector(3 downto 0); signal fifo_01_wr_addr_3d : std_logic_vector(3 downto 0); -- DDR_DQ_IN signals from DDR_DQ Input buffer --signal ddr_dq_in : std_logic_vector(63 downto 0); --signal write_data270_1 : std_logic_vector(63 downto 0); --signal write_data270_2 : std_logic_vector(63 downto 0); signal rst_dqs_div : std_logic; --signal rst_dqs_div2 : std_logic; signal rst_dqs_delay_0_n : std_logic; signal rst_dqs_delay_1_n : std_logic; --signal rst_dqs_delay_2_n : std_logic; --signal rst_dqs_delay_3_n : std_logic; --signal rst_dqs_delay_4_n : std_logic; --signal rst_dqs_delay_5_n : std_logic; --signal rst_dqs_delay_6_n : std_logic; --signal rst_dqs_delay_7_n : std_logic; signal dqs0_delayed_col0_n : std_logic; signal dqs1_delayed_col0_n : std_logic; --signal dqs0_delayed_col1_n : std_logic; --signal dqs1_delayed_col1_n : std_logic; signal tclk180_rst_dqs_div_in : std_logic; signal tclk180_rst_dqs_div_in_delay1 : std_logic; signal tclk180_rst_dqs_div_in_delay2 : std_logic; signal tclk180_rst_dqs_div_end_pulse : std_logic; -- used for clear WEs signal fifo_xx_we_reset : std_logic; -- signal rst_dqs_div_in_delay1 : std_logic; signal rst_dqs_div_in_delay2 : std_logic; signal rst_dqs_div_in_delay3 : std_logic; attribute syn_keep : boolean; -- Using Syn_Keep Derictive attribute syn_keep of rst_dqs_div : signal is true; --attribute syn_keep of rst_dqs_div_in_delay1 : signal is true; --attribute syn_keep of rst_dqs_div_in_delay2 : signal is true; --attribute syn_keep of rst_dqs_div_in_delay3 : signal is true; begin fifo_00_wr_addr_val <= fifo_00_wr_addr; fifo_01_wr_addr_val <= fifo_01_wr_addr; fifo_10_wr_addr_val <= fifo_10_wr_addr; fifo_11_wr_addr_val <= fifo_11_wr_addr; fifo_00_wr_en_val <= fifo_00_wr_en; fifo_10_wr_en_val <= fifo_10_wr_en; fifo_01_wr_en_val <= fifo_01_wr_en; fifo_11_wr_en_val <= fifo_11_wr_en; -- dqs0_delayed_col1_val <= dqs0_delayed_col1; -- dqs1_delayed_col1_val <= dqs1_delayed_col1; dqs0_delayed_col0_val <= dqs0_delayed_col0; dqs1_delayed_col0_val <= dqs1_delayed_col0; -- dqsx_delayed_col0 negated signals dqs0_delayed_col0_n <= not dqs0_delayed_col0; dqs1_delayed_col0_n <= not dqs1_delayed_col0; -- dqsx_delayed_col1 negated signals --dqs0_delayed_col1_n <= not dqs0_delayed_col1; --dqs1_delayed_col1_n <= not dqs1_delayed_col1; -- data_valid signal is derived from fifo_00 and fifo_01 empty signals only -- FIFO WRITE POINTER DELAYED SIGNALS -- To avoid meta-stability due to the domain crossing from ddr_dqs to clk90 process (clk90) begin if (rising_edge(clk90)) then if (reset90_r = '1') then fifo_00_wr_addr_d <= "0000"; fifo_01_wr_addr_d <= "0000"; else fifo_00_wr_addr_d <= fifo_00_wr_addr; fifo_01_wr_addr_d <= fifo_01_wr_addr; end if; end if; end process; -- FIFO WRITE POINTER DOUBLE DELAYED SIGNALS process (clk90) begin if (rising_edge(clk90)) then if (reset90_r = '1') then fifo_00_wr_addr_2d <= "0000"; fifo_01_wr_addr_2d <= "0000"; else fifo_00_wr_addr_2d <= fifo_00_wr_addr_d; fifo_01_wr_addr_2d <= fifo_01_wr_addr_d; end if; end if; end process; process (clk90) begin if (rising_edge(clk90)) then if (reset90_r = '1') then fifo_00_wr_addr_3d <= "0000"; fifo_01_wr_addr_3d <= "0000"; else fifo_00_wr_addr_3d <= fifo_00_wr_addr_2d; fifo_01_wr_addr_3d <= fifo_01_wr_addr_2d; end if; end if; end process; -- user data valid output signal from data path. fifo_00_empty <= '1' when (fifo0_rd_addr(3 downto 0) = fifo_00_wr_addr_3d(3 downto 0)) else '0'; fifo_01_empty <= '1' when (fifo1_rd_addr(3 downto 0) = fifo_01_wr_addr_3d(3 downto 0)) else '0'; read_valid_data_0_1 <= ( (not fifo_00_empty) and (not fifo_01_empty) ); read_valid_data_1_val <= (read_valid_data_0_1); process(clk90) begin if clk90'event and clk90 = '1' then if reset90_r = '1' then u_data_val <= '0'; read_valid_data_r <= '0'; read_valid_data_r1 <= '0'; else read_valid_data_r <= read_valid_data_0_1; read_valid_data_r1 <= read_valid_data_r; u_data_val <= read_valid_data_r1; end if; end if; end process; dqs0_delayed_col0 <= dqs_delayed_col0(0); dqs1_delayed_col0 <= dqs_delayed_col0(1); --dqs0_delayed_col1 <= dqs_delayed_col1(0); --dqs1_delayed_col1 <= dqs_delayed_col1(1); -- dqsx_delayed_col0 negated signals rst_dqs_div_lut_delay1 : LUT4 generic map (INIT => x"e2e2") port map ( I0 => '1', I1 => not rst_dqs_div_in, I2 => '0', I3 => '1', -- O => rst_dqs_div O => rst_dqs_div_in_delay1 ); rst_dqs_div_lut_delay2 : LUT4 generic map (INIT => x"e2e2") port map ( I0 => '1', I1 => not rst_dqs_div_in_delay1, I2 => '0', I3 => '1', O => rst_dqs_div_in_delay2 ); rst_dqs_div_lut_delay3 : LUT4 generic map (INIT => x"e2e2") port map ( I0 => '1', I1 => not rst_dqs_div_in_delay2, I2 => '0', I3 => '1', O => rst_dqs_div_in_delay3 ); rst_dqs_div_lut_delay4 : LUT4 generic map (INIT => x"e2e2") port map ( I0 => '1', I1 => not rst_dqs_div_in_delay3, I2 => '0', I3 => '1', O => rst_dqs_div ); --rst_dqs_div_delayed1 : dqs_delay port map ( -- clk_in => rst_dqs_div_in, -- sel_in => delay_sel, -- clk_out => rst_dqs_div -- ); -------------------------------------------------------------------------------------------------------------------------------------------------- --************************************************************************************************** -- DQS Internal Delay Circuit implemented in LUTs --************************************************************************************************** -- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs --dqs_delay0_col0 : dqs_delay port map ( -- clk_in => dqs_int_delay_in0, -- sel_in => delay_sel, -- clk_out => dqs_delayed_col0(0) -- ); dqs_delayed_col0(0) <= dqs_int_delay_in0 ; -- Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs --dqs_delay1_col0 : dqs_delay port map ( -- clk_in => dqs_int_delay_in1, -- sel_in => delay_sel, -- clk_out => dqs_delayed_col0(1) -- ); dqs_delayed_col0(1) <= dqs_int_delay_in1 ; ------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------ -- help logic, die am Ende des Read Cycles auf jeden Fall die WE enable signale zurueck setzen soll -- ich habe geshen, das WE0 und WE1 gestzt bleiben , da das "rst_dqs_div" wohl mit der letzten -- negativen Flanke von dqs_int_delay_in1wohl noch gültig ist. clr_we_signal_logic: process(clk180) begin if rising_edge (clk180) then tclk180_rst_dqs_div_in <= rst_dqs_div ; tclk180_rst_dqs_div_in_delay1 <= tclk180_rst_dqs_div_in ; tclk180_rst_dqs_div_in_delay2 <= tclk180_rst_dqs_div_in_delay1 ; tclk180_rst_dqs_div_end_pulse <= tclk180_rst_dqs_div_in_delay2 and not tclk180_rst_dqs_div_in_delay1; end if; end process; fifo_xx_we_reset <= reset_r or tclk180_rst_dqs_div_end_pulse ; ------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------ fifo_00_wr_en_inst: fifo_0_wr_en port map ( clk => dqs0_delayed_col0_n, -- reset => reset_r, reset => fifo_xx_we_reset, din => rst_dqs_div, rst_dqs_delay_n => rst_dqs_delay_0_n, dout => fifo_00_wr_en ); fifo_01_wr_en_inst: fifo_1_wr_en port map ( clk => dqs0_delayed_col0, rst_dqs_delay_n => rst_dqs_delay_0_n, reset => fifo_xx_we_reset, din => rst_dqs_div, dout => fifo_01_wr_en ); fifo_10_wr_en_inst: fifo_0_wr_en port map ( clk => dqs1_delayed_col0_n, reset => fifo_xx_we_reset, din => rst_dqs_div, rst_dqs_delay_n => rst_dqs_delay_1_n, dout => fifo_10_wr_en ); fifo_11_wr_en_inst: fifo_1_wr_en port map ( clk => dqs1_delayed_col0, rst_dqs_delay_n => rst_dqs_delay_1_n, reset => fifo_xx_we_reset, din => rst_dqs_div, dout => fifo_11_wr_en ); ------------------------------------------------------------------------------------------------- -- write pointer gray counter instances fifo_00_wr_addr_inst : wr_gray_cntr port map ( clk => dqs0_delayed_col0, reset => reset_r, cnt_en => fifo_00_wr_en, wgc_gcnt => fifo_00_wr_addr ); fifo_01_wr_addr_inst : wr_gray_cntr port map ( clk => dqs0_delayed_col0_n, reset => reset_r, cnt_en => fifo_01_wr_en, wgc_gcnt => fifo_01_wr_addr ); fifo_10_wr_addr_inst : wr_gray_cntr port map ( clk => dqs1_delayed_col0, reset => reset_r, cnt_en => fifo_10_wr_en, wgc_gcnt => fifo_10_wr_addr ); fifo_11_wr_addr_inst : wr_gray_cntr port map ( clk => dqs1_delayed_col0_n, reset => reset_r, cnt_en => fifo_11_wr_en, wgc_gcnt => fifo_11_wr_addr ); end arc_data_read_controller;