URL
https://opencores.org/ocsvn/pulse_processing_algorithm/pulse_processing_algorithm/trunk
NET "system_adc_clk_p" TNM_NET = "system_adc_clk_p";
TIMESPEC "TS_system_adc_clk_p" = PERIOD "system_adc_clk_p" 10.0 ns HIGH 50 %;
NET "adc1_clk" TNM_NET = "adc1_clk";
TIMESPEC "TS_adc1_dco_p" = PERIOD "adc1_clk" 10 ns HIGH 50 %;
NET "adc2_clk" TNM_NET = "adc2_clk";
TIMESPEC "TS_adc2_dco_p" = PERIOD "adc2_clk" 10 ns HIGH 50 %;
NET "system_clk_ibufg" TNM_NET = "system_clk_ibufg";
TIMESPEC "TS_system_clk_ibufg" = PERIOD "system_clk_ibufg" 9.0 ns HIGH 50 %;
NET "system_clk_p" TNM_NET = "system_clk_p";
NET "adc2_dco_p" TNM_NET = "adc2_dco_p";
NET "adc1_dco_p" TNM_NET = "adc1_dco_p";
NET "clk90_int" TNM_NET = "TN_ddr_clock90";
NET "clk_int" TNM_NET = "TN_ddr_clock";
NET "sys_clk_100" TNM_NET = "TN_sys_100_clock";
TIMESPEC "TS_sys_100_clock_to_ddr_clock90" = FROM "TN_sys_100_clock" TO "TN_ddr_clock90" 10 ns;
TIMESPEC "TS_ddr_clock90_to_sys_100_clock" = FROM "TN_ddr_clock90" TO "TN_sys_100_clock" 10 ns;
TIMESPEC "TS_sys_100_clock_to_ddr_clock" = FROM "TN_sys_100_clock" TO "TN_ddr_clock" 10 ns;
TIMESPEC "TS_ddr_clock_to_sys_100_clock" = FROM "TN_ddr_clock" TO "TN_sys_100_clock" 10 ns;
NET "adc1_clk" TNM_NET = "TN_adc1_clk";
TIMESPEC "TS_adc1_clk_to_sys_100_clock" = FROM "TN_adc1_clk" TO "TN_sys_100_clock" 10 ns;
TIMESPEC "TS_sys_100_clock_to_adc1_clk" = FROM "TN_sys_100_clock" TO "TN_adc1_clk" 10 ns;
#PL
#NET "adc2_clk" TNM_NET = "TN_adc2_clk";
#TIMESPEC "TS_adc2_clk_to_sys_100_clock" = FROM "TN_adc2_clk" TO "TN_sys_100_clock" 10 ns;
#TIMESPEC "TS_sys_100_clock_to_adc2_clk" = FROM "TN_sys_100_clock" TO "TN_adc2_clk" 10 ns;
#PL
TIMEGRP "timegr_dqs" = PADS( "ddr1_dqs<0>" "ddr1_dqs<1>" );
TIMEGRP "timegr_dq" = PADS( "ddr1_dq<0>" "ddr1_dq<1>" "ddr1_dq<2>" "ddr1_dq<3>" "ddr1_dq<4>" "ddr1_dq<5>" "ddr1_dq<6>" "ddr1_dq<7>" "ddr1_dq<8>" "ddr1_dq<9>" "ddr1_dq<10>" "ddr1_dq<11>" "ddr1_dq<12>" "ddr1_dq<13>" "ddr1_dq<14>" "ddr1_dq<15>" );
NET "system_adc_clk" MAXDELAY = 1000ps ;
NET "ram2_ddr2_iobs/datapath_ddr2_iobs0/dqs0_in" MAXDELAY = 2000ps ; #600ps
NET "ram2_ddr2_iobs/datapath_ddr2_iobs0/dqs1_in" MAXDELAY = 2000ps ; #600ps
NET "ram2_ddr2_dq_in_rising*" MAXDELAY = 600ps ;
NET "ram2_ddr2_dq_in_falling*" MAXDELAY = 600ps ;
NET "ram2_ddr2_data_path/data_read_controller0/fifo_00_wr_en_inst/din_delay" MAXDELAY = 400ps ;
NET "ram2_ddr2_data_path/data_read_controller0/fifo_01_wr_en_inst/din_delay_1" MAXDELAY = 400ps ;
NET "ram2_ddr2_data_path/data_read_controller0/fifo_10_wr_en_inst/din_delay" MAXDELAY = 400ps ;
NET "ram2_ddr2_data_path/data_read_controller0/fifo_11_wr_en_inst/din_delay_1" MAXDELAY = 400ps ;
NET "ram2_ddr2_data_path/data_read_controller0/fifo_11_wr_en_inst/dout0" MAXDELAY = 400ps ;
NET "ram2_ddr2_data_path/fifo*_wr_en" MAXDELAY = 1100ps ;
NET "ram2_ddr2_data_path/fifo*_wr_addr*" MAXDELAY = 2000ps ;
NET "ram2_ddr2_data_path/fifo*_rd_addr*" MAXDELAY = 2000ps ;
NET "ram2_ddr2_data_path/data_read0/fifo*rd_addr_r*" MAXDELAY = 2000ps ;
NET "ram2_ddr2_data_path/data_read0/fifo_*_data_out*" MAXDELAY = 2500ps ;
NET "ram2_ddr2_data_path/reset_r*" MAXDELAY = 1500ps ;
NET "ram2_controller/rst_dqs_div_r*" MAXDELAY = 800ps ;
NET "ram2_ddr2_rst_dqs_div_int*" MAXDELAY = 800ps ;
NET "ram2_controller/dqs_reset*" MAXDELAY = 1800ps ;
NET "ram2_ddr2_rst_dqs_div" MAXDELAY = 800ps ;
INST "ram2_ddr2_data_path/data_read0/fifo0_bit0" LOC = "SLICE_X78Y78";
INST "ram2_ddr2_data_path/data_read0/fifo1_bit0" LOC = "SLICE_X76Y78";
INST "ram2_ddr2_data_path/data_read0/fifo0_bit1" LOC = "SLICE_X78Y79";
INST "ram2_ddr2_data_path/data_read0/fifo1_bit1" LOC = "SLICE_X76Y79";
INST "ram2_ddr2_data_path/data_read0/fifo0_bit2" LOC = "SLICE_X78Y80";
INST "ram2_ddr2_data_path/data_read0/fifo1_bit2" LOC = "SLICE_X76Y80";
INST "ram2_ddr2_data_path/data_read0/fifo0_bit3" LOC = "SLICE_X78Y81";
INST "ram2_ddr2_data_path/data_read0/fifo1_bit3" LOC = "SLICE_X76Y81";
INST "ram2_ddr2_data_path/data_read0/fifo0_bit4" LOC = "SLICE_X78Y82";
INST "ram2_ddr2_data_path/data_read0/fifo1_bit4" LOC = "SLICE_X76Y82";
INST "ram2_ddr2_data_path/data_read0/fifo0_bit5" LOC = "SLICE_X78Y83";
INST "ram2_ddr2_data_path/data_read0/fifo1_bit5" LOC = "SLICE_X76Y83";
INST "ram2_ddr2_data_path/data_read0/fifo0_bit6" LOC = "SLICE_X78Y86";
INST "ram2_ddr2_data_path/data_read0/fifo1_bit6" LOC = "SLICE_X76Y86";
INST "ram2_ddr2_data_path/data_read0/fifo0_bit7" LOC = "SLICE_X78Y87";
INST "ram2_ddr2_data_path/data_read0/fifo1_bit7" LOC = "SLICE_X76Y87";
INST "ram2_ddr2_data_path/data_read_controller0/fifo_00_wr_addr_inst/bit0" LOC = "SLICE_X79Y86";
INST "ram2_ddr2_data_path/data_read_controller0/fifo_00_wr_addr_inst/bit1" LOC = "SLICE_X79Y86";
INST "ram2_ddr2_data_path/data_read_controller0/fifo_00_wr_addr_inst/bit2" LOC = "SLICE_X79Y87";
INST "ram2_ddr2_data_path/data_read_controller0/fifo_00_wr_addr_inst/bit3" LOC = "SLICE_X79Y87";
INST "ram2_ddr2_data_path/data_read_controller0/fifo_00_wr_en_inst/delay_ff" LOC = "SLICE_X77Y78";
INST "ram2_ddr2_data_path/data_read_controller0/fifo_01_wr_addr_inst/bit0" LOC = "SLICE_X77Y86";
INST "ram2_ddr2_data_path/data_read_controller0/fifo_01_wr_addr_inst/bit1" LOC = "SLICE_X77Y86";
INST "ram2_ddr2_data_path/data_read_controller0/fifo_01_wr_addr_inst/bit2" LOC = "SLICE_X77Y87";
INST "ram2_ddr2_data_path/data_read_controller0/fifo_01_wr_addr_inst/bit3" LOC = "SLICE_X77Y87";
INST "ram2_ddr2_data_path/data_read_controller0/fifo_01_wr_en_inst/delay_ff_1" LOC = "SLICE_X79Y78";
INST "ram2_ddr2_data_path/data_read0/fifo0_bit8" LOC = "SLICE_X78Y54";
INST "ram2_ddr2_data_path/data_read0/fifo1_bit8" LOC = "SLICE_X76Y54";
INST "ram2_ddr2_data_path/data_read0/fifo0_bit9" LOC = "SLICE_X78Y52";
INST "ram2_ddr2_data_path/data_read0/fifo1_bit9" LOC = "SLICE_X76Y52";
INST "ram2_ddr2_data_path/data_read0/fifo0_bit10" LOC = "SLICE_X78Y56";
INST "ram2_ddr2_data_path/data_read0/fifo1_bit10" LOC = "SLICE_X76Y56";
INST "ram2_ddr2_data_path/data_read0/fifo0_bit11" LOC = "SLICE_X78Y55";
INST "ram2_ddr2_data_path/data_read0/fifo1_bit11" LOC = "SLICE_X76Y55";
INST "ram2_ddr2_data_path/data_read0/fifo0_bit12" LOC = "SLICE_X78Y68";
INST "ram2_ddr2_data_path/data_read0/fifo1_bit12" LOC = "SLICE_X76Y68";
INST "ram2_ddr2_data_path/data_read0/fifo0_bit13" LOC = "SLICE_X78Y69";
INST "ram2_ddr2_data_path/data_read0/fifo1_bit13" LOC = "SLICE_X76Y69";
INST "ram2_ddr2_data_path/data_read0/fifo0_bit14" LOC = "SLICE_X78Y72";
INST "ram2_ddr2_data_path/data_read0/fifo1_bit14" LOC = "SLICE_X76Y72";
INST "ram2_ddr2_data_path/data_read0/fifo0_bit15" LOC = "SLICE_X78Y73";
INST "ram2_ddr2_data_path/data_read0/fifo1_bit15" LOC = "SLICE_X76Y73";
INST "ram2_ddr2_data_path/data_read_controller0/fifo_10_wr_addr_inst/bit0" LOC = "SLICE_X79Y72";
INST "ram2_ddr2_data_path/data_read_controller0/fifo_10_wr_addr_inst/bit1" LOC = "SLICE_X79Y72";
INST "ram2_ddr2_data_path/data_read_controller0/fifo_10_wr_addr_inst/bit2" LOC = "SLICE_X79Y73";
INST "ram2_ddr2_data_path/data_read_controller0/fifo_10_wr_addr_inst/bit3" LOC = "SLICE_X79Y73";
INST "ram2_ddr2_data_path/data_read_controller0/fifo_10_wr_en_inst/delay_ff" LOC = "SLICE_X77Y53";
INST "ram2_ddr2_data_path/data_read_controller0/fifo_11_wr_addr_inst/bit0" LOC = "SLICE_X77Y72";
INST "ram2_ddr2_data_path/data_read_controller0/fifo_11_wr_addr_inst/bit1" LOC = "SLICE_X77Y72";
INST "ram2_ddr2_data_path/data_read_controller0/fifo_11_wr_addr_inst/bit2" LOC = "SLICE_X77Y73";
INST "ram2_ddr2_data_path/data_read_controller0/fifo_11_wr_addr_inst/bit3" LOC = "SLICE_X77Y73";
INST "ram2_ddr2_data_path/data_read_controller0/fifo_11_wr_en_inst/delay_ff_1" LOC = "SLICE_X79Y53";
INST "ram2_ddr2_iobs/datapath_ddr2_iobs0/dqs0_lut_delay1" LOC = SLICE_X79Y85 ;
INST "ram2_ddr2_iobs/datapath_ddr2_iobs0/dqs0_lut_delay2" LOC = SLICE_X79Y85 ;
INST "ram2_ddr2_iobs/datapath_ddr2_iobs0/dqs0_lut_delay3" LOC = SLICE_X79Y84 ;
INST "ram2_ddr2_iobs/datapath_ddr2_iobs0/dqs0_lut_delay4" LOC = SLICE_X79Y84 ;
INST "ram2_ddr2_iobs/datapath_ddr2_iobs0/dqs1_lut_delay1" LOC = SLICE_X79Y69 ;
INST "ram2_ddr2_iobs/datapath_ddr2_iobs0/dqs1_lut_delay2" LOC = SLICE_X79Y69 ; # XXY42
INST "ram2_ddr2_iobs/datapath_ddr2_iobs0/dqs1_lut_delay3" LOC = SLICE_X79Y68 ;
INST "ram2_ddr2_iobs/datapath_ddr2_iobs0/dqs1_lut_delay4" LOC = SLICE_X79Y68 ; # XXY42
INST "ram2_ddr2_data_path/data_read_controller0/rst_dqs_div_lut_delay1" LOC = SLICE_X74Y85 ;
INST "ram2_ddr2_data_path/data_read_controller0/rst_dqs_div_lut_delay2" LOC = SLICE_X74Y85 ;
INST "ram2_ddr2_data_path/data_read_controller0/rst_dqs_div_lut_delay3" LOC = SLICE_X74Y84 ;
INST "ram2_ddr2_data_path/data_read_controller0/rst_dqs_div_lut_delay4" LOC = SLICE_X74Y84 ;
#--******************************************************************************************************+
NET "ram1_ddr2_iobs/datapath_ddr2_iobs0/dqs0_in" MAXDELAY = 2000ps ; # 600ps
NET "ram1_ddr2_iobs/datapath_ddr2_iobs0/dqs1_in" MAXDELAY = 2000ps ; # 600ps
NET "ram1_ddr2_dq_in_rising*" MAXDELAY = 600ps ;
NET "ram1_ddr2_dq_in_falling*" MAXDELAY = 600ps ;
#NET "ram1_ddr2_dqs_int_delay_in*" MAXDELAY = 600ps
NET "ram1_ddr2_data_path/data_read_controller0/fifo_00_wr_en_inst/din_delay" MAXDELAY = 400ps ;
NET "ram1_ddr2_data_path/data_read_controller0/fifo_01_wr_en_inst/din_delay_1" MAXDELAY = 400ps ;
NET "ram1_ddr2_data_path/data_read_controller0/fifo_10_wr_en_inst/din_delay" MAXDELAY = 400ps ;
NET "ram1_ddr2_data_path/data_read_controller0/fifo_11_wr_en_inst/din_delay_1" MAXDELAY = 400ps ;
NET "ram1_ddr2_data_path/data_read_controller0/fifo_11_wr_en_inst/dout0" MAXDELAY = 400ps ;
NET "ram1_ddr2_data_path/fifo*_wr_en" MAXDELAY = 1000ps ;
NET "ram1_ddr2_data_path/fifo*_wr_addr*" MAXDELAY = 2350ps ;
NET "ram1_ddr2_data_path/fifo*_rd_addr*" MAXDELAY = 2350ps ;
NET "ram1_ddr2_data_path/data_read0/fifo*rd_addr_r*" MAXDELAY = 2350ps ;
NET "ram1_ddr2_data_path/data_read0/fifo_*_data_out*" MAXDELAY = 2500ps ;
NET "ram1_ddr2_data_path/reset_r*" MAXDELAY = 1500ps ;
NET "ram1_controller/rst_dqs_div_r*" MAXDELAY = 800ps ;
NET "ram1_ddr2_rst_dqs_div_int*" MAXDELAY = 800ps ;
NET "ram1_controller/dqs_reset*" MAXDELAY = 1800ps ;
NET "ram1_ddr2_rst_dqs_div" MAXDELAY = 800ps ;
INST "ram1_ddr2_iobs/datapath_ddr2_iobs0/dqs0_lut_delay1" LOC = SLICE_X79Y11 ;
INST "ram1_ddr2_iobs/datapath_ddr2_iobs0/dqs0_lut_delay2" LOC = SLICE_X79Y11 ;
INST "ram1_ddr2_iobs/datapath_ddr2_iobs0/dqs0_lut_delay3" LOC = SLICE_X79Y10 ;
INST "ram1_ddr2_iobs/datapath_ddr2_iobs0/dqs0_lut_delay4" LOC = SLICE_X79Y10 ;
INST "ram1_ddr2_iobs/datapath_ddr2_iobs0/dqs1_lut_delay1" LOC = SLICE_X79Y27 ;
INST "ram1_ddr2_iobs/datapath_ddr2_iobs0/dqs1_lut_delay2" LOC = SLICE_X79Y27 ;
INST "ram1_ddr2_iobs/datapath_ddr2_iobs0/dqs1_lut_delay3" LOC = SLICE_X79Y26 ;
INST "ram1_ddr2_iobs/datapath_ddr2_iobs0/dqs1_lut_delay4" LOC = SLICE_X79Y26 ;
INST "ram1_ddr2_data_path/data_read_controller0/rst_dqs_div_lut_delay1" LOC = SLICE_X74Y25 ;
INST "ram1_ddr2_data_path/data_read_controller0/rst_dqs_div_lut_delay2" LOC = SLICE_X74Y25 ;
INST "ram1_ddr2_data_path/data_read_controller0/rst_dqs_div_lut_delay3" LOC = SLICE_X74Y24 ;
INST "ram1_ddr2_data_path/data_read_controller0/rst_dqs_div_lut_delay4" LOC = SLICE_X74Y24 ;
INST "ram1_ddr2_data_path/data_read0/fifo0_bit0" LOC = "SLICE_X78Y12";
INST "ram1_ddr2_data_path/data_read0/fifo1_bit0" LOC = "SLICE_X76Y12";
INST "ram1_ddr2_data_path/data_read0/fifo0_bit1" LOC = "SLICE_X78Y13";
INST "ram1_ddr2_data_path/data_read0/fifo1_bit1" LOC = "SLICE_X76Y13";
INST "ram1_ddr2_data_path/data_read0/fifo0_bit2" LOC = "SLICE_X78Y14";
INST "ram1_ddr2_data_path/data_read0/fifo1_bit2" LOC = "SLICE_X76Y14";
INST "ram1_ddr2_data_path/data_read0/fifo0_bit3" LOC = "SLICE_X78Y15";
INST "ram1_ddr2_data_path/data_read0/fifo1_bit3" LOC = "SLICE_X76Y15";
INST "ram1_ddr2_data_path/data_read0/fifo0_bit4" LOC = "SLICE_X78Y16";
INST "ram1_ddr2_data_path/data_read0/fifo1_bit4" LOC = "SLICE_X76Y16";
INST "ram1_ddr2_data_path/data_read0/fifo0_bit5" LOC = "SLICE_X78Y17";
INST "ram1_ddr2_data_path/data_read0/fifo1_bit5" LOC = "SLICE_X76Y17";
INST "ram1_ddr2_data_path/data_read0/fifo0_bit6" LOC = "SLICE_X78Y18";
INST "ram1_ddr2_data_path/data_read0/fifo1_bit6" LOC = "SLICE_X76Y18";
INST "ram1_ddr2_data_path/data_read0/fifo0_bit7" LOC = "SLICE_X78Y19";
INST "ram1_ddr2_data_path/data_read0/fifo1_bit7" LOC = "SLICE_X76Y19";
INST "ram1_ddr2_data_path/data_read_controller0/fifo_00_wr_addr_inst/bit0" LOC = "SLICE_X79Y18";
INST "ram1_ddr2_data_path/data_read_controller0/fifo_00_wr_addr_inst/bit1" LOC = "SLICE_X79Y18";
INST "ram1_ddr2_data_path/data_read_controller0/fifo_00_wr_addr_inst/bit2" LOC = "SLICE_X79Y19";
INST "ram1_ddr2_data_path/data_read_controller0/fifo_00_wr_addr_inst/bit3" LOC = "SLICE_X79Y19";
INST "ram1_ddr2_data_path/data_read_controller0/fifo_00_wr_en_inst/delay_ff" LOC = "SLICE_X77Y12";
INST "ram1_ddr2_data_path/data_read_controller0/fifo_01_wr_addr_inst/bit0" LOC = "SLICE_X77Y18";
INST "ram1_ddr2_data_path/data_read_controller0/fifo_01_wr_addr_inst/bit1" LOC = "SLICE_X77Y18";
INST "ram1_ddr2_data_path/data_read_controller0/fifo_01_wr_addr_inst/bit2" LOC = "SLICE_X77Y19";
INST "ram1_ddr2_data_path/data_read_controller0/fifo_01_wr_addr_inst/bit3" LOC = "SLICE_X77Y19";
INST "ram1_ddr2_data_path/data_read_controller0/fifo_01_wr_en_inst/delay_ff_1" LOC = "SLICE_X79Y12";
INST "ram1_ddr2_data_path/data_read0/fifo0_bit8" LOC = "SLICE_X78Y26";
INST "ram1_ddr2_data_path/data_read0/fifo1_bit8" LOC = "SLICE_X76Y26";
INST "ram1_ddr2_data_path/data_read0/fifo0_bit9" LOC = "SLICE_X78Y27";
INST "ram1_ddr2_data_path/data_read0/fifo1_bit9" LOC = "SLICE_X76Y27";
INST "ram1_ddr2_data_path/data_read0/fifo0_bit10" LOC = "SLICE_X78Y40";
INST "ram1_ddr2_data_path/data_read0/fifo1_bit10" LOC = "SLICE_X76Y40";
INST "ram1_ddr2_data_path/data_read0/fifo0_bit11" LOC = "SLICE_X78Y41";
INST "ram1_ddr2_data_path/data_read0/fifo1_bit11" LOC = "SLICE_X76Y41";
INST "ram1_ddr2_data_path/data_read0/fifo0_bit12" LOC = "SLICE_X78Y42";
INST "ram1_ddr2_data_path/data_read0/fifo1_bit12" LOC = "SLICE_X76Y42";
INST "ram1_ddr2_data_path/data_read0/fifo0_bit13" LOC = "SLICE_X78Y43";
INST "ram1_ddr2_data_path/data_read0/fifo1_bit13" LOC = "SLICE_X76Y43";
INST "ram1_ddr2_data_path/data_read0/fifo0_bit14" LOC = "SLICE_X78Y48";
INST "ram1_ddr2_data_path/data_read0/fifo1_bit14" LOC = "SLICE_X76Y48";
INST "ram1_ddr2_data_path/data_read0/fifo0_bit15" LOC = "SLICE_X78Y49";
INST "ram1_ddr2_data_path/data_read0/fifo1_bit15" LOC = "SLICE_X76Y49";
INST "ram1_ddr2_data_path/data_read_controller0/fifo_10_wr_addr_inst/bit0" LOC = "SLICE_X79Y48";
INST "ram1_ddr2_data_path/data_read_controller0/fifo_10_wr_addr_inst/bit1" LOC = "SLICE_X79Y48";
INST "ram1_ddr2_data_path/data_read_controller0/fifo_10_wr_addr_inst/bit2" LOC = "SLICE_X79Y49";
INST "ram1_ddr2_data_path/data_read_controller0/fifo_10_wr_addr_inst/bit3" LOC = "SLICE_X79Y49";
INST "ram1_ddr2_data_path/data_read_controller0/fifo_10_wr_en_inst/delay_ff" LOC = "SLICE_X77Y26";
INST "ram1_ddr2_data_path/data_read_controller0/fifo_11_wr_addr_inst/bit0" LOC = "SLICE_X77Y48";
INST "ram1_ddr2_data_path/data_read_controller0/fifo_11_wr_addr_inst/bit1" LOC = "SLICE_X77Y48";
INST "ram1_ddr2_data_path/data_read_controller0/fifo_11_wr_addr_inst/bit2" LOC = "SLICE_X77Y49";
INST "ram1_ddr2_data_path/data_read_controller0/fifo_11_wr_addr_inst/bit3" LOC = "SLICE_X77Y49";
INST "ram1_ddr2_data_path/data_read_controller0/fifo_11_wr_en_inst/delay_ff_1" LOC = "SLICE_X79Y26";
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "adc1_clk_out_n" LOC = "M6" | IOSTANDARD = LVDS_25 | SLEW = FAST ;
NET "adc1_clk_out_p" LOC = "M5" | IOSTANDARD = LVDS_25 | SLEW = FAST ;
NET "adc1_dco_n" LOC = "AA11" | IOSTANDARD = LVDS_25 ;
NET "adc1_dco_p" LOC = "Y11" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_n<0>" LOC = "Y3" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_n<10>" LOC = "R5" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_n<11>" LOC = "P2" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_n<12>" LOC = "P5" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_n<13>" LOC = "N2" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_n<14>" LOC = "M2" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_n<15>" LOC = "N6" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_n<1>" LOC = "W4" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_n<2>" LOC = "W2" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_n<3>" LOC = "V2" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_n<4>" LOC = "V4" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_n<5>" LOC = "T2" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_n<6>" LOC = "V5" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_n<7>" LOC = "U4" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_n<8>" LOC = "T6" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_n<9>" LOC = "R2" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_p<0>" LOC = "Y2" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_p<10>" LOC = "P6" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_p<11>" LOC = "P1" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_p<12>" LOC = "P4" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_p<13>" LOC = "N1" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_p<14>" LOC = "M1" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_p<15>" LOC = "N5" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_p<1>" LOC = "W3" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_p<2>" LOC = "W1" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_p<3>" LOC = "V1" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_p<4>" LOC = "V3" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_p<5>" LOC = "T1" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_p<6>" LOC = "U5" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_p<7>" LOC = "T4" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_p<8>" LOC = "T5" | IOSTANDARD = LVDS_25 ;
NET "adc1_din_p<9>" LOC = "R1" | IOSTANDARD = LVDS_25 ;
NET "adc2_clk_out_n" LOC = "C3" | IOSTANDARD = LVDS_25 | SLEW = FAST ;
NET "adc2_clk_out_p" LOC = "C4" | IOSTANDARD = LVDS_25 | SLEW = FAST ;
NET "adc2_dco_n" LOC = "B11" | IOSTANDARD = LVDS_25 ;
NET "adc2_dco_p" LOC = "A11" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_n<0>" LOC = "L1" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_n<10>" LOC = "G1" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_n<11>" LOC = "G3" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_n<12>" LOC = "F2" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_n<13>" LOC = "E1" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_n<14>" LOC = "D1" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_n<15>" LOC = "D3" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_n<1>" LOC = "K1" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_n<2>" LOC = "L3" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_n<3>" LOC = "K3" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_n<4>" LOC = "K5" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_n<5>" LOC = "J1" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_n<6>" LOC = "J4" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_n<7>" LOC = "J5" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_n<8>" LOC = "H1" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_n<9>" LOC = "H5" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_p<0>" LOC = "L2" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_p<10>" LOC = "G2" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_p<11>" LOC = "G4" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_p<12>" LOC = "F3" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_p<13>" LOC = "E2" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_p<14>" LOC = "C1" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_p<15>" LOC = "D2" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_p<1>" LOC = "K2" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_p<2>" LOC = "L4" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_p<3>" LOC = "K4" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_p<4>" LOC = "K6" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_p<5>" LOC = "J2" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_p<6>" LOC = "H4" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_p<7>" LOC = "J6" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_p<8>" LOC = "H2" | IOSTANDARD = LVDS_25 ;
NET "adc2_din_p<9>" LOC = "G5" | IOSTANDARD = LVDS_25 ;
NET "ddr1_address<0>" LOC = "AB18" | IOSTANDARD = SSTL18_I ;
NET "ddr1_address<10>" LOC = "W17" | IOSTANDARD = SSTL18_I ;
NET "ddr1_address<11>" LOC = "AA15" | IOSTANDARD = SSTL18_I ;
NET "ddr1_address<12>" LOC = "V14" | IOSTANDARD = SSTL18_I ;
NET "ddr1_address<13>" LOC = "Y13" | IOSTANDARD = SSTL18_I ;
NET "ddr1_address<14>" LOC = "AA16" | IOSTANDARD = SSTL18_I ;
NET "ddr1_address<15>" LOC = "AB16" | IOSTANDARD = SSTL18_I ;
NET "ddr1_address<1>" LOC = "AA18" | IOSTANDARD = SSTL18_I ;
NET "ddr1_address<2>" LOC = "U17" | IOSTANDARD = SSTL18_I ;
NET "ddr1_address<3>" LOC = "V17" | IOSTANDARD = SSTL18_I ;
NET "ddr1_address<4>" LOC = "AA17" | IOSTANDARD = SSTL18_I ;
NET "ddr1_address<5>" LOC = "U16" | IOSTANDARD = SSTL18_I ;
NET "ddr1_address<6>" LOC = "Y17" | IOSTANDARD = SSTL18_I ;
NET "ddr1_address<7>" LOC = "W16" | IOSTANDARD = SSTL18_I ;
NET "ddr1_address<8>" LOC = "V16" | IOSTANDARD = SSTL18_I ;
NET "ddr1_address<9>" LOC = "AB15" | IOSTANDARD = SSTL18_I ;
NET "ddr1_ba2_reserve" LOC = "U14" | IOSTANDARD = SSTL18_I ;
NET "ddr1_ba<0>" LOC = "Y18" | IOSTANDARD = SSTL18_I ;
NET "ddr1_ba<1>" LOC = "W14" | IOSTANDARD = SSTL18_I ;
NET "ddr1_casb" LOC = "U13" | IOSTANDARD = SSTL18_I ;
NET "ddr1_cke" LOC = "V19" | IOSTANDARD = SSTL18_I ;
NET "ddr1_clk" LOC = "W22" | IOSTANDARD = SSTL18_I ;
NET "ddr1_clkb" LOC = "Y22" | IOSTANDARD = SSTL18_I ;
NET "ddr1_csb" LOC = "Y21" | IOSTANDARD = SSTL18_I ;
NET "ddr1_dm<0>" LOC = "U21" | IOSTANDARD = SSTL18_I ;
NET "ddr1_dm<1>" LOC = "N20" | IOSTANDARD = SSTL18_I ;
NET "ddr1_dq<0>" LOC = "W20" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr1_dq<10>" LOC = "N21" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr1_dq<11>" LOC = "N22" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr1_dq<12>" LOC = "M17" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr1_dq<13>" LOC = "M18" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr1_dq<14>" LOC = "L21" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr1_dq<15>" LOC = "M21" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr1_dq<1>" LOC = "W21" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr1_dq<2>" LOC = "V20" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr1_dq<3>" LOC = "U19" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr1_dq<4>" LOC = "V21" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr1_dq<5>" LOC = "V22" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr1_dq<6>" LOC = "U18" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr1_dq<7>" LOC = "T17" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr1_dq<8>" LOC = "T21" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr1_dq<9>" LOC = "T22" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr1_dqs<0>" LOC = "R18" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE | PULLDOWN ;
NET "ddr1_dqs<1>" LOC = "M20" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE | PULLDOWN ;
NET "ddr1_dqs_reserve<0>" LOC = "T18" | IOSTANDARD = SSTL18_I ;
NET "ddr1_dqs_reserve<1>" LOC = "M19" | IOSTANDARD = SSTL18_I ;
NET "ddr1_ODT0" LOC = "AA13" | IOSTANDARD = SSTL18_I ;
NET "ddr1_rasb" LOC = "V13" | IOSTANDARD = SSTL18_I ;
NET "ddr1_rst_dqs_div_iob" LOC = "W15" | IOSTANDARD = SSTL18_I ;
NET "ddr1_web" LOC = "W13" | IOSTANDARD = SSTL18_I ;
NET "ddr2_address<0>" LOC = "D18" | IOSTANDARD = SSTL18_I ;
NET "ddr2_address<10>" LOC = "E17" | IOSTANDARD = SSTL18_I ;
NET "ddr2_address<11>" LOC = "F17" | IOSTANDARD = SSTL18_I ;
NET "ddr2_address<12>" LOC = "A13" | IOSTANDARD = SSTL18_I ;
NET "ddr2_address<13>" LOC = "B14" | IOSTANDARD = SSTL18_I ;
NET "ddr2_address<14>" LOC = "A16" | IOSTANDARD = SSTL18_I ;
NET "ddr2_address<15>" LOC = "B16" | IOSTANDARD = SSTL18_I ;
NET "ddr2_address<1>" LOC = "D14" | IOSTANDARD = SSTL18_I ;
NET "ddr2_address<2>" LOC = "C18" | IOSTANDARD = SSTL18_I ;
NET "ddr2_address<3>" LOC = "E16" | IOSTANDARD = SSTL18_I ;
NET "ddr2_address<4>" LOC = "B18" | IOSTANDARD = SSTL18_I ;
NET "ddr2_address<5>" LOC = "F13" | IOSTANDARD = SSTL18_I ;
NET "ddr2_address<6>" LOC = "C17" | IOSTANDARD = SSTL18_I ;
NET "ddr2_address<7>" LOC = "E15" | IOSTANDARD = SSTL18_I ;
NET "ddr2_address<8>" LOC = "B17" | IOSTANDARD = SSTL18_I ;
NET "ddr2_address<9>" LOC = "A14" | IOSTANDARD = SSTL18_I ;
NET "ddr2_ba2_reserve" LOC = "E14" | IOSTANDARD = SSTL18_I ;
NET "ddr2_ba<0>" LOC = "B19" | IOSTANDARD = SSTL18_I ;
NET "ddr2_ba<1>" LOC = "D15" | IOSTANDARD = SSTL18_I ;
NET "ddr2_casb" LOC = "B13" | IOSTANDARD = SSTL18_I ;
NET "ddr2_cke" LOC = "F16" | IOSTANDARD = SSTL18_I ;
NET "ddr2_clk" LOC = "B15" | IOSTANDARD = SSTL18_I ;
NET "ddr2_clkb" LOC = "A15" | IOSTANDARD = SSTL18_I ;
NET "ddr2_csb" LOC = "C22" | IOSTANDARD = SSTL18_I ;
NET "ddr2_dm<0>" LOC = "D21" | IOSTANDARD = SSTL18_I ;
NET "ddr2_dm<1>" LOC = "G19" | IOSTANDARD = SSTL18_I ;
NET "ddr2_dq<0>" LOC = "E22" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr2_dq<10>" LOC = "K20" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr2_dq<11>" LOC = "K22" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr2_dq<12>" LOC = "G22" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr2_dq<13>" LOC = "G21" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr2_dq<14>" LOC = "F20" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr2_dq<15>" LOC = "F21" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr2_dq<1>" LOC = "E21" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr2_dq<2>" LOC = "E20" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr2_dq<3>" LOC = "E19" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr2_dq<4>" LOC = "F18" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr2_dq<5>" LOC = "E18" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr2_dq<6>" LOC = "D20" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr2_dq<7>" LOC = "D19" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr2_dq<8>" LOC = "K21" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr2_dq<9>" LOC = "L18" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
NET "ddr2_dqs<0>" LOC = "G17" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE | PULLDOWN ;
NET "ddr2_dqs<1>" LOC = "L19" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE | PULLDOWN ;
NET "ddr2_dqs_reserve<0>" LOC = "G18" | IOSTANDARD = SSTL18_I ;
NET "ddr2_dqs_reserve<1>" LOC = "L20" | IOSTANDARD = SSTL18_I ;
NET "ddr2_ODT0" LOC = "C13" | IOSTANDARD = SSTL18_I ;
NET "ddr2_rasb" LOC = "E12" | IOSTANDARD = SSTL18_I ;
NET "ddr2_rst_dqs_div_iob" LOC = "D13" | IOSTANDARD = SSTL18_I ;
NET "ddr2_web" LOC = "D17" | IOSTANDARD = SSTL18_I ;
NET "FPGA_ADC12_BUSY_L" LOC = "AB10" | SLEW = FAST ;
NET "FPGA_ADC12_EVENT_END_L" LOC = "AA10" | SLEW = FAST ;
NET "FPGA_ADC1_TRIGGER_L" LOC = "AA8" | SLEW = FAST ;
NET "FPGA_ADC2_TRIGGER_L" LOC = "Y10" | SLEW = FAST ;
NET "FPGA_ADC_B1_SAMPLE_ENABLED_L" LOC = "V7" | PULLUP ; # prot5
NET "FPGA_ADC_B2_SAMPLE_ENABLED_L" LOC = "V8" | PULLUP ; # prot6
NET "FPGA_ADC_SAMPLE_START_L" LOC = "V9" | PULLUP ; # prot7
NET "FPGA_ADC_SAMPLE_STOP_L" LOC = "V10" | PULLUP ; # prot8 MCA NOT_FIRST_SCAN Flag
NET "FPGA_ADC_SAMPLE_LOGIC_RESET_L" LOC = "W8" | PULLUP ;
NET "FPGA_ADC_TIMESTAMP_CLR_L" LOC = "W6" ; # prot11
NET "FPGA_ADC_LED_TIMESTAMP_OVERFLOW_PULSE_L" LOC = "Y6" ; # prot15
NET "FPGA_LEMO_USER_IN_L" LOC = "W5" ; # prot10 wird als Veto genutzt
NET "FPGA_ADC_PROT13_L" LOC = "W9" | PULLUP ; # prot13 MCA LNE
NET "FPGA_ADC_PROT14_L" LOC = "W10" | PULLUP ; # prot14 MCA Mode Enable
NET "CON_WITH_ADC12_OUT1_L" LOC = "B7" ; # out irq to next upper
NET "CON_WITH_ADC12_IN1_L" LOC = "A7" ; # in irq from next upper
NET "CON_WITH_ADC12_OUT2_L" LOC = "E8" ;
NET "CON_WITH_ADC12_IN2_L" LOC = "D8" ;
NET "CON_WITH_ADC78_IN1_L" LOC = "AA4" ; # in irq from next lower
NET "CON_WITH_ADC78_OUT1_L" LOC = "AA5" ; # out irq to next lower
NET "CON_WITH_ADC78_IN2_L" LOC = "AB4" ;
NET "CON_WITH_ADC78_OUT2_L" LOC = "AB5" ;
NET "FPGA_ID_D0" LOC = "AB7" ;
NET "FPGA_ID_D1" LOC = "AA7" ;
NET "i_fpga_reset_l" LOC = "U6" | PULLUP ; # prot0
NET "i_fpga_key_reset_l" LOC = "Y5" | PULLUP ; # prot9
NET "i_fpga_sel_l" LOC = "AB8" | PULLUP;
NET "i_fpga_ds_l" LOC = "U7" | PULLUP; # prot1
NET "i_fpga_write_l" LOC = "U10"| PULLUP ; # prot2
NET "i_fpga_block_l" LOC = "U11" | PULLUP; # prot3
NET "wst_out_l_oreg" LOC = "V6" | SLEW = FAST | DRIVE = 12 ; # prot4
NET "io_fpga_ad<0>" LOC = "A10" | SLEW = FAST | DRIVE = 12 ;
NET "io_fpga_ad<10>" LOC = "B5" | SLEW = FAST | DRIVE = 12 ;
NET "io_fpga_ad<11>" LOC = "B4" | SLEW = FAST | DRIVE = 12 ;
NET "io_fpga_ad<12>" LOC = "C11" | SLEW = FAST | DRIVE = 12 ;
NET "io_fpga_ad<13>" LOC = "C10" | SLEW = FAST | DRIVE = 12 ;
NET "io_fpga_ad<14>" LOC = "C7" | SLEW = FAST | DRIVE = 12 ;
NET "io_fpga_ad<15>" LOC = "C6" | SLEW = FAST | DRIVE = 12 ;
NET "io_fpga_ad<16>" LOC = "C5" | SLEW = FAST | DRIVE = 12 ;
NET "io_fpga_ad<17>" LOC = "D11" | SLEW = FAST | DRIVE = 12 ;
NET "io_fpga_ad<18>" LOC = "D10" | SLEW = FAST | DRIVE = 12 ;
NET "io_fpga_ad<19>" LOC = "D9" | SLEW = FAST | DRIVE = 12 ;
NET "io_fpga_ad<1>" LOC = "A9" | SLEW = FAST | DRIVE = 12 ;
NET "io_fpga_ad<20>" LOC = "D7" | SLEW = FAST | DRIVE = 12 ;
NET "io_fpga_ad<21>" LOC = "D6" | SLEW = FAST | DRIVE = 12 ;
NET "io_fpga_ad<22>" LOC = "D5" | SLEW = FAST | DRIVE = 12 ;
NET "io_fpga_ad<23>" LOC = "E11" | SLEW = FAST | DRIVE = 12 ;
NET "io_fpga_ad<24>" LOC = "E10" | SLEW = FAST | DRIVE = 12 ;
NET "io_fpga_ad<25>" LOC = "E9" | SLEW = FAST | DRIVE = 12 ;
NET "io_fpga_ad<26>" LOC = "E7" | SLEW = FAST | DRIVE = 12 ;
NET "io_fpga_ad<27>" LOC = "E6" | SLEW = FAST | DRIVE = 12 ;
NET "io_fpga_ad<28>" LOC = "F11" | SLEW = FAST | DRIVE = 12 ;
NET "io_fpga_ad<29>" LOC = "F10" | SLEW = FAST | DRIVE = 12 ;
NET "io_fpga_ad<2>" LOC = "A8" | SLEW = FAST | DRIVE = 12 ;
NET "io_fpga_ad<30>" LOC = "F9" | SLEW = FAST | DRIVE = 12 ;
NET "io_fpga_ad<31>" LOC = "F7" | SLEW = FAST | DRIVE = 12 ;
NET "io_fpga_ad<3>" LOC = "A5" | SLEW = FAST | DRIVE = 12 ;
NET "io_fpga_ad<4>" LOC = "A4" | SLEW = FAST | DRIVE = 12 ;
NET "io_fpga_ad<5>" LOC = "A3" | SLEW = FAST | DRIVE = 12 ;
NET "io_fpga_ad<6>" LOC = "B10" | SLEW = FAST | DRIVE = 12 ;
NET "io_fpga_ad<7>" LOC = "B9" | SLEW = FAST | DRIVE = 12 ;
NET "io_fpga_ad<8>" LOC = "B8" | SLEW = FAST | DRIVE = 12 ;
NET "io_fpga_ad<9>" LOC = "B6" | SLEW = FAST | DRIVE = 12 ;
NET "system_adc_clk_n" LOC = "AA12" | IOSTANDARD = LVDS_25 ;
NET "system_adc_clk_p" LOC = "AB12" | IOSTANDARD = LVDS_25 ;
NET "system_clk_n" LOC = "B12" | IOSTANDARD = LVDS_25 ;
NET "system_clk_p" LOC = "C12" | IOSTANDARD = LVDS_25 ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE
// 06/06 @ 10:12:07
NET "ram1_ddr2_iobs/datapath_ddr2_iobs0/dqs0_in"
ROUTE="{3;1;3s1000fg456;4c3cc268!-1;78200;-43440;S!0;-159;0!1;-1632;"
"-10208!1;-33;1777!2;-2809;-11239!3;-12136;-612!4;1009;1447!5;10269;38891!"
"6;327;0;L!7;226;-50240!9;1713;-7143!9;1705;-7135!9;1713;-3767!9;1705;"
"-3759!9;1713;-143!9;1705;-135!9;1713;3233!9;1705;3241!10;120;-161;L!10;"
"120;159;L!11;128;-161;L!11;128;159;L!12;120;-161;L!12;120;159;L!13;128;"
"-161;L!13;128;159;L!14;120;-161;L!14;120;159;L!15;128;-161;L!15;128;159;L"
"!16;120;-161;L!16;120;159;L!17;128;-161;L!17;128;159;L!}";
NET "ram1_ddr2_iobs/datapath_ddr2_iobs0/dqs1_in"
ROUTE="{3;1;3s1000fg456;ece908db!-1;78200;-6056;S!0;-159;0!1;-1724;-1736!"
"1;-33;1777!2;-3476;-11784!3;-12136;-612!4;256;-13936!5;9804;7968!6;1512;"
"-2648!7;677;1195!7;677;-39813!7;691;-19317!8;327;0;L!9;1727;-3527!9;1719;"
"-3519!9;1727;-7151!9;1719;-7143!10;1719;-143!10;1727;-151!11;1705;3241!"
"11;1713;6609!11;1705;6617!11;1713;3233!13;120;159;L!14;128;159;L!15;120;"
"-161;L!16;128;-161;L!17;128;-161;L!17;128;159;L!18;120;159;L!18;120;-161;"
"L!19;128;-161;L!19;128;159;L!20;120;-161;L!20;120;159;L!21;128;-161;L!21;"
"128;159;L!22;120;159;L!22;120;-161;L!}";
NET "ram2_ddr2_iobs/datapath_ddr2_iobs0/dqs0_in"
ROUTE="{3;1;3s1000fg456;8e10cbae!-1;78200;48456;S!0;-159;0!1;-33;1777!2;"
"-1576;7344!2;-12136;-612!3;-2816;3676!4;9732;-53400!5;993;1459!6;749;"
"62563!7;327;0;L!8;1727;-7151!8;1719;-7143!8;1727;-3527!8;1719;-3519!8;"
"1727;-151!8;1719;-143!8;1727;6601!8;1719;6609!10;120;-161;L!10;120;159;L!"
"11;128;-161;L!11;128;159;L!12;120;-161;L!12;120;159;L!13;128;-161;L!13;"
"128;159;L!14;120;-161;L!14;120;159;L!15;128;-161;L!15;128;159;L!16;120;"
"159;L!16;120;-161;L!17;128;159;L!17;128;-161;L!}";
NET "ram2_ddr2_iobs/datapath_ddr2_iobs0/dqs1_in"
ROUTE="{3;1;3s1000fg456;99c8b0b4!-1;78200;4320;S!0;-159;0!1;-1692;1736!1;"
"-33;1777!2;-3438;11712!3;-12136;-612!4;216;13568!5;9780;-12736!6;1482;"
"4128!7;715;42147!7;701;21651!8;327;0;L!9;1713;-143!9;1705;-135!9;1713;"
"6609!9;1705;6617!10;1727;-6903!10;1719;-6895!10;1727;-151!10;1719;-143!"
"10;1719;-3519!10;1727;-3527!12;120;-161;L!12;120;159;L!13;128;-161;L!13;"
"128;159;L!14;120;159;L!14;120;-161;L!15;128;159;L!15;128;-161;L!16;120;"
"-161;L!17;128;-161;L!18;120;-161;L!19;128;-161;L!20;128;159;L!20;128;"
"-161;L!21;120;-161;L!21;120;159;L!}";
NET "ram2_ddr2_dq_in_falling<0>"
ROUTE="{3;1;3s1000fg456;91159d71!-1;78200;51496;S!0;-208;-1247!1;-4376;"
"-2748!2;-3921;4059!3;1458;-352!4;167;0;L!}";
NET "ram2_ddr2_dq_in_falling<1>"
ROUTE="{3;1;3s1000fg456;22d15618!-1;78200;51816;S!0;-200;-1575!1;-4416;"
"660!2;-2431;651!3;167;0;L!}";
NET "ram2_ddr2_dq_in_falling<2>"
ROUTE="{3;1;3s1000fg456;4df40e72!-1;78200;55120;S!0;-2043;-592!1;-6173;"
"-65!2;1169;369!3;167;0;L!}";
NET "ram2_ddr2_dq_in_falling<3>"
ROUTE="{3;1;3s1000fg456;40d24bd1!-1;78200;55440;S!0;-200;-1699!1;-4416;"
"784!2;-2431;651!3;167;0;L!}";
#NET "ram2_ddr2_dq_in_falling<4>"
#ROUTE="{3;1;3s1000fg456;6cd94ec0!-1;78200;58496;S!0;-192;2113!1;-4408;"
#"-712!2;-2447;-665!3;0;-1024!4;167;0;L!}";
NET "ram2_ddr2_dq_in_falling<5>"
ROUTE="{3;1;3s1000fg456;7ec24a76!-1;78200;58816;S!0;-200;-1575!1;-4416;"
"660!2;-2431;651!3;167;0;L!}";
NET "ram2_ddr2_dq_in_falling<6>"
ROUTE="{3;1;3s1000fg456;d255f653!-1;78200;65568;S!0;-2043;-912!1;-6173;"
"-65!2;1169;369!3;167;0;L!}";
NET "ram2_ddr2_dq_in_falling<7>"
ROUTE="{3;1;3s1000fg456;7f3336aa!-1;78200;65248;S!0;-200;-1255!1;-4416;"
"660!2;-2431;651!3;167;0;L!}";
NET "ram2_ddr2_dq_in_falling<8>"
ROUTE="{3;1;3s1000fg456;7d207d2!-1;78200;11056;S!0;-200;-1575!1;-4416;"
"660!2;-2431;307!3;167;0;L!}";
NET "ram2_ddr2_dq_in_falling<9>"
ROUTE="{3;1;3s1000fg456;ba0282c2!-1;78200;7360;S!0;-200;-1255!1;-4416;"
"660!2;-2431;307!3;167;0;L!}";
NET "ram2_ddr2_dq_in_falling<10>"
ROUTE="{3;1;3s1000fg456;96c2c681!-1;78200;14112;S!0;-200;-1255!1;-4416;"
"660!2;-2431;307!3;167;0;L!}";
#NET "ram2_ddr2_dq_in_falling<11>"
#ROUTE="{3;1;3s1000fg456;e53c8fe0!-1;78200;10736;S!0;-2043;-592!1;-6173;"
#"-65!2;1169;713!3;167;0;L!}";
NET "ram2_ddr2_dq_in_falling<12>"
ROUTE="{3;1;3s1000fg456;4f0b6976!-1;78200;34616;S!0;-2043;-592!1;-6173;"
"-65!2;1169;369!3;167;0;L!}";
NET "ram2_ddr2_dq_in_falling<13>"
ROUTE="{3;1;3s1000fg456;37c962ec!-1;78200;34936;S!0;-200;-1575!1;-4416;"
"660!2;-2431;651!3;167;0;L!}";
NET "ram2_ddr2_dq_in_falling<14>"
ROUTE="{3;1;3s1000fg456;b6eccd07!-1;78200;41688;S!0;-2043;-912!1;-6173;"
"-65!2;1169;369!3;167;0;L!}";
NET "ram2_ddr2_dq_in_falling<15>"
ROUTE="{3;1;3s1000fg456;9062d6b2!-1;78200;41368;S!0;-200;-1255!1;-4416;"
"660!2;-2431;651!3;167;0;L!}";
NET "ram2_ddr2_dq_in_rising<0>"
ROUTE="{3;1;3s1000fg456;4df40e72!-1;78200;51504;S!0;-2043;-600!1;-1548;"
"304!2;167;0;L!}";
NET "ram2_ddr2_dq_in_rising<1>"
ROUTE="{3;1;3s1000fg456;40d24bd1!-1;78200;51824;S!0;-2067;-928!1;-1524;"
"648!2;0;8!3;167;0;L!}";
NET "ram2_ddr2_dq_in_rising<2>"
ROUTE="{3;1;3s1000fg456;a98db838!-1;78200;55128;S!0;-2067;-608!1;-1524;"
"648!2;0;-336!3;167;0;L!}";
NET "ram2_ddr2_dq_in_rising<3>"
ROUTE="{3;1;3s1000fg456;d3a4e30c!-1;78200;55448;S!0;-1851;1744!1;1828;"
"584!2;-1281;15!3;-3763;-2583!4;1476;-32!5;167;0;L!}";
NET "ram2_ddr2_dq_in_rising<4>"
ROUTE="{3;1;3s1000fg456;90aac99f!-1;78200;58504;S!0;-2043;-600!1;-1548;"
"304!2;167;0;L!}";
NET "ram2_ddr2_dq_in_rising<5>"
ROUTE="{3;1;3s1000fg456;f933645c!-1;78200;58824;S!0;-2067;-928!1;-1524;"
"648!2;0;8!3;167;0;L!}";
NET "ram2_ddr2_dq_in_rising<6>"
ROUTE="{3;1;3s1000fg456;ac374ae0!-1;78200;65576;S!0;-2067;-928!1;-1524;"
"648!2;0;-336!3;167;0;L!}";
NET "ram2_ddr2_dq_in_rising<7>"
ROUTE="{3;1;3s1000fg456;cfb24ace!-1;78200;65256;S!0;-2059;1400!1;-1532;"
"-672!2;0;-680!3;167;0;L!}";
NET "ram2_ddr2_dq_in_rising<8>"
ROUTE="{3;1;3s1000fg456;ada80821!-1;78200;11064;S!0;-1851;1744!1;1828;"
"584!2;-1281;15!3;-3763;-2583!4;1476;-376!5;167;0;L!}";
NET "ram2_ddr2_dq_in_rising<9>"
ROUTE="{3;1;3s1000fg456;9d9bf507!-1;78200;7368;S!0;-2043;-600!1;-1548;"
"304!2;167;0;L!}";
NET "ram2_ddr2_dq_in_rising<10>"
ROUTE="{3;1;3s1000fg456;c827908e!-1;78200;14120;S!0;-2043;-600!1;-1548;"
"304!2;167;0;L!}";
NET "ram2_ddr2_dq_in_rising<11>"
ROUTE="{3;1;3s1000fg456;72420bcc!-1;78200;10744;S!0;-2067;-608!1;-1524;"
"648!2;0;8!3;167;0;L!}";
NET "ram2_ddr2_dq_in_rising<12>"
ROUTE="{3;1;3s1000fg456;a36c7604!-1;78200;34624;S!0;-2067;-608!1;-1524;"
"648!2;0;-336!3;167;0;L!}";
#NET "ram2_ddr2_dq_in_rising<13>"
#ROUTE="{3;1;3s1000fg456;de3b8a2a!-1;78200;34944;S!0;-2059;1080!1;-1532;"
#"-672!2;0;-680!3;167;0;L!}";
NET "ram2_ddr2_dq_in_rising<14>"
ROUTE="{3;1;3s1000fg456;55f2a395!-1;78200;41696;S!0;-2067;-928!1;-1524;"
"648!2;0;-336!3;167;0;L!}";
NET "ram2_ddr2_dq_in_rising<15>"
ROUTE="{3;1;3s1000fg456;e86eaa1!-1;78200;41376;S!0;-2059;1400!1;-1532;"
"-672!2;0;-680!3;167;0;L!}";
// 06/06 @ 10:52:30
NET "ram1_ddr2_dq_in_falling<0>"
ROUTE="{3;1;3s1000fg456;fad98df6!-1;78200;-60904;S!0;-208;-1247!1;-4376;"
"-2748!2;-3921;4059!3;1458;-352!4;167;0;L!}";
NET "ram1_ddr2_dq_in_falling<1>"
ROUTE="{3;1;3s1000fg456;7661b145!-1;78200;-60584;S!0;-200;-1575!1;-4416;"
"660!2;-2431;651!3;167;0;L!}";
NET "ram1_ddr2_dq_in_falling<2>"
ROUTE="{3;1;3s1000fg456;c6f6b973!-1;78200;-57528;S!0;-208;-1247!1;-4376;"
"-2748!2;-3921;4059!3;1458;-352!4;167;0;L!}";
NET "ram1_ddr2_dq_in_falling<3>"
ROUTE="{3;1;3s1000fg456;c9079a8c!-1;78200;-57208;S!0;-200;-1575!1;-4416;"
"660!2;-2431;651!3;167;0;L!}";
NET "ram1_ddr2_dq_in_falling<4>"
ROUTE="{3;1;3s1000fg456;ea4a07da!-1;78200;-53904;S!0;-200;-1379!1;-4416;"
"784!2;-2431;307!3;167;0;L!}";
NET "ram1_ddr2_dq_in_falling<5>"
ROUTE="{3;1;3s1000fg456;38a2ee33!-1;78200;-53584;S!0;-208;-1691!1;-4376;"
"-2872!2;-3921;4307!3;1458;-8!4;167;0;L!}";
NET "ram1_ddr2_dq_in_falling<6>"
ROUTE="{3;1;3s1000fg456;5453682b!-1;78200;-50528;S!0;-2043;-592!1;-6173;"
"-65!2;1169;369!3;167;0;L!}";
NET "ram1_ddr2_dq_in_falling<7>"
ROUTE="{3;1;3s1000fg456;e227436c!-1;78200;-50208;S!0;-200;-1575!1;-4416;"
"660!2;-2431;651!3;167;0;L!}";
NET "ram1_ddr2_dq_in_falling<8>"
ROUTE="{3;1;3s1000fg456;449aea95!-1;78200;-37024;S!0;-200;-1255!1;-4416;"
"660!2;-2431;307!3;167;0;L!}";
NET "ram1_ddr2_dq_in_falling<9>"
ROUTE="{3;1;3s1000fg456;51241ec9!-1;78200;-36704;S!0;-208;-1567!1;-4376;"
"-2748!2;-3921;4059!3;1458;-8!4;167;0;L!}";
NET "ram1_ddr2_dq_in_falling<10>"
ROUTE="{3;1;3s1000fg456;57f25b81!-1;78200;-13144;S!0;-2043;-592!1;-6173;"
"-65!2;1169;369!3;167;0;L!}";
NET "ram1_ddr2_dq_in_falling<11>"
ROUTE="{3;1;3s1000fg456;20aea785!-1;78200;-12824;S!0;-200;-1575!1;-4416;"
"660!2;-2431;651!3;167;0;L!}";
NET "ram1_ddr2_dq_in_falling<12>"
ROUTE="{3;1;3s1000fg456;edddf5a8!-1;78200;-9768;S!0;-200;-1255!1;-4416;"
"660!2;-2431;307!3;167;0;L!}";
#NET "ram1_ddr2_dq_in_falling<13>"
#ROUTE="{3;1;3s1000fg456;c0afe05e!-1;78200;-9448;S!0;-192;1793!1;-4408;"
#"-712!2;-2447;-665!3;0;-680!4;167;0;L!}";
NET "ram1_ddr2_dq_in_falling<14>"
ROUTE="{3;1;3s1000fg456;fcfec485!-1;78200;928;S!0;-200;-1699!1;-4416;784!"
"2;-2431;307!3;167;0;L!}";
NET "ram1_ddr2_dq_in_falling<15>"
ROUTE="{3;1;3s1000fg456;fa72f8a1!-1;78200;-3016;S!0;-1851;2320!1;-6365;"
"647!2;1169;713!3;167;0;L!}";
NET "ram1_ddr2_dq_in_rising<0>"
ROUTE="{3;1;3s1000fg456;bbef0d49!-1;78200;-60896;S!0;-2067;-608!1;-1524;"
"648!2;0;-336!3;167;0;L!}";
NET "ram1_ddr2_dq_in_rising<1>"
ROUTE="{3;1;3s1000fg456;c756ef03!-1;78200;-60576;S!0;-2043;-920!1;-1548;"
"648!2;167;0;L!}";
NET "ram1_ddr2_dq_in_rising<2>"
ROUTE="{3;1;3s1000fg456;f6516412!-1;78200;-57520;S!0;-2043;-600!1;-1548;"
"304!2;167;0;L!}";
NET "ram1_ddr2_dq_in_rising<3>"
ROUTE="{3;1;3s1000fg456;294eb63a!-1;78200;-57200;S!0;-2067;-928!1;-1524;"
"648!2;0;8!3;167;0;L!}";
NET "ram1_ddr2_dq_in_rising<4>"
ROUTE="{3;1;3s1000fg456;ec1b6420!-1;78200;-53896;S!0;-2043;-600!1;-1548;"
"304!2;167;0;L!}";
NET "ram1_ddr2_dq_in_rising<5>"
ROUTE="{3;1;3s1000fg456;70685ea7!-1;78200;-53576;S!0;-2067;-928!1;-1524;"
"648!2;0;8!3;167;0;L!}";
NET "ram1_ddr2_dq_in_rising<6>"
ROUTE="{3;1;3s1000fg456;545d66cf!-1;78200;-50520;S!0;-2067;-608!1;-1524;"
"648!2;0;-336!3;167;0;L!}";
NET "ram1_ddr2_dq_in_rising<7>"
ROUTE="{3;1;3s1000fg456;19b5df66!-1;78200;-50200;S!0;-2059;1080!1;-1532;"
"-672!2;0;-680!3;167;0;L!}";
NET "ram1_ddr2_dq_in_rising<8>"
ROUTE="{3;1;3s1000fg456;74da3fd2!-1;78200;-37016;S!0;-2067;-608!1;-1524;"
"648!2;0;-336!3;167;0;L!}";
NET "ram1_ddr2_dq_in_rising<9>"
ROUTE="{3;1;3s1000fg456;1d6ea017!-1;78200;-36696;S!0;-2043;-920!1;-1548;"
"648!2;167;0;L!}";
NET "ram1_ddr2_dq_in_rising<10>"
ROUTE="{3;1;3s1000fg456;15b0e694!-1;78200;-13136;S!0;-2067;-608!1;-1524;"
"648!2;0;-336!3;167;0;L!}";
#NET "ram1_ddr2_dq_in_rising<11>"
#ROUTE="{3;1;3s1000fg456;6c91ddfb!-1;78200;-12816;S!0;-2059;1080!1;-1532;"
#"-672!2;0;-680!3;167;0;L!}";
NET "ram1_ddr2_dq_in_rising<12>"
ROUTE="{3;1;3s1000fg456;8122bee4!-1;78200;-9760;S!0;-2067;-608!1;-1524;"
"648!2;0;-336!3;167;0;L!}";
NET "ram1_ddr2_dq_in_rising<13>"
ROUTE="{3;1;3s1000fg456;82dd67b9!-1;78200;-9440;S!0;-2043;-920!1;-1548;"
"648!2;167;0;L!}";
NET "ram1_ddr2_dq_in_rising<14>"
ROUTE="{3;1;3s1000fg456;1af6bfb9!-1;78200;936;S!0;-2043;-920!1;-1548;304!"
"2;167;0;L!}";
NET "ram1_ddr2_dq_in_rising<15>"
ROUTE="{3;1;3s1000fg456;77ad7fbf!-1;78200;-3008;S!0;-2059;1400!1;-1532;"
"2272!2;167;0;L!}";
// 06/06 @ 11:05:52
NET "ram1_ddr2_iobs/datapath_ddr2_iobs0/dqs_int_delay_in0"
ROUTE="{3;1;3s1000fg456;f7a7e793!-1;74936;-63664;S!0;-384;1497!1;-12136;"
"-612!2;6825;59387!2;10281;59387!3;200;-50224!4;200;-50224!5;2039;-6928;L!"
"5;2039;3448;L!5;2039;3792;L!5;1879;-7616;L!5;1879;-7272;L!5;1879;-4240;L!"
"5;1879;-3896;L!5;1879;-616;L!5;1879;-272;L!5;1879;2760;L!5;1879;3104;L!6;"
"2039;3448;L!6;2039;3792;L!6;1879;-7616;L!6;1879;-7272;L!6;1879;-4240;L!6;"
"1879;-3896;L!6;1879;-616;L!6;1879;-272;L!6;1879;2760;L!6;1879;3104;L!6;"
"2039;-6928;L!}";
NET "ram1_ddr2_iobs/datapath_ddr2_iobs0/dqs_int_delay_in1"
ROUTE="{3;1;3s1000fg456;839ff060!-1;74936;-36408;S!0;-384;1497!1;-12136;"
"-612!2;6276;28368!2;9732;28368!3;763;1043!3;749;-19205!4;763;1043!4;749;"
"-19205!5;2025;7080;L!5;2025;7424;L!5;1865;-7360;L!5;1865;-7016;L!5;1865;"
"-3984;L!5;1865;-3640;L!5;1865;6392;L!5;1865;6736;L!6;1879;-10992;L!6;"
"1879;-10648;L!6;2039;-10304;L!7;2025;7080;L!7;2025;7424;L!7;1865;-7360;L!"
"7;1865;-7016;L!7;1865;-3984;L!7;1865;-3640;L!7;1865;6392;L!7;1865;6736;L!"
"8;2039;-10304;L!8;1879;-10992;L!8;1879;-10648;L!}";
NET "ram2_ddr2_iobs/datapath_ddr2_iobs0/dqs_int_delay_in0"
ROUTE="{3;1;3s1000fg456;43f880d9!-1;74936;62488;S!0;-384;1497!1;-12136;"
"-612!2;6849;-63157!2;10305;-63157!3;190;51560!3;176;72320!4;190;51560!4;"
"176;72320!5;2025;80;L!5;1865;-608;L!5;1865;-264;L!5;1865;3016;L!5;1865;"
"3360;L!5;1865;6392;L!5;1865;6736;L!6;2039;-6928;L!6;2039;-6584;L!6;1879;"
"-7616;L!6;1879;-7272;L!7;1865;-608;L!7;1865;-264;L!7;1865;3016;L!7;1865;"
"3360;L!7;1865;6392;L!7;1865;6736;L!7;2025;80;L!8;2039;-6928;L!8;2039;"
"-6584;L!8;1879;-7616;L!8;1879;-7272;L!}";
NET "ram2_ddr2_iobs/datapath_ddr2_iobs0/dqs_int_delay_in1"
ROUTE="{3;1;3s1000fg456;ee14069!-1;74936;35232;S!0;-384;1497!1;-12136;"
"-612!2;6300;-32944!2;9756;-32944!3;725;41859!3;725;1099!3;739;21347!4;"
"725;41859!4;725;1099!4;739;21347!5;2039;-3304;L!5;2039;-2960;L!5;1879;"
"-10744;L!5;1879;-10400;L!5;1879;-3992;L!5;1879;-3648;L!6;1879;6480;L!6;"
"1879;6136;L!6;1879;2760;L!6;2039;3792;L!7;1865;-10736;L!8;2039;-3304;L!8;"
"2039;-2960;L!8;1879;-10744;L!8;1879;-10400;L!8;1879;-3992;L!8;1879;-3648;"
"L!9;1879;6480;L!9;1879;6136;L!9;1879;2760;L!9;2039;3792;L!10;1865;-10736;"
"L!}";
