I was looking for a quick implementation of RC4 and I couldn't find one, so I wrote one based on the wikipedia example.
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It's quite easy to use:
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1) First, issue rst
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2) Load the password byte-by-byte into the password_input port. The lenght of the password is KEY_SIZE
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3) Issue 768 clocks to perform key expansion
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4) Now you should start receiving the pseudo-random stream via the output bus, one byte per clock. To encrypt or decrypt using RC4 you simply xor your data with the output stream.
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Also you shouldn't use the first kb of stream because of a known RC4 vulnerability, so please discard those bytes.
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The testbench and makefile work using icarus verilog and you can peer into rc4_tb.v to see an example implementation.
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Any question or suggestion send an email to aortega@alu.itba.edu.ar