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[/] [reed_solomon_decoder/] [trunk/] [rtl/] [out_stage.v] - Blame information for rev 2

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/* This program is free software: you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation, either version 3 of the License, or
   (at your option) any later version.
 
   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.
 
   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.
 
   Email : semiconductors@varkongroup.com
   Tel   : 1-732-447-8611
 
*/
 
 
 
module out_stage
/////  generate output bytes from pipeling memories
(
 
input clk, // input clock planned to be 56 Mhz
input reset, // active high asynchronous reset
 
// active high flag for one clock to indicate that the block should work
input DONE,
 
output reg RE,  /// RE for input memories 
 
output reg [7:0] RdAdd,
 
input [7:0] In_byte,
//////////////////////////////////////
output reg [7:0] Out_byte,
output reg CEO,
output reg Valid_out,
//////////////////////////////////////
output reg out_done
 
);
 
reg CE;
reg [2:0] cnt8;
 
 
reg state;  //// 0 or 1
 
reg F;  /// flag to control translation from state 0 to state1
 
////// CE generation///////////
always@(posedge clk or posedge reset)
begin
        if(reset)
                begin
                        CE<=0;
                        cnt8<=0;
                        CEO<=0;
                end
        else
                begin
                        cnt8<=cnt8+1;
                        CEO <= CE;
 
                        if(&cnt8)
                                CE<=1;
                        else
                                CE<=0;
                end
end
//////////////////////////////////////////////////////////
always@(posedge clk or posedge reset)
begin
        if(reset)
                begin
                        RE<=0;
                        RdAdd<=0;
                        out_done<=0;
                        state<=0;
                        Valid_out<=0;
                        Out_byte<=0;
                        F<=0;
                end
        else
                begin
                        case(state)
                        ////////////////////////////////////////////////
                        1:begin  // operation is running
                                if (CE)
                                                begin
                                                        if(RdAdd == 187)
                                                                begin
                                                                        state<=0;
                                                                        out_done<=1;
                                                                end
                                                        else
                                                                RdAdd<=RdAdd+1;
 
                                                                Out_byte<=In_byte;
                                                                Valid_out<=1;
                                                end
                        end
                        ///////////////////////////////////////////////
                        default:begin    /// idle state
                                if(CE)
                                        Valid_out<=0;
 
 
                                out_done<=0;
 
                                if(DONE)
                                        begin
                                                F<=1;
                                                RE<=~RE;
                                                RdAdd<=0;
                                        end
 
                                if(F && CE)
                                        begin
                                                state<=1;
                                                F<=0;
                                        end
                        end
                        /////////////////////////////////////////////////////////////////////
                        endcase
                end
end
 
endmodule

Line No.	Rev	Author	Line
1	2	aelmahmoud	`/* This program is free software: you can redistribute it and/or modify`
2			`it under the terms of the GNU General Public License as published by`
3			`the Free Software Foundation, either version 3 of the License, or`
4			`(at your option) any later version.`
5
6			`This program is distributed in the hope that it will be useful,`
7			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
8			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
9			`GNU General Public License for more details.`
10
11			`You should have received a copy of the GNU General Public License`
12			`along with this program. If not, see <http://www.gnu.org/licenses/>.`
13
14			`Email : semiconductors@varkongroup.com`
15			`Tel : 1-732-447-8611`
16
17			`*/`
18
19
20
21			`module out_stage`
22			`///// generate output bytes from pipeling memories`
23			`(`
24
25			`input clk, // input clock planned to be 56 Mhz`
26			`input reset, // active high asynchronous reset`
27
28			`// active high flag for one clock to indicate that the block should work`
29			`input DONE,`
30
31			`output reg RE, /// RE for input memories`
32
33			`output reg [7:0] RdAdd,`
34
35			`input [7:0] In_byte,`
36			`//////////////////////////////////////`
37			`output reg [7:0] Out_byte,`
38			`output reg CEO,`
39			`output reg Valid_out,`
40			`//////////////////////////////////////`
41			`output reg out_done`
42
43			`);`
44
45			`reg CE;`
46			`reg [2:0] cnt8;`
47
48
49			`reg state; //// 0 or 1`
50
51			`reg F; /// flag to control translation from state 0 to state1`
52
53			`////// CE generation///////////`
54			`always@(posedge clk or posedge reset)`
55			`begin`
56			`if(reset)`
57			`begin`
58			`CE<=0;`
59			`cnt8<=0;`
60			`CEO<=0;`
61			`end`
62			`else`
63			`begin`
64			`cnt8<=cnt8+1;`
65			`CEO <= CE;`
66
67			`if(&cnt8)`
68			`CE<=1;`
69			`else`
70			`CE<=0;`
71			`end`
72			`end`
73			`//////////////////////////////////////////////////////////`
74			`always@(posedge clk or posedge reset)`
75			`begin`
76			`if(reset)`
77			`begin`
78			`RE<=0;`
79			`RdAdd<=0;`
80			`out_done<=0;`
81			`state<=0;`
82			`Valid_out<=0;`
83			`Out_byte<=0;`
84			`F<=0;`
85			`end`
86			`else`
87			`begin`
88			`case(state)`
89			`////////////////////////////////////////////////`
90			`1:begin // operation is running`
91			`if (CE)`
92			`begin`
93			`if(RdAdd == 187)`
94			`begin`
95			`state<=0;`
96			`out_done<=1;`
97			`end`
98			`else`
99			`RdAdd<=RdAdd+1;`
100
101			`Out_byte<=In_byte;`
102			`Valid_out<=1;`
103			`end`
104			`end`
105			`///////////////////////////////////////////////`
106			`default:begin /// idle state`
107			`if(CE)`
108			`Valid_out<=0;`
109
110
111			`out_done<=0;`
112
113			`if(DONE)`
114			`begin`
115			`F<=1;`
116			`RE<=~RE;`
117			`RdAdd<=0;`
118			`end`
119
120			`if(F && CE)`
121			`begin`
122			`state<=1;`
123			`F<=0;`
124			`end`
125			`end`
126			`/////////////////////////////////////////////////////////////////////`
127			`endcase`
128			`end`
129			`end`
130
131			`endmodule`

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[/] [reed_solomon_decoder/] [trunk/] [rtl/] [out_stage.v] - Blame information for rev 2