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[/] [reed_solomon_decoder/] [trunk/] [rtl/] [transport_in2out.v] - Blame information for rev 2

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/* This program is free software: you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation, either version 3 of the License, or
   (at your option) any later version.
 
   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.
 
   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.
 
   Email : semiconductors@varkongroup.com
   Tel   : 1-732-447-8611
 
*/
 
 
 
module transport_in2out
///  transport input block from input pipeling memories to output pipeling memories
(
 
input clk, // input clock planned to be 56 Mhz
input reset, // active high asynchronous reset
 
// active high flag for one clock to indicate that the block should work
input S_Ready,
 
output reg RE,WE,  /// RE for input memories , WE for output memories 
 
output reg [7:0] RdAdd,WrAdd,
 
output reg Wr_done
 
);
 
 
reg cnt;
 
reg state;  //// 0 or 1
 
 
 
always@(posedge clk or posedge reset)
begin
        if(reset)
                begin
                        WE<=0;
                        RE<=0;
                        RdAdd<=0;
                        WrAdd<=0;
                        Wr_done<=0;
                        state<=0;
                        cnt<=0;
                end
        else
                begin
                        case(state)
                        ////////////////////////////////////
                        1:begin    //// operation is runing
                                cnt<=~cnt;
 
                                if(cnt)
                                        begin
                                                WrAdd<=WrAdd+1;
                                                if(WrAdd == 186)
                                                        begin
                                                                state<=0;
                                                                Wr_done<=1;
                                                        end
                                        end
                                else
                                        begin
                                                RdAdd<=RdAdd-1;
                                        end
                        end
                        ///////////////////////////////////////
                        default:begin    //// idle state
                                Wr_done<=0;
                                if(S_Ready)
                                        begin
                                                state<=1;
                                                RE<=~RE;
                                                WE<=~WE;
                                                RdAdd<= 204;
                                                WrAdd<= 255;
                                                cnt<=0;
                                        end
                        end
                        ///////////////////////////////////
                        endcase
                end
end
 
endmodule

Line No.	Rev	Author	Line
1	2	aelmahmoud
2			`/* This program is free software: you can redistribute it and/or modify`
3			`it under the terms of the GNU General Public License as published by`
4			`the Free Software Foundation, either version 3 of the License, or`
5			`(at your option) any later version.`
6
7			`This program is distributed in the hope that it will be useful,`
8			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
9			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
10			`GNU General Public License for more details.`
11
12			`You should have received a copy of the GNU General Public License`
13			`along with this program. If not, see <http://www.gnu.org/licenses/>.`
14
15			`Email : semiconductors@varkongroup.com`
16			`Tel : 1-732-447-8611`
17
18			`*/`
19
20
21
22			`module transport_in2out`
23			`/// transport input block from input pipeling memories to output pipeling memories`
24			`(`
25
26			`input clk, // input clock planned to be 56 Mhz`
27			`input reset, // active high asynchronous reset`
28
29			`// active high flag for one clock to indicate that the block should work`
30			`input S_Ready,`
31
32			`output reg RE,WE, /// RE for input memories , WE for output memories`
33
34			`output reg [7:0] RdAdd,WrAdd,`
35
36			`output reg Wr_done`
37
38			`);`
39
40
41			`reg cnt;`
42
43			`reg state; //// 0 or 1`
44
45
46
47			`always@(posedge clk or posedge reset)`
48			`begin`
49			`if(reset)`
50			`begin`
51			`WE<=0;`
52			`RE<=0;`
53			`RdAdd<=0;`
54			`WrAdd<=0;`
55			`Wr_done<=0;`
56			`state<=0;`
57			`cnt<=0;`
58			`end`
59			`else`
60			`begin`
61			`case(state)`
62			`////////////////////////////////////`
63			`1:begin //// operation is runing`
64			`cnt<=~cnt;`
65
66			`if(cnt)`
67			`begin`
68			`WrAdd<=WrAdd+1;`
69			`if(WrAdd == 186)`
70			`begin`
71			`state<=0;`
72			`Wr_done<=1;`
73			`end`
74			`end`
75			`else`
76			`begin`
77			`RdAdd<=RdAdd-1;`
78			`end`
79			`end`
80			`///////////////////////////////////////`
81			`default:begin //// idle state`
82			`Wr_done<=0;`
83			`if(S_Ready)`
84			`begin`
85			`state<=1;`
86			`RE<=~RE;`
87			`WE<=~WE;`
88			`RdAdd<= 204;`
89			`WrAdd<= 255;`
90			`cnt<=0;`
91			`end`
92			`end`
93			`///////////////////////////////////`
94			`endcase`
95			`end`
96			`end`
97
98			`endmodule`

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[/] [reed_solomon_decoder/] [trunk/] [rtl/] [transport_in2out.v] - Blame information for rev 2