Subversion Repositories rio

-------------------------------------------------------------------------------

-- 

-- RapidIO IP Library Core

-- 

-- This file is part of the RapidIO IP library project

-- http://www.opencores.org/cores/rio/

-- 

-- Description

-- Contains automatic simulation test code to verify a RioSwitch implementation.

-- 

-- To Do:

-- - Use the Wishbone port as a test port on the implementation defined config-space.

-- - Test all sizes of packets that go through the maintenance port.

-- 

-- Author(s): 

-- - Magnus Rosenius, magro732@opencores.org 

-- 

-------------------------------------------------------------------------------

-- 

-- Copyright (C) 2013 Authors and OPENCORES.ORG 

-- 

-- This source file may be used and distributed without 

-- restriction provided that this copyright statement is not 

-- removed from the file and that any derivative work contains 

-- the original copyright notice and the associated disclaimer. 

-- 

-- This source file is free software; you can redistribute it 

-- and/or modify it under the terms of the GNU Lesser General 

-- Public License as published by the Free Software Foundation; 

-- either version 2.1 of the License, or (at your option) any 

-- later version. 

-- 

-- This source is distributed in the hope that it will be 

-- useful, but WITHOUT ANY WARRANTY; without even the implied 

-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 

-- PURPOSE. See the GNU Lesser General Public License for more 

-- details. 

-- 

-- You should have received a copy of the GNU Lesser General 

-- Public License along with this source; if not, download it 

-- from http://www.opencores.org/lgpl.shtml 

-- 

-------------------------------------------------------------------------------

-------------------------------------------------------------------------------

-- TestRioSwitch.

-------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use ieee.math_real.all;

library std;

use std.textio.all;

use work.rio_common.all;

use work.TestPortPackage.all;

-------------------------------------------------------------------------------

-- Entity for TestRioSwitch.

-------------------------------------------------------------------------------

entity TestRioSwitch is

end entity;

-------------------------------------------------------------------------------

-- Architecture for TestRioSwitch.

-------------------------------------------------------------------------------

architecture TestRioSwitchImpl of TestRioSwitch is

  component RioSwitch is

    generic(

      SWITCH_PORTS : natural range 3 to 255 := 4;

      DEVICE_IDENTITY : std_logic_vector(15 downto 0);

      DEVICE_VENDOR_IDENTITY : std_logic_vector(15 downto 0);

      DEVICE_REV : std_logic_vector(31 downto 0);

      ASSY_IDENTITY : std_logic_vector(15 downto 0);

      ASSY_VENDOR_IDENTITY : std_logic_vector(15 downto 0);

      ASSY_REV : std_logic_vector(15 downto 0));

    port(

      clk : in std_logic;

      areset_n : in std_logic;

      writeFrameFull_i : in Array1(SWITCH_PORTS-1 downto 0);

      writeFrame_o : out Array1(SWITCH_PORTS-1 downto 0);

      writeFrameAbort_o : out Array1(SWITCH_PORTS-1 downto 0);

      writeContent_o : out Array1(SWITCH_PORTS-1 downto 0);

      writeContentData_o : out Array32(SWITCH_PORTS-1 downto 0);

      readFrameEmpty_i : in Array1(SWITCH_PORTS-1 downto 0);

      readFrame_o : out Array1(SWITCH_PORTS-1 downto 0);

      readFrameRestart_o : out Array1(SWITCH_PORTS-1 downto 0);

      readFrameAborted_i : in Array1(SWITCH_PORTS-1 downto 0);

      readContentEmpty_i : in Array1(SWITCH_PORTS-1 downto 0);

      readContent_o : out Array1(SWITCH_PORTS-1 downto 0);

      readContentEnd_i : in Array1(SWITCH_PORTS-1 downto 0);

      readContentData_i : in Array32(SWITCH_PORTS-1 downto 0);

      portLinkTimeout_o : out std_logic_vector(23 downto 0);

      linkInitialized_i : in Array1(SWITCH_PORTS-1 downto 0);

      outputPortEnable_o : out Array1(SWITCH_PORTS-1 downto 0);

      inputPortEnable_o : out Array1(SWITCH_PORTS-1 downto 0);

      localAckIdWrite_o : out Array1(SWITCH_PORTS-1 downto 0);

      clrOutstandingAckId_o : out Array1(SWITCH_PORTS-1 downto 0);

      inboundAckId_o : out Array5(SWITCH_PORTS-1 downto 0);

      outstandingAckId_o : out Array5(SWITCH_PORTS-1 downto 0);

      outboundAckId_o : out Array5(SWITCH_PORTS-1 downto 0);

      inboundAckId_i : in Array5(SWITCH_PORTS-1 downto 0);

      outstandingAckId_i : in Array5(SWITCH_PORTS-1 downto 0);

      outboundAckId_i : in Array5(SWITCH_PORTS-1 downto 0);

      configStb_o : out std_logic;

      configWe_o : out std_logic;

      configAddr_o : out std_logic_vector(23 downto 0);

      configData_o : out std_logic_vector(31 downto 0);

      configData_i : in std_logic_vector(31 downto 0);

      configAck_i : in std_logic);

  end component;

  constant PORTS : natural := 3;

  constant SWITCH_IDENTITY : std_logic_vector(15 downto 0) := x"0123";

  constant SWITCH_VENDOR_IDENTITY : std_logic_vector(15 downto 0) := x"4567";

  constant SWITCH_REV : std_logic_vector(31 downto 0) := x"89abcdef";

  constant SWITCH_ASSY_IDENTITY : std_logic_vector(15 downto 0) := x"0011";

  constant SWITCH_ASSY_VENDOR_IDENTITY : std_logic_vector(15 downto 0) := x"2233";

  constant SWITCH_ASSY_REV : std_logic_vector(15 downto 0) := x"4455";

  signal clk : std_logic;

  signal areset_n : std_logic;

  signal inboundEmpty : Array1(PORTS-1 downto 0);

  signal inboundEmpty0 : std_logic;

  signal inboundEmpty1 : std_logic;

  signal inboundEmpty2 : std_logic;

  signal inboundWrite : Array1(PORTS-1 downto 0);

  signal inboundWrite0 : std_logic;

  signal inboundWrite1 : std_logic;

  signal inboundWrite2 : std_logic;

  signal inboundMessage : TestPortMessagePacketBufferArray(PORTS-1 downto 0);

  signal inboundMessage0 : TestPortMessagePacketBuffer;

  signal inboundMessage1 : TestPortMessagePacketBuffer;

  signal inboundMessage2 : TestPortMessagePacketBuffer;

  signal inboundAck : Array1(PORTS-1 downto 0);

  signal inboundAck0 : std_logic;

  signal inboundAck1 : std_logic;

  signal inboundAck2 : std_logic;

  signal outboundEmpty : Array1(PORTS-1 downto 0);

  signal outboundEmpty0 : std_logic;

  signal outboundEmpty1 : std_logic;

  signal outboundEmpty2 : std_logic;

  signal outboundWrite : Array1(PORTS-1 downto 0);

  signal outboundWrite0 : std_logic;

  signal outboundWrite1 : std_logic;

  signal outboundWrite2 : std_logic;

  signal outboundMessage : TestPortMessagePacketBufferArray(PORTS-1 downto 0);

  signal outboundMessage0 : TestPortMessagePacketBuffer;

  signal outboundMessage1 : TestPortMessagePacketBuffer;

  signal outboundMessage2 : TestPortMessagePacketBuffer;

  signal outboundAck : Array1(PORTS-1 downto 0);

  signal outboundAck0 : std_logic;

  signal outboundAck1 : std_logic;

  signal outboundAck2 : std_logic;

  signal writeFrameFull : Array1(PORTS-1 downto 0);

  signal writeFrame : Array1(PORTS-1 downto 0);

  signal writeFrameAbort : Array1(PORTS-1 downto 0);

  signal writeContent : Array1(PORTS-1 downto 0);

  signal writeContentData : Array32(PORTS-1 downto 0);

  signal readFrameEmpty : Array1(PORTS-1 downto 0);

  signal readFrame : Array1(PORTS-1 downto 0);

  signal readFrameRestart : Array1(PORTS-1 downto 0);

  signal readFrameAborted : Array1(PORTS-1 downto 0);

  signal readContentEmpty : Array1(PORTS-1 downto 0);

  signal readContent : Array1(PORTS-1 downto 0);

  signal readContentEnd : Array1(PORTS-1 downto 0);

  signal readContentData : Array32(PORTS-1 downto 0);

  signal portLinkTimeout : std_logic_vector(23 downto 0);

  signal linkInitialized : Array1(PORTS-1 downto 0);

  signal outputPortEnable : Array1(PORTS-1 downto 0);

  signal inputPortEnable : Array1(PORTS-1 downto 0);

  signal localAckIdWrite : Array1(PORTS-1 downto 0);

  signal clrOutstandingAckId : Array1(PORTS-1 downto 0);

  signal inboundAckIdWrite : Array5(PORTS-1 downto 0);

  signal outstandingAckIdWrite : Array5(PORTS-1 downto 0);

  signal outboundAckIdWrite : Array5(PORTS-1 downto 0);

  signal inboundAckIdRead : Array5(PORTS-1 downto 0);

  signal outstandingAckIdRead : Array5(PORTS-1 downto 0);

  signal outboundAckIdRead : Array5(PORTS-1 downto 0);

  signal messageEmpty : std_logic;

  signal messageWrite : std_logic;

  signal message : TestPortMessageWishbone;

  signal messageAck : std_logic;

  signal configStb : std_logic;

  signal configWe : std_logic;

  signal configAddr : std_logic_vector(23 downto 0);

  signal configDataWrite : std_logic_vector(31 downto 0);

  signal configDataRead : std_logic_vector(31 downto 0);

  signal configAck : std_logic;

begin

  -----------------------------------------------------------------------------

  -- Clock generation.

  -----------------------------------------------------------------------------

  ClockGenerator: process

  begin

    clk <= '0';

    wait for 20 ns;

    clk <= '1';

    wait for 20 ns;

  end process;

  -----------------------------------------------------------------------------

  -- Serial port emulator.

  -----------------------------------------------------------------------------

  TestDriver: process

    ---------------------------------------------------------------------------

    -- 

    ---------------------------------------------------------------------------

    procedure SendFrame(constant portIndex : natural range 0 to 7;

                        constant frame : RioFrame) is

    begin

      -- Crappy Modelsim cannot handle arrays of signals...

      case portIndex is

        when 0 =>

          TestPortPacketBufferWrite(inboundWrite0, inboundMessage0, inboundAck0,

                                    frame, false);

        when 1 =>

          TestPortPacketBufferWrite(inboundWrite1, inboundMessage1, inboundAck1,

                                    frame, false);

        when others =>

          TestPortPacketBufferWrite(inboundWrite2, inboundMessage2, inboundAck2,

                                    frame, false);

      end case;

    end procedure;

    ---------------------------------------------------------------------------

    -- 

    ---------------------------------------------------------------------------

    procedure ReceiveFrame(constant portIndex : natural range 0 to 7;

                           constant frame : RioFrame) is

    begin

      -- Crappy Modelsim cannot handle arrays of signals...

      case portIndex is

        when 0 =>

          TestPortPacketBufferWrite(outboundWrite0, outboundMessage0, outboundAck0,

                                    frame, false);

        when 1 =>

          TestPortPacketBufferWrite(outboundWrite1, outboundMessage1, outboundAck1,

                                    frame, false);

        when others =>

          TestPortPacketBufferWrite(outboundWrite2, outboundMessage2, outboundAck2,

                                    frame, false);

      end case;

    end procedure;

    ---------------------------------------------------------------------------

    -- 

    ---------------------------------------------------------------------------

    procedure SendFrame(constant portIndex : natural range 0 to 7;

                        constant sourceId : std_logic_vector(15 downto 0);

                        constant destinationId : std_logic_vector(15 downto 0);

                        constant payload : RioPayload) is

      variable frame : RioFrame;

    begin

      frame := RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",

                              tt=>"01", ftype=>"0000",

                              sourceId=>sourceId, destId=>destinationId,

                              payload=>payload);

      SendFrame(portIndex, frame);

    end procedure;

    ---------------------------------------------------------------------------

    -- 

    ---------------------------------------------------------------------------

    procedure ReceiveFrame(constant portIndex : natural range 0 to 7;

                           constant sourceId : std_logic_vector(15 downto 0);

                           constant destinationId : std_logic_vector(15 downto 0);

                           constant payload : RioPayload) is

      variable frame : RioFrame;

    begin

      frame := RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",

                              tt=>"01", ftype=>"0000",

                              sourceId=>sourceId, destId=>destinationId,

                              payload=>payload);

      ReceiveFrame(portIndex, frame);

    end procedure;

    ---------------------------------------------------------------------------

    -- 

    ---------------------------------------------------------------------------

    procedure ReadConfig32(constant portIndex : natural range 0 to 7;

                           constant destinationId : std_logic_vector(15 downto 0);

                           constant sourceId : std_logic_vector(15 downto 0);

                           constant hop : std_logic_vector(7 downto 0);

                           constant tid : std_logic_vector(7 downto 0);

                           constant address : std_logic_vector(23 downto 0);

                           constant data : std_logic_vector(31 downto 0)) is

      variable maintData : DoubleWordArray(0 to 7);

    begin

      SendFrame(portIndex, RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",

                                          tt=>"01", ftype=>FTYPE_MAINTENANCE_CLASS,

                                          sourceId=>sourceId, destId=>destinationId,

                                          payload=>RioMaintenance(transaction=>"0000",

                                                                  size=>"1000",

                                                                  tid=>tid,

                                                                  hopCount=>hop,

                                                                  configOffset=>address(23 downto 3),

                                                                  wdptr=>address(2),

                                                                  dataLength=>0,

                                                                  data=>maintData)));

      if (address(2) = '0') then

        maintData(0) := data & x"00000000";

      else

        maintData(0) := x"00000000" & data ;

      end if;

      ReceiveFrame(portIndex, RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",

                                             tt=>"01", ftype=>FTYPE_MAINTENANCE_CLASS,

                                             sourceId=>destinationId, destId=>sourceId,

                                             payload=>RioMaintenance(transaction=>"0010",

                                                                     size=>"0000",

                                                                     tid=>tid,

                                                                     hopCount=>x"ff",

                                                                     configOffset=>"000000000000000000000",

                                                                     wdptr=>'0',

                                                                     dataLength=>1,

                                                                     data=>maintData)));

    end procedure;

    ---------------------------------------------------------------------------

    -- 

    ---------------------------------------------------------------------------

    procedure WriteConfig32(constant portIndex : natural range 0 to 7;

                            constant destinationId : std_logic_vector(15 downto 0);

                            constant sourceId : std_logic_vector(15 downto 0);

                            constant hop : std_logic_vector(7 downto 0);

                            constant tid : std_logic_vector(7 downto 0);

                            constant address : std_logic_vector(23 downto 0);

                            constant data : std_logic_vector(31 downto 0)) is

      variable maintData : DoubleWordArray(0 to 7);

    begin

      if (address(2) = '0') then

        maintData(0) := data & x"00000000";

      else

        maintData(0) := x"00000000" & data ;

      end if;

      SendFrame(portIndex, RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",

                                          tt=>"01", ftype=>FTYPE_MAINTENANCE_CLASS,

                                          sourceId=>sourceId, destId=>destinationId,

                                          payload=>RioMaintenance(transaction=>"0001",

                                                                  size=>"1000",

                                                                  tid=>tid,

                                                                  hopCount=>hop,

                                                                  configOffset=>address(23 downto 3),

                                                                  wdptr=>address(2),

                                                                  dataLength=>1,

                                                                  data=>maintData)));

      ReceiveFrame(portIndex, RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",

                                             tt=>"01", ftype=>FTYPE_MAINTENANCE_CLASS,

                                             sourceId=>destinationId, destId=>sourceId,

                                             payload=>RioMaintenance(transaction=>"0011",

                                                                     size=>"0000",

                                                                     tid=>tid,

                                                                     hopCount=>x"ff",

                                                                     configOffset=>"000000000000000000000",

                                                                     wdptr=>'0',

                                                                     dataLength=>0,

                                                                     data=>maintData)));

    end procedure;

    ---------------------------------------------------------------------------

    -- 

    ---------------------------------------------------------------------------

    procedure RouteFrame(constant sourcePortIndex : natural range 0 to 7;

                         constant destinationPortIndex : natural range 0 to 7;

                         constant sourceId : std_logic_vector(15 downto 0);

                         constant destinationId : std_logic_vector(15 downto 0);

                         constant payload : RioPayload) is

      variable frame : RioFrame;

    begin

      frame := RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",

                              tt=>"01", ftype=>"0000",

                              destId=>destinationId, sourceId=>sourceId,

                              payload=>payload);

      ReceiveFrame(destinationPortIndex, frame);

      SendFrame(sourcePortIndex, frame);

    end procedure;

    ---------------------------------------------------------------------------

    -- 

    ---------------------------------------------------------------------------

    procedure ExchangeFrames is

    begin

      TestWait(inboundEmpty0, '1', "port0 frame sent");

      TestWait(inboundEmpty1, '1', "port0 frame sent");

      TestWait(inboundEmpty2, '1', "port0 frame sent");

      TestWait(outboundEmpty0, '1', "port0 frame received");

      TestWait(outboundEmpty1, '1', "port0 frame received");

      TestWait(outboundEmpty2, '1', "port0 frame received");

    end procedure;

    ---------------------------------------------------------------------------

    -- 

    ---------------------------------------------------------------------------

    procedure ConfigRead(constant address : std_logic_vector(23 downto 0);

                         constant data : std_logic_vector(31 downto 0)) is

    begin

      TestPortWishboneWrite(writeSignal=>messageWrite,

                            messageSignal=>message,

                            ackSignal=>messageAck,

                            writeAccess=>false,

                            address=>(x"00000000" & x"00" & address),

                            byteSelect=>x"00",

                            data=>(x"00000000" & data),

                            latency=>3);

    end procedure;

    procedure ConfigWrite(constant address : std_logic_vector(23 downto 0);

                          constant data : std_logic_vector(31 downto 0)) is

    begin

      TestPortWishboneWrite(writeSignal=>messageWrite,

                            messageSignal=>message,

                            ackSignal=>messageAck,

                            writeAccess=>true,

                            address=>(x"00000000" & x"00" & address),

                            byteSelect=>x"00",

                            data=>(x"00000000" & data),

                            latency=>3);

    end procedure;

    -- These variabels are needed for the random number generation.

    variable seed1 : positive := 1;

    variable seed2: positive := 1;

    variable maintData : DoubleWordArray(0 to 7);

    variable data : DoubleWordArray(0 to 31);

    variable randomPayload : RioPayload;

    variable randomPayload1 : RioPayload;

    variable randomPayload2 : RioPayload;

    variable frame : RioFrame;

  begin

    areset_n <= '0';

    linkInitialized <= (others=>'0');

    writeFrameFull <= (others=>'0');

    for portIndex in 0 to PORTS-1 loop

      inboundWrite0 <= '0';

      outboundWrite0 <= '0';

      inboundWrite1 <= '0';

      outboundWrite1 <= '0';

      inboundWrite2 <= '0';

      outboundWrite2 <= '0';

      localAckIdWrite(portIndex) <= '0';

      clrOutstandingAckId(portIndex) <= '0';

      inboundAckIdWrite(portIndex) <= (others=>'0');

      outstandingAckIdWrite(portIndex) <= (others=>'0');

      outboundAckIdWrite(portIndex) <= (others=>'0');

    end loop;

    wait until clk'event and clk = '1';

    wait until clk'event and clk = '1';

    areset_n <= '1';

    wait until clk'event and clk = '1';

    wait until clk'event and clk = '1';

    ---------------------------------------------------------------------------

    PrintS("-----------------------------------------------------------------");

    PrintS("TG_RioSwitch");

    PrintS("-----------------------------------------------------------------");

    PrintS("TG_RioSwitch-TC1");

    PrintS("Description: Test switch maintenance accesses on different ports.");

    PrintS("Requirement: XXXXX");

    PrintS("-----------------------------------------------------------------");

    PrintS("Step 1:");

    PrintS("Action: Send maintenance read request packets to read switch identity.");

    PrintS("Result: The switch should answer with its configured identitiy.");

    ---------------------------------------------------------------------------

    PrintR("TG_RioSwitch-TC1-Step1");

    ---------------------------------------------------------------------------

    ReadConfig32(portIndex=>0, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",

                 tid=>x"00", address=>x"000000", data=>(SWITCH_IDENTITY & SWITCH_VENDOR_IDENTITY));

    ReadConfig32(portIndex=>1, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",

                 tid=>x"01", address=>x"000004", data=>SWITCH_REV);

    ReadConfig32(portIndex=>2, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",

                 tid=>x"02", address=>x"000008", data=>(SWITCH_ASSY_IDENTITY & SWITCH_ASSY_VENDOR_IDENTITY));

    ReadConfig32(portIndex=>3, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",

                 tid=>x"03", address=>x"00000c", data=>(SWITCH_ASSY_REV & x"0100"));

    ExchangeFrames;

    ---------------------------------------------------------------------------

    PrintS("-----------------------------------------------------------------");

    PrintS("Step 2:");

    PrintS("Action: Check the switch Processing Element Features.");

    PrintS("Result: The expected switch features should be returned. ");

    PrintS("        Switch with extended features pointer valid. Common ");

    PrintS("        transport large system support and standard route table ");

    PrintS("        configuration support.");

    ---------------------------------------------------------------------------

    PrintR("TG_RioSwitch-TC1-Step2");

    ---------------------------------------------------------------------------

    ReadConfig32(portIndex=>4, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",

                 tid=>x"04", address=>x"000010", data=>x"10000118");

    ExchangeFrames;

    ---------------------------------------------------------------------------

    PrintS("-----------------------------------------------------------------");

    PrintS("Step 3:");

    PrintS("Action: Check the switch port information.");

    PrintS("Result: The expected port and number of ports should be returned.");

    ---------------------------------------------------------------------------

    PrintR("TG_RioSwitch-TC1-Step3");

    ---------------------------------------------------------------------------

    ReadConfig32(portIndex=>2, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",

                 tid=>x"05", address=>x"000014", data=>x"00000302");

    ExchangeFrames;

    ---------------------------------------------------------------------------

    PrintS("-----------------------------------------------------------------");

    PrintS("Step 4:");

    PrintS("Action: Check the switch number of supported routes.");

    PrintS("Result: The expected number of supported routes should be returned.");

    ---------------------------------------------------------------------------

    PrintR("TG_RioSwitch-TC1-Step4");

    ---------------------------------------------------------------------------

    ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",

                 tid=>x"06", address=>x"000034", data=>x"00000800");

    ExchangeFrames;

    ---------------------------------------------------------------------------

    PrintS("-----------------------------------------------------------------");

    PrintS("Step 5:");

    PrintS("Action: Test host base device id lock by reading it, then hold it ");

    PrintS("        and try to grab it from another address.");

    PrintS("Result: The value should follow the specification.");

    ---------------------------------------------------------------------------

    PrintR("TG_RioSwitch-TC1-Step5");

    ---------------------------------------------------------------------------

    -- Check that the lock is released.

    ReadConfig32(portIndex=>0, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",

                 tid=>x"00", address=>x"000068", data=>x"0000ffff");

    -- Try to accuire the lock.

    WriteConfig32(portIndex=>0, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",

                  tid=>x"00", address=>x"000068", data=>x"00000002");

    -- Check that the lock has been accuired.

    ReadConfig32(portIndex=>0, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",

                 tid=>x"00", address=>x"000068", data=>x"00000002");

    -- Try to accuire the lock from another source.

    WriteConfig32(portIndex=>0, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",

                  tid=>x"00", address=>x"000068", data=>x"00000003");

    -- Check that the lock refuses the new access.

    ReadConfig32(portIndex=>0, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",

                 tid=>x"00", address=>x"000068", data=>x"00000002");

    -- Release the lock.

    WriteConfig32(portIndex=>0, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",

                  tid=>x"00", address=>x"000068", data=>x"00000002");

    -- Check that the lock is released.

    ReadConfig32(portIndex=>0, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",

                 tid=>x"00", address=>x"000068", data=>x"0000ffff");

    -- Check that the lock can be accuired from another source once unlocked.

    WriteConfig32(portIndex=>0, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",

                  tid=>x"00", address=>x"000068", data=>x"00000003");

    -- Check that the lock is released.

    ReadConfig32(portIndex=>0, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",

                 tid=>x"00", address=>x"000068", data=>x"00000003");

    -- Release the lock again.

    WriteConfig32(portIndex=>0, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",