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-------------------------------------------------------------------------------
-- 
-- RapidIO IP Library Core
-- 
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
-- 
-- Description
-- Contains automatic test code to verify a RioWbBridge implementation.
-- 
-- To Do:
-- REMARK: Move the testport package and entities to a seperate file.
-- 
-- Author(s): 
-- - Magnus Rosenius, magro732@opencores.org 
-- 
-------------------------------------------------------------------------------
-- 
-- Copyright (C) 2013 Authors and OPENCORES.ORG 
-- 
-- This source file may be used and distributed without 
-- restriction provided that this copyright statement is not 
-- removed from the file and that any derivative work contains 
-- the original copyright notice and the associated disclaimer. 
-- 
-- This source file is free software; you can redistribute it 
-- and/or modify it under the terms of the GNU Lesser General 
-- Public License as published by the Free Software Foundation; 
-- either version 2.1 of the License, or (at your option) any 
-- later version. 
-- 
-- This source is distributed in the hope that it will be 
-- useful, but WITHOUT ANY WARRANTY; without even the implied 
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
-- PURPOSE. See the GNU Lesser General Public License for more 
-- details. 
-- 
-- You should have received a copy of the GNU Lesser General 
-- Public License along with this source; if not, download it 
-- from http://www.opencores.org/lgpl.shtml 
-- 
-------------------------------------------------------------------------------
 
 
-------------------------------------------------------------------------------
-- 
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.rio_common.all;
 
-------------------------------------------------------------------------------
-- 
-------------------------------------------------------------------------------
package TestPortPackage is
  constant ADDRESS_WIDTH : natural := 31;
  constant DATA_SIZE_MAX : natural := 32;
 
  type TestPortMessageWishbone is record
    writeAccess : boolean;
    address : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
    byteSelect : std_logic_vector(7 downto 0);
    length : natural range 1 to DATA_SIZE_MAX;
    data : DoublewordArray(0 to DATA_SIZE_MAX-1);
    latency : natural;
  end record;
 
  type TestPortMessageSymbol is record
    symbolType : std_logic_vector(1 downto 0);
    symbolContent : std_logic_vector(31 downto 0);
    ignoreIdle : boolean;
  end record;
 
  type TestPortMessagePacketBuffer is record
    frame : RioFrame;
    willAbort : boolean;
  end record;
 
  -----------------------------------------------------------------------------
  -- 
  -----------------------------------------------------------------------------
 
  component TestPortWishbone is
    port(
      clk : in std_logic;
      areset_n : in std_logic;
 
      messageEmpty_o : out std_logic;
      messageWrite_i : in std_logic;
      message_i : in TestPortMessageWishbone;
      messageAck_o : out std_logic;
 
      cyc_i : in std_logic;
      stb_i : in std_logic;
      we_i : in std_logic;
      adr_i : in std_logic_vector(30 downto 0);
      sel_i : in std_logic_vector(7 downto 0);
      dat_i : in std_logic_vector(63 downto 0);
      dat_o : out std_logic_vector(63 downto 0);
      err_o : out std_logic;
      ack_o : out std_logic);
  end component;
 
  component TestPortPacketBuffer is
    port(
      clk : in std_logic;
      areset_n : in std_logic;
 
      readEmpty_o : out std_logic;
      readWrite_i : in std_logic;
      readMessage_i : in TestPortMessagePacketBuffer;
      readAck_o : out std_logic;
 
      writeEmpty_o : out std_logic;
      writeWrite_i : in std_logic;
      writeMessage_i : in TestPortMessagePacketBuffer;
      writeAck_o : out std_logic;
 
      readFrameEmpty_o : out std_logic;
      readFrame_i : in std_logic;
      readFrameRestart_i : in std_logic;
      readFrameAborted_o : out std_logic;
      readWindowEmpty_o : out std_logic;
      readWindowReset_i : in std_logic;
      readWindowNext_i : in std_logic;
      readContentEmpty_o : out std_logic;
      readContent_i : in std_logic;
      readContentEnd_o : out std_logic;
      readContentData_o : out std_logic_vector(31 downto 0);
 
      writeFrame_i : in std_logic;
      writeFrameAbort_i : in std_logic;
      writeContent_i : in std_logic;
      writeContentData_i : in std_logic_vector(31 downto 0));
  end component;
 
  -----------------------------------------------------------------------------
  -- 
  -----------------------------------------------------------------------------
  procedure TestPortWishboneWrite(
    signal writeSignal : out std_logic;
    signal messageSignal : out TestPortMessageWishbone;
    signal ackSignal : in std_logic;
    constant writeAccess : in boolean;
    constant address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
    constant byteSelect : in std_logic_vector(7 downto 0);
    constant length : in natural range 1 to DATA_SIZE_MAX;
    constant data : in DoublewordArray(0 to DATA_SIZE_MAX-1);
    constant latency : natural := 0);
 
  procedure TestPortPacketBufferWrite(
    signal writeSignal : out std_logic;
    signal messageSignal : out TestPortMessagePacketBuffer;
    signal ackSignal : in std_logic;
    constant frame : in RioFrame;
    constant willAbort : boolean := false);
 
end package;
 
-------------------------------------------------------------------------------
-- 
-------------------------------------------------------------------------------
package body TestPortPackage is
 
  -----------------------------------------------------------------------------
  -- 
  -----------------------------------------------------------------------------
  procedure TestPortWishboneWrite(
    signal writeSignal : out std_logic;
    signal messageSignal : out TestPortMessageWishbone;
    signal ackSignal : in std_logic;
    constant writeAccess : in boolean;
    constant address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
    constant byteSelect : in std_logic_vector(7 downto 0);
    constant length : in natural range 1 to DATA_SIZE_MAX;
    constant data : in DoublewordArray(0 to DATA_SIZE_MAX-1);
    constant latency : natural := 0) is
  begin
    writeSignal <= '1';
    messageSignal.writeAccess <= writeAccess;
    messageSignal.address <= address;
    messageSignal.byteSelect <= byteSelect;
    messageSignal.length <= length;
    messageSignal.data <= data;
    messageSignal.latency <= latency;
    wait until ackSignal = '1';
    writeSignal <= '0';
    wait until ackSignal = '0';
  end procedure;
 
  -----------------------------------------------------------------------------
  -- 
  -----------------------------------------------------------------------------
  procedure TestPortPacketBufferWrite(
    signal writeSignal : out std_logic;
    signal messageSignal : out TestPortMessagePacketBuffer;
    signal ackSignal : in std_logic;
    constant frame : in RioFrame;
    constant willAbort : boolean := false) is
  begin
    writeSignal <= '1';
    messageSignal.frame <= frame;
    messageSignal.willAbort <= willAbort;
    wait until ackSignal = '1';
    writeSignal <= '0';
    wait until ackSignal = '0';
  end procedure;
 
end package body;
 
 
 
 
-------------------------------------------------------------------------------
-- 
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
use work.rio_common.all;
use work.TestPortPackage.all;
 
 
-------------------------------------------------------------------------------
-- 
-------------------------------------------------------------------------------
entity TestPortPacketBuffer is
  port(
    clk : in std_logic;
    areset_n : in std_logic;
 
    readEmpty_o : out std_logic;
    readWrite_i : in std_logic;
    readMessage_i : in TestPortMessagePacketBuffer;
    readAck_o : out std_logic;
 
    writeEmpty_o : out std_logic;
    writeWrite_i : in std_logic;
    writeMessage_i : in TestPortMessagePacketBuffer;
    writeAck_o : out std_logic;
 
    readFrameEmpty_o : out std_logic;
    readFrame_i : in std_logic;
    readFrameRestart_i : in std_logic;
    readFrameAborted_o : out std_logic;
    readWindowEmpty_o : out std_logic;
    readWindowReset_i : in std_logic;
    readWindowNext_i : in std_logic;
    readContentEmpty_o : out std_logic;
    readContent_i : in std_logic;
    readContentEnd_o : out std_logic;
    readContentData_o : out std_logic_vector(31 downto 0);
 
    -- writeFrameFull_o is missing yes, but you can control it from the testbench directly
    -- instead.
    writeFrame_i : in std_logic;
    writeFrameAbort_i : in std_logic;
    writeContent_i : in std_logic;
    writeContentData_i : in std_logic_vector(31 downto 0));
end entity;
 
 
-------------------------------------------------------------------------------
-- 
-------------------------------------------------------------------------------
architecture TestPortPacketBufferPortImpl of TestPortPacketBuffer is
  constant QUEUE_SIZE : natural := 63;
  type QueueArray is array (natural range <>) of TestPortMessagePacketBuffer;
 
  function QueueIndexInc(constant i : natural) return natural is
    variable returnValue : natural;
  begin
    if(i = QUEUE_SIZE) then
      returnValue := 0;
    else
      returnValue := i + 1;
    end if;
    return returnValue;
  end function;
 
begin
 
  -----------------------------------------------------------------------------
  -- 
  -----------------------------------------------------------------------------
  Reader: process
    variable frameQueue : QueueArray(0 to QUEUE_SIZE);
    variable front, back, window : natural range 0 to QUEUE_SIZE;
    variable frameIndex : natural;
  begin
    wait until areset_n = '1';
 
    readFrameEmpty_o <= '1';
    readFrameAborted_o <= '0';
    readWindowEmpty_o <= '1';
    readContentEmpty_o <= '1';
    readContentEnd_o <= '0';
    readContentData_o <= (others=>'0');
 
    front := 0;
    back := 0;
    window := 0;
    frameIndex := 0;
    readEmpty_o <= '1';
    readAck_o <= '0';
 
    loop
      wait until clk = '1' or readWrite_i = '1';
 
      if (clk'event) then
        if (readFrame_i = '1') then
          if (back /= front) then
            back := QueueIndexInc(back);
          else
            TestError("READ:BACK:reading when no frame is present");
          end if;
        end if;
 
        if (readFrameRestart_i = '1') then
          frameIndex := 0;
        end if;
 
        if (readWindowReset_i = '1') then
          window := back;
          frameIndex := 0;
        end if;
 
        if (readWindowNext_i = '1') then
          if (window /= front) then
            window := QueueIndexInc(window);
            frameIndex := 0;
          else
            TestError("READ:WINDOW:reading when no frame is present");
          end if;
        end if;
 
        if (readContent_i = '1') then
          if (back /= front) then
            if (frameIndex < frameQueue(window).frame.length) then
              readContentData_o <= frameQueue(window).frame.payload(frameIndex);
              frameIndex := frameIndex + 1;
              if (frameIndex = frameQueue(window).frame.length) then
                readContentEnd_o <= '1';
              else
                readContentEnd_o <= '0';
              end if;
            else
              TestError("READ:CONTENT:reading when frame has ended");
            end if;
          else
            TestError("READ:CONTENT:reading when no frame is present");
          end if;
        end if;
 
        if (front = back) then
          readFrameEmpty_o <= '1';
        else
          readFrameEmpty_o <= '0';
        end if;
 
        if (front = window) then
          readWindowEmpty_o <= '1';
          readContentEmpty_o <= '1';
        else
          readWindowEmpty_o <= '0';
          if (frameIndex /= frameQueue(window).frame.length) then
            readContentEmpty_o <= '0';
          else
            readContentEmpty_o <= '1';
          end if;
        end if;
 
        if (front = back) then
          readEmpty_o <= '1';
        else
          readEmpty_o <= '0';
        end if;
      elsif (readWrite_i'event) then
        frameQueue(front) := readMessage_i;
        front := QueueIndexInc(front);
 
        readEmpty_o <= '0';
        readAck_o <= '1';
        wait until readWrite_i = '0';
        readAck_o <= '0';
      end if;
    end loop;
  end process;
 
  -----------------------------------------------------------------------------
  -- 
  -----------------------------------------------------------------------------
  Writer: process
    variable frameQueue : QueueArray(0 to QUEUE_SIZE);
    variable front, back : natural range 0 to QUEUE_SIZE;
    variable frameIndex : natural range 0 to 69;
  begin
    wait until areset_n = '1';
 
    writeEmpty_o <= '1';
    writeAck_o <= '0';
 
    front := 0;
    back := 0;
    frameIndex := 0;
 
    loop
      wait until clk = '1' or writeWrite_i = '1';
 
      if (clk'event) then
 
        if (writeFrame_i = '1') then
          if (frameIndex = 0) then
            TestError("WRITE:Empty frame written.");
          end if;
          if (frameIndex /= frameQueue(back).frame.length) then
            TestError("WRITE:Frame with unmatching length was written.");
          end if;
          if (back /= front) then
            back := QueueIndexInc(back);
          else
            TestError("WRITE:Unexpected frame written.");
          end if;
          frameIndex := 0;
        end if;
 
        if (writeFrameAbort_i = '1') then
          if (back /= front) then
            if (frameQueue(back).willAbort) then
              TestCompare(frameIndex,
                          frameQueue(back).frame.length,
                          "frameIndex abort");
              back := QueueIndexInc(back);
            else
              TestError("WRITE:Not expecting this frame to abort.");
            end if;
          end if;
          frameIndex := 0;
        end if;
 
        if (writeContent_i = '1') then
          if (frameIndex < frameQueue(back).frame.length) then
            TestCompare(writeContentData_i,
                        frameQueue(back).frame.payload(frameIndex),
                        "frame content");
            frameIndex := frameIndex + 1;
          else
            TestError("WRITE:Receiving more frame content than expected.");
          end if;
        end if;
 
        if (front = back) then
          writeEmpty_o <= '1';
        else
          writeEmpty_o <= '0';
        end if;
      elsif (writeWrite_i'event) then
        frameQueue(front) := writeMessage_i;
        front := QueueIndexInc(front);
 
        writeEmpty_o <= '0';
        writeAck_o <= '1';
        wait until writeWrite_i = '0';
        writeAck_o <= '0';
      end if;
    end loop;
  end process;
 
end architecture;
 
 
 
-------------------------------------------------------------------------------
-- 
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
use work.rio_common.all;
use work.TestPortPackage.all;
 
 
-------------------------------------------------------------------------------
-- 
-------------------------------------------------------------------------------
entity TestPortWishbone is
  port(
    clk : in std_logic;
    areset_n : in std_logic;
 
    messageEmpty_o : out std_logic;
    messageWrite_i : in std_logic;
    message_i : in TestPortMessageWishbone;
    messageAck_o : out std_logic;
 
    cyc_i : in std_logic;
    stb_i : in std_logic;
    we_i : in std_logic;
    adr_i : in std_logic_vector(30 downto 0);
    sel_i : in std_logic_vector(7 downto 0);
    dat_i : in std_logic_vector(63 downto 0);
    dat_o : out std_logic_vector(63 downto 0);
    err_o : out std_logic;
    ack_o : out std_logic);
end entity;
 
 
-------------------------------------------------------------------------------
-- 
-------------------------------------------------------------------------------
architecture TestPortWishboneImpl of TestPortWishbone is
  constant QUEUE_SIZE : natural := 63;
  type QueueArray is array (natural range <>) of TestPortMessageWishbone;
 
  function QueueIndexInc(constant i : natural) return natural is
    variable returnValue : natural;
  begin
    if(i = QUEUE_SIZE) then
      returnValue := 0;
    else
      returnValue := i + 1;
    end if;
    return returnValue;
  end function;
 
begin
 
  -----------------------------------------------------------------------------
  -- 
  -----------------------------------------------------------------------------
  Slave: process
    variable queue : QueueArray(0 to QUEUE_SIZE);
    variable front, back : natural range 0 to QUEUE_SIZE;
    variable cyclePosition : natural;
    variable latencyCounter : natural;
  begin
    wait until areset_n = '1';
 
    messageEmpty_o <= '1';
    messageAck_o <= '0';
 
    dat_o <= (others=>'U');
    err_o <= '0';
    ack_o <= '0';
 
    front := 0;
    back := 0;
    cyclePosition := 0;
    latencyCounter := 0;
 
    loop
      wait until clk = '1' or messageWrite_i = '1';
 
      if (clk'event) then
        if (cyc_i = '1') then
          if (front /= back) then
            if (stb_i = '1') then
              if (latencyCounter <= queue(back).latency) then
                TestCompare(stb_i, '1', "stb_i");
                if (queue(back).writeAccess) then
                  TestCompare(we_i, '1', "we_i");
                else
                  TestCompare(we_i, '0', "we_i");
                end if;
                TestCompare(adr_i, std_logic_vector(unsigned(queue(back).address)+cyclePosition), "adr_i");
                TestCompare(sel_i, queue(back).byteSelect, "sel_i");
                if (queue(back).writeAccess) then
                  TestCompare(dat_i, queue(back).data(cyclePosition), "dat_i");
                end if;
              end if;
 
              if (latencyCounter < queue(back).latency) then
                dat_o <= (others=>'U');
                ack_o <= '0';
                latencyCounter := latencyCounter + 1;
              elsif (latencyCounter = queue(back).latency) then
                if (queue(back).writeAccess) then
                  dat_o <= (others=>'U');
                else
                  dat_o <= queue(back).data(cyclePosition);
                end if;
                ack_o <= '1';
                latencyCounter := latencyCounter + 1;
              else
                dat_o <= (others=>'U');
                ack_o <= '0';
                latencyCounter := 0;
                cyclePosition := cyclePosition + 1;
 
                if (cyclePosition = queue(back).length) then
                  back := QueueIndexInc(back);
                  cyclePosition := 0;
                end if;
              end if;
            end if;
          else
            TestError("Unexpected access.");
          end if;
        else
          if (cyclePosition /= 0) or (latencyCounter /= 0) then
            TestError("Cycle unexpectedly aborted.");
            cyclePosition := 0;
            latencyCounter := 0;
          end if;
          TestCompare(stb_i, '0', "stb_i");
        end if;
 
        if (front = back) then
          messageEmpty_o <= '1';
        else
          messageEmpty_o <= '0';
        end if;
      elsif (messageWrite_i'event) then
        queue(front) := message_i;
        front := QueueIndexInc(front);
 
        messageEmpty_o <= '0';
        messageAck_o <= '1';
        wait until messageWrite_i = '0';
        messageAck_o <= '0';
      end if;
    end loop;
  end process;
 
end architecture;
 
 
-------------------------------------------------------------------------------
-- TestRioWbBridge.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
use work.rio_common.all;
use work.TestPortPackage.all;
 
 
-------------------------------------------------------------------------------
-- Entity for TestRioWbBridge.
-------------------------------------------------------------------------------
entity TestRioWbBridge is
end entity;
 
 
-------------------------------------------------------------------------------
-- Architecture for TestRioWbBridge.
-------------------------------------------------------------------------------
architecture TestRioWbBridgeImpl of TestRioWbBridge is
 
  component RioWbBridge is
    generic(
      EXTENDED_ADDRESS : natural range 0 to 2 := 0;
      DEVICE_IDENTITY : std_logic_vector(15 downto 0);
      DEVICE_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
      DEVICE_REV : std_logic_vector(31 downto 0);
      ASSY_IDENTITY : std_logic_vector(15 downto 0);
      ASSY_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
      ASSY_REV : std_logic_vector(15 downto 0));
    port(
      clk : in std_logic;
      areset_n : in std_logic;
      enable : in std_logic;
 
      readFrameEmpty_i : in std_logic;
      readFrame_o : out std_logic;
      readContent_o : out std_logic;
      readContentEnd_i : in std_logic;
      readContentData_i : in std_logic_vector(31 downto 0);
      writeFrameFull_i : in std_logic;
      writeFrame_o : out std_logic;
      writeFrameAbort_o : out std_logic;
      writeContent_o : out std_logic;
      writeContentData_o : out std_logic_vector(31 downto 0);
 
      cyc_o : out std_logic;
      stb_o : out std_logic;
      we_o : out std_logic;
      adr_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
      sel_o : out std_logic_vector(7 downto 0);
      dat_o : out std_logic_vector(63 downto 0);
      dat_i : in std_logic_vector(63 downto 0);
      err_i : in std_logic;
      ack_i : in std_logic);
  end component;
 
  -----------------------------------------------------------------------------
  -- 
  -----------------------------------------------------------------------------
 
  signal clk : std_logic;
  signal areset_n : std_logic;
  signal enable : std_logic;
 
  signal writeFrameFull : std_logic;
  signal writeFrame : std_logic;
  signal writeFrameAbort : std_logic;
  signal writeContent : std_logic;
  signal writeContentData : std_logic_vector(31 downto 0);
 
  signal readFrameEmpty : std_logic;
  signal readFrame : std_logic;
  signal readFrameRestart : std_logic;
  signal readFrameAborted : std_logic;
  signal readContentEmpty : std_logic;
  signal readContent : std_logic;
  signal readContentEnd : std_logic;
  signal readContentData : std_logic_vector(31 downto 0);
 
  signal wbCyc : std_logic;
  signal wbStb : std_logic;
  signal wbWe : std_logic;
  signal wbAdr : std_logic_vector(30 downto 0);
  signal wbSel : std_logic_vector(7 downto 0);
  signal wbDatWrite : std_logic_vector(63 downto 0);
  signal wbDatRead : std_logic_vector(63 downto 0);
  signal wbAck : std_logic;
  signal wbErr : std_logic;
 
  signal outboundEmpty : std_logic;
  signal outboundWrite : std_logic;
  signal outboundMessage : TestPortMessagePacketBuffer;
  signal outboundAck : std_logic;
 
  signal inboundEmpty : std_logic;
  signal inboundWrite : std_logic;
  signal inboundMessage : TestPortMessagePacketBuffer;
  signal inboundAck : std_logic;
 
  signal wbMessageEmpty : std_logic;
  signal wbMessageWrite : std_logic;
  signal wbMessage : TestPortMessageWishbone;
  signal wbMessageAck : std_logic;
 
begin
 
  -----------------------------------------------------------------------------
  -- Clock generation.
  -----------------------------------------------------------------------------
  ClockGenerator: process
  begin
    clk <= '0';
    wait for 20 ns;
    clk <= '1';
    wait for 20 ns;
  end process;
 
 
  -----------------------------------------------------------------------------
  -- Serial port emulator.
  -----------------------------------------------------------------------------
  TestDriver: process
 
    -----------------------------------------------------------------------------
    -- Procedures to handle outbound and inbound packets.
    -----------------------------------------------------------------------------
    procedure OutboundFrame(constant frame : in RioFrame) is
    begin
      TestPortPacketBufferWrite(outboundWrite, outboundMessage, outboundAck,
                                frame, false);
    end procedure;
 
    procedure InboundFrame(constant frame : in RioFrame) is
    begin
      TestPortPacketBufferWrite(inboundWrite, inboundMessage, inboundAck,
                                frame, false);
    end procedure;
 
    ---------------------------------------------------------------------------
    -- Procedure to handle wishbone accesses.
    ---------------------------------------------------------------------------
    procedure SetSlaveAccess(constant writeAccess : in boolean;
                             constant address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
                             constant byteSelect : in std_logic_vector(7 downto 0);
                             constant length : in natural range 1 to DATA_SIZE_MAX;
                             constant data : in DoublewordArray(0 to DATA_SIZE_MAX-1);
                             constant latency : natural := 1) is
    begin
      TestPortWishboneWrite(wbMessageWrite, wbMessage, wbMessageAck,
                            writeAccess, address, byteSelect, length, data, latency);
    end procedure;
 
    ---------------------------------------------------------------------------
    -- 
    ---------------------------------------------------------------------------
    function getReadSize(constant rdsize : in std_logic_vector(3 downto 0);
                         constant wdptr : in std_logic) return natural is
    begin
      case rdsize is
        when "0000" | "0001" | "0010" | "0011" =>
          return 1;
        when "0100" | "0110" =>
          return 1;
        when "0101" =>
          return 1;
        when "1000" =>
          return 1;
        when "0111" =>
          return 1;
        when "1001" =>
          return 1;
        when "1010" =>
          return 1;
        when "1011" =>
          if (wdptr = '0') then
            return 1;
          else
            return 2;
          end if;
        when "1100" =>
          if (wdptr = '0') then
            return 4;
          else
            return 8;
          end if;
        when "1101" =>
          if (wdptr = '0') then
            return 12;
          else
            return 16;
          end if;
        when "1110" =>
          if (wdptr = '0') then
            return 20;
          else
            return 24;
          end if;
        when "1111" =>
          if (wdptr = '0') then
            return 28;
          else
            return 32;
          end if;
        when others =>
          return 0;
      end case;
    end function;
 
    function getReadMask(constant rdsize : in std_logic_vector(3 downto 0);
                         constant wdptr : in std_logic) return std_logic_vector is
    begin
      case rdsize is
        when "0000" =>
          if (wdptr = '0') then
            return "10000000";
          else
            return "00001000";
          end if;
        when "0001" =>
          if (wdptr = '0') then
            return "01000000";
          else
            return "00000100";
          end if;
        when "0010" =>
          if (wdptr = '0') then
            return "00100000";
          else
            return "00000010";
          end if;
        when "0011" =>
          if (wdptr = '0') then
            return "00010000";
          else
            return "00000001";
          end if;
        when "0100" =>
          if (wdptr = '0') then
            return "11000000";
          else
            return "00001100";
          end if;
        when "0110" =>
          if (wdptr = '0') then
            return "00110000";
          else
            return "00000011";
          end if;
        when "0101" =>
          if (wdptr = '0') then
            return "11100000";
          else
            return "00000111";
          end if;
        when "1000" =>
          if (wdptr = '0') then
            return "11110000";
          else
            return "00001111";
          end if;
        when "0111" =>
          if (wdptr = '0') then
            return "11111000";
          else
            return "00011111";
          end if;
        when "1001" =>
          if (wdptr = '0') then
            return "11111100";
          else
            return "00111111";
          end if;
        when "1010" =>
          if (wdptr = '0') then
            return "11111110";
          else
            return "01111111";
          end if;
        when others =>
          return "11111111";
      end case;
    end function;
 
    ---------------------------------------------------------------------------
    -- Local variables.
    ---------------------------------------------------------------------------
    variable seed1 : positive := 1;
    variable seed2: positive := 1;
 
    variable rdsize : std_logic_vector(3 downto 0);
    variable wrsize : std_logic_vector(3 downto 0);
    variable wdptr : std_logic;
    variable maintData : DoubleWordArray(0 to 7);
    variable ioData : DoubleWordArray(0 to 31);
    variable frame : RioFrame;
 
  begin
    areset_n <= '0';
    enable <= '1';
 
    inboundWrite <= '0';
    outboundWrite <= '0';
    wbMessageWrite <= '0';
 
    writeFrameFull <= '0';
 
    wait until clk'event and clk = '1';
    wait until clk'event and clk = '1';
    areset_n <= '1';
    wait until clk'event and clk = '1';
    wait until clk'event and clk = '1';
 
    ---------------------------------------------------------------------------
    PrintS("-----------------------------------------------------------------");
    PrintS("TG_RioWbBridge");
    PrintS("-----------------------------------------------------------------");
    PrintS("TG_RioWbBridge-TC1");
    PrintS("Description: Test maintenance requests.");
    PrintS("Requirement: XXXXX");
    PrintS("-----------------------------------------------------------------");
    PrintS("Step 1:");
    PrintS("Action: Send maintenance read request for one word on even offset.");
    PrintS("Result: Check the accesses on the external configuration port.");
    PrintS("-----------------------------------------------------------------");
    ---------------------------------------------------------------------------
    PrintR("TG_RioWbBridge-TC1-Step1");
    ---------------------------------------------------------------------------
 
    InboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
                                tt=>"01", ftype=>FTYPE_MAINTENANCE_CLASS,
                                sourceId=>x"dead", destId=>x"beef",
                                payload=>RioMaintenance(transaction=>"0000",
                                                        size=>"1000",
                                                        tid=>x"aa",
                                                        hopCount=>x"ff",
                                                        configOffset=>"000000000000000000000",
                                                        wdptr=>'0',
                                                        dataLength=>0,
                                                        data=>maintData)));
 
    maintData(0) := x"deadbeef00000000";
    OutboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
                                 tt=>"01", ftype=>FTYPE_MAINTENANCE_CLASS,
                                 sourceId=>x"beef", destId=>x"dead",
                                 payload=>RioMaintenance(transaction=>"0010",
                                                         size=>"0000",
                                                         tid=>x"aa",
                                                         hopCount=>x"ff",
                                                         configOffset=>"000000000000000000000",
                                                         wdptr=>'0',
                                                         dataLength=>1,
                                                         data=>maintData)));
 
    TestWait(inboundEmpty, '1', "inbound frame");
    TestWait(outboundEmpty, '1', "outbound frame");
 
    ---------------------------------------------------------------------------
    PrintS("-----------------------------------------------------------------");
    PrintS("TG_RioWbBridge-TC2");
    PrintS("Description: Test request class packets.");
    PrintS("Requirement: XXXXX");
    PrintS("-----------------------------------------------------------------");
    PrintS("Step 1:");
    PrintS("Action: Send request class NREAD packets for all sizes.");
    PrintS("Result: The Wishbone access should match the inbound packet.");
    PrintS("-----------------------------------------------------------------");
    ---------------------------------------------------------------------------
    PrintR("TG_RioWbBridge-TC2-Step1");
    ---------------------------------------------------------------------------
    -- REMARK: Change the address and tid also...
    for i in 0 to 15 loop
      for j in 0 to 1 loop
        rdsize := std_logic_vector(to_unsigned(i, 4));
        if (j = 0) then
          wdptr := '0';
        else
          wdptr:= '1';
        end if;
 
        CreateRandomPayload(ioData, seed1, seed2);
 
        InboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
                                    tt=>"01", ftype=>FTYPE_REQUEST_CLASS,
                                    sourceId=>x"dead", destId=>x"beef",
                                    payload=>RioNread(rdsize=>rdsize,
                                                      tid=>x"aa",
                                                      address=>"00000000000000000000000000000",
                                                      wdptr=>wdptr,
                                                      xamsbs=>"00")));
 
        OutboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
                                     tt=>"01", ftype=>FTYPE_RESPONSE_CLASS,
                                     sourceId=>x"beef", destId=>x"dead",
                                     payload=>RioResponse(status=>"0000",
                                                          tid=>x"aa",
                                                          dataLength=>getReadSize(rdsize, wdptr),
                                                          data=>ioData)));
 
        SetSlaveAccess(false, "0000000000000000000000000000000",
                       getReadMask(rdsize, wdptr),
                       getReadSize(rdsize, wdptr),
                       ioData);
 
        TestWait(inboundEmpty, '1', "inbound frame");
        TestWait(outboundEmpty, '1', "outbound frame");
        TestWait(wbMessageEmpty, '1', "wishbone access");
      end loop;
    end loop;
 
    ---------------------------------------------------------------------------
    PrintS("-----------------------------------------------------------------");
    PrintS("TG_RioWbBridge-TC3");
    PrintS("Description: Test write class packets.");
    PrintS("Requirement: XXXXX");
    PrintS("-----------------------------------------------------------------");
    PrintS("Step 1:");
    PrintS("Action: Send write class NWRITER packets for all sizes.");
    PrintS("Result: The Wishbone access should match the inbound packet and a ");
    PrintS("        response should be sent.");
    PrintS("-----------------------------------------------------------------");
    ---------------------------------------------------------------------------
    PrintR("TG_RioWbBridge-TC3-Step1");
    ---------------------------------------------------------------------------
    -- REMARK: Change the address and tid also...
    for i in 0 to 15 loop
      for j in 0 to 1 loop
        wrsize := std_logic_vector(to_unsigned(i, 4));
        if (j = 0) then
          wdptr := '0';
        else
          wdptr:= '1';
        end if;
 
        CreateRandomPayload(ioData, seed1, seed2);
 
        InboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
                                    tt=>"01", ftype=>FTYPE_WRITE_CLASS,
                                    sourceId=>x"dead", destId=>x"beef",
                                    payload=>RioNwriteR(wrsize=>wrsize,
                                                        tid=>x"aa",
                                                        address=>"00000000000000000000000000000",
                                                        wdptr=>wdptr,
                                                        xamsbs=>"00",
                                                        dataLength=>getReadSize(wrsize, wdptr),
                                                        data=>ioData)));
 
        OutboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
                                     tt=>"01", ftype=>FTYPE_RESPONSE_CLASS,
                                     sourceId=>x"beef", destId=>x"dead",
                                     payload=>RioResponse(status=>"0000",
                                                          tid=>x"aa",
                                                          dataLength=>0,
                                                          data=>ioData)));
 
        SetSlaveAccess(true, "0000000000000000000000000000000",
                       getReadMask(wrsize, wdptr),
                       getReadSize(wrsize, wdptr),
                       ioData);
 
        TestWait(inboundEmpty, '1', "inbound frame");
        TestWait(outboundEmpty, '1', "outbound frame");
        TestWait(wbMessageEmpty, '1', "wishbone access");
      end loop;
    end loop;
 
    ---------------------------------------------------------------------------
    PrintS("-----------------------------------------------------------------");
    PrintS("Step 2:");
    PrintS("Action: Send write class NWRITE packets for all sizes.");
    PrintS("Result: The Wishbone access should match the inbound packet.");
    PrintS("-----------------------------------------------------------------");
    ---------------------------------------------------------------------------
    PrintR("TG_RioWbBridge-TC3-Step2");
    ---------------------------------------------------------------------------
    -- REMARK: Change the address and tid also...
    for i in 0 to 15 loop
      for j in 0 to 1 loop
        wrsize := std_logic_vector(to_unsigned(i, 4));
        if (j = 0) then
          wdptr := '0';
        else
          wdptr:= '1';
        end if;
 
        CreateRandomPayload(ioData, seed1, seed2);
 
        InboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
                                    tt=>"01", ftype=>FTYPE_WRITE_CLASS,
                                    sourceId=>x"dead", destId=>x"beef",
                                    payload=>RioNwrite(wrsize=>wrsize,
                                                       address=>"00000000000000000000000000000",
                                                       wdptr=>wdptr,
                                                       xamsbs=>"00",
                                                       dataLength=>getReadSize(wrsize, wdptr),
                                                       data=>ioData)));
 
        SetSlaveAccess(true, "0000000000000000000000000000000",
                       getReadMask(wrsize, wdptr),
                       getReadSize(wrsize, wdptr),
                       ioData);
 
        TestWait(inboundEmpty, '1', "inbound frame");
        TestWait(outboundEmpty, '1', "outbound frame");
        TestWait(wbMessageEmpty, '1', "wishbone access");
      end loop;
    end loop;
 
    ---------------------------------------------------------------------------
    -- Test completed.
    ---------------------------------------------------------------------------
 
    TestEnd;
  end process;
 
  -----------------------------------------------------------------------------
  -- Instantiate the test object.
  -----------------------------------------------------------------------------
  TestObject: RioWbBridge
    generic map(
      EXTENDED_ADDRESS=>0,
      DEVICE_IDENTITY=>x"dead",
      DEVICE_VENDOR_IDENTITY=>x"beef",
      DEVICE_REV=>x"c0debabe",
      ASSY_IDENTITY=>x"1111",
      ASSY_VENDOR_IDENTITY=>x"2222",
      ASSY_REV=>x"3333")
    port map(
      clk=>clk,
      areset_n=>areset_n,
      enable=>enable,
      readFrameEmpty_i=>readFrameEmpty,
      readFrame_o=>readFrame,
      readContent_o=>readContent,
      readContentEnd_i=>readContentEnd,
      readContentData_i=>readContentData,
      writeFrameFull_i=>writeFrameFull,
      writeFrame_o=>writeFrame,
      writeFrameAbort_o=>writeFrameAbort,
      writeContent_o=>writeContent,
      writeContentData_o=>writeContentData,
      cyc_o=>wbCyc,
      stb_o=>wbStb,
      we_o=>wbWe,
      adr_o=>wbAdr,
      sel_o=>wbSel,
      dat_o=>wbDatWrite,
      dat_i=>wbDatRead,
      err_i=>wbErr,
      ack_i=>wbAck);
 
  -----------------------------------------------------------------------------
  -- Instantiate the test ports.
  -----------------------------------------------------------------------------
 
  TestPortPacketBufferInst: TestPortPacketBuffer
    port map(
      clk=>clk, areset_n=>areset_n,
      readEmpty_o=>inboundEmpty,
      readWrite_i=>inboundWrite,
      readMessage_i=>inboundMessage,
      readAck_o=>inboundAck,
      writeEmpty_o=>outboundEmpty,
      writeWrite_i=>outboundWrite,
      writeMessage_i=>outboundMessage,
      writeAck_o=>outboundAck,
      readFrameEmpty_o=>readFrameEmpty,
      readFrame_i=>readFrame,
      readFrameRestart_i=>'0',
      readFrameAborted_o=>readFrameAborted,
      readWindowEmpty_o=>open,
      readWindowReset_i=>'0',
      readWindowNext_i=>readFrame,
      readContentEmpty_o=>readContentEmpty,
      readContent_i=>readContent,
      readContentEnd_o=>readContentEnd,
      readContentData_o=>readContentData,
      writeFrame_i=>writeFrame,
      writeFrameAbort_i=>writeFrameAbort,
      writeContent_i=>writeContent,
      writeContentData_i=>writeContentData);
 
  TestPortWishboneInst: TestPortWishbone
    port map(
      clk=>clk,
      areset_n=>areset_n,
      messageEmpty_o=>wbMessageEmpty,
      messageWrite_i=>wbMessageWrite,
      message_i=>wbMessage,
      messageAck_o=>wbMessageAck,
      cyc_i=>wbCyc,
      stb_i=>wbStb,
      we_i=>wbWe,
      adr_i=>wbAdr,
      sel_i=>wbSel,
      dat_i=>wbDatWrite,
      dat_o=>wbDatRead,
      err_o=>wbErr,
      ack_o=>wbAck);
 
end architecture;

Line No.	Rev	Author	Line
1	42	magro732	`-------------------------------------------------------------------------------`
2			`--`
3			`-- RapidIO IP Library Core`
4			`--`
5			`-- This file is part of the RapidIO IP library project`
6			`-- http://www.opencores.org/cores/rio/`
7			`--`
8			`-- Description`
9			`-- Contains automatic test code to verify a RioWbBridge implementation.`
10			`--`
11			`-- To Do:`
12	45	magro732	`-- REMARK: Move the testport package and entities to a seperate file.`
13	42	magro732	`--`
14			`-- Author(s):`
15			`-- - Magnus Rosenius, magro732@opencores.org`
16			`--`
17			`-------------------------------------------------------------------------------`
18			`--`
19			`-- Copyright (C) 2013 Authors and OPENCORES.ORG`
20			`--`
21			`-- This source file may be used and distributed without`
22			`-- restriction provided that this copyright statement is not`
23			`-- removed from the file and that any derivative work contains`
24			`-- the original copyright notice and the associated disclaimer.`
25			`--`
26			`-- This source file is free software; you can redistribute it`
27			`-- and/or modify it under the terms of the GNU Lesser General`
28			`-- Public License as published by the Free Software Foundation;`
29			`-- either version 2.1 of the License, or (at your option) any`
30			`-- later version.`
31			`--`
32			`-- This source is distributed in the hope that it will be`
33			`-- useful, but WITHOUT ANY WARRANTY; without even the implied`
34			`-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
35			`-- PURPOSE. See the GNU Lesser General Public License for more`
36			`-- details.`
37			`--`
38			`-- You should have received a copy of the GNU Lesser General`
39			`-- Public License along with this source; if not, download it`
40			`-- from http://www.opencores.org/lgpl.shtml`
41			`--`
42			`-------------------------------------------------------------------------------`
43
44
45			`-------------------------------------------------------------------------------`
46			`--`
47			`-------------------------------------------------------------------------------`
48			`library ieee;`
49			`use ieee.std_logic_1164.all;`
50			`use work.rio_common.all;`
51
52			`-------------------------------------------------------------------------------`
53			`--`
54			`-------------------------------------------------------------------------------`
55			`package TestPortPackage is`
56			`constant ADDRESS_WIDTH : natural := 31;`
57			`constant DATA_SIZE_MAX : natural := 32;`
58
59			`type TestPortMessageWishbone is record`
60			`writeAccess : boolean;`
61			`address : std_logic_vector(ADDRESS_WIDTH-1 downto 0);`
62			`byteSelect : std_logic_vector(7 downto 0);`
63			`length : natural range 1 to DATA_SIZE_MAX;`
64	44	magro732	`data : DoublewordArray(0 to DATA_SIZE_MAX-1);`
65	42	magro732	`latency : natural;`
66			`end record;`
67
68			`type TestPortMessageSymbol is record`
69			`symbolType : std_logic_vector(1 downto 0);`
70			`symbolContent : std_logic_vector(31 downto 0);`
71			`ignoreIdle : boolean;`
72			`end record;`
73
74			`type TestPortMessagePacketBuffer is record`
75			`frame : RioFrame;`
76			`willAbort : boolean;`
77			`end record;`
78
79			`-----------------------------------------------------------------------------`
80			`--`
81			`-----------------------------------------------------------------------------`
82
83			`component TestPortWishbone is`
84			`port(`
85			`clk : in std_logic;`
86			`areset_n : in std_logic;`
87
88			`messageEmpty_o : out std_logic;`
89			`messageWrite_i : in std_logic;`
90			`message_i : in TestPortMessageWishbone;`
91			`messageAck_o : out std_logic;`
92
93			`cyc_i : in std_logic;`
94			`stb_i : in std_logic;`
95			`we_i : in std_logic;`
96			`adr_i : in std_logic_vector(30 downto 0);`
97			`sel_i : in std_logic_vector(7 downto 0);`
98			`dat_i : in std_logic_vector(63 downto 0);`
99	44	magro732	`dat_o : out std_logic_vector(63 downto 0);`
100	42	magro732	`err_o : out std_logic;`
101			`ack_o : out std_logic);`
102			`end component;`
103
104			`component TestPortPacketBuffer is`
105			`port(`
106			`clk : in std_logic;`
107			`areset_n : in std_logic;`
108
109	44	magro732	`readEmpty_o : out std_logic;`
110			`readWrite_i : in std_logic;`
111			`readMessage_i : in TestPortMessagePacketBuffer;`
112			`readAck_o : out std_logic;`
113	42	magro732
114	44	magro732	`writeEmpty_o : out std_logic;`
115			`writeWrite_i : in std_logic;`
116			`writeMessage_i : in TestPortMessagePacketBuffer;`
117			`writeAck_o : out std_logic;`
118	42	magro732
119			`readFrameEmpty_o : out std_logic;`
120			`readFrame_i : in std_logic;`
121			`readFrameRestart_i : in std_logic;`
122			`readFrameAborted_o : out std_logic;`
123			`readWindowEmpty_o : out std_logic;`
124			`readWindowReset_i : in std_logic;`
125			`readWindowNext_i : in std_logic;`
126			`readContentEmpty_o : out std_logic;`
127			`readContent_i : in std_logic;`
128			`readContentEnd_o : out std_logic;`
129			`readContentData_o : out std_logic_vector(31 downto 0);`
130
131			`writeFrame_i : in std_logic;`
132			`writeFrameAbort_i : in std_logic;`
133			`writeContent_i : in std_logic;`
134			`writeContentData_i : in std_logic_vector(31 downto 0));`
135			`end component;`
136
137			`-----------------------------------------------------------------------------`
138			`--`
139			`-----------------------------------------------------------------------------`
140			`procedure TestPortWishboneWrite(`
141			`signal writeSignal : out std_logic;`
142			`signal messageSignal : out TestPortMessageWishbone;`
143			`signal ackSignal : in std_logic;`
144			`constant writeAccess : in boolean;`
145			`constant address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);`
146			`constant byteSelect : in std_logic_vector(7 downto 0);`
147			`constant length : in natural range 1 to DATA_SIZE_MAX;`
148			`constant data : in DoublewordArray(0 to DATA_SIZE_MAX-1);`
149			`constant latency : natural := 0);`
150
151			`procedure TestPortPacketBufferWrite(`
152			`signal writeSignal : out std_logic;`
153			`signal messageSignal : out TestPortMessagePacketBuffer;`
154			`signal ackSignal : in std_logic;`
155			`constant frame : in RioFrame;`
156			`constant willAbort : boolean := false);`
157
158			`end package;`
159
160			`-------------------------------------------------------------------------------`
161			`--`
162			`-------------------------------------------------------------------------------`
163			`package body TestPortPackage is`
164
165			`-----------------------------------------------------------------------------`
166			`--`
167			`-----------------------------------------------------------------------------`
168			`procedure TestPortWishboneWrite(`
169			`signal writeSignal : out std_logic;`
170			`signal messageSignal : out TestPortMessageWishbone;`
171			`signal ackSignal : in std_logic;`
172			`constant writeAccess : in boolean;`
173			`constant address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);`
174			`constant byteSelect : in std_logic_vector(7 downto 0);`
175			`constant length : in natural range 1 to DATA_SIZE_MAX;`
176			`constant data : in DoublewordArray(0 to DATA_SIZE_MAX-1);`
177			`constant latency : natural := 0) is`
178			`begin`
179			`writeSignal <= '1';`
180			`messageSignal.writeAccess <= writeAccess;`
181			`messageSignal.address <= address;`
182			`messageSignal.byteSelect <= byteSelect;`
183			`messageSignal.length <= length;`
184			`messageSignal.data <= data;`
185			`messageSignal.latency <= latency;`
186			`wait until ackSignal = '1';`
187			`writeSignal <= '0';`
188			`wait until ackSignal = '0';`
189			`end procedure;`
190
191			`-----------------------------------------------------------------------------`
192			`--`
193			`-----------------------------------------------------------------------------`
194			`procedure TestPortPacketBufferWrite(`
195			`signal writeSignal : out std_logic;`
196			`signal messageSignal : out TestPortMessagePacketBuffer;`
197			`signal ackSignal : in std_logic;`
198			`constant frame : in RioFrame;`
199			`constant willAbort : boolean := false) is`
200			`begin`
201			`writeSignal <= '1';`
202			`messageSignal.frame <= frame;`
203			`messageSignal.willAbort <= willAbort;`
204			`wait until ackSignal = '1';`
205			`writeSignal <= '0';`
206			`wait until ackSignal = '0';`
207			`end procedure;`
208
209			`end package body;`
210
211
212
213
214			`-------------------------------------------------------------------------------`
215			`--`
216			`-------------------------------------------------------------------------------`
217			`library ieee;`
218			`use ieee.std_logic_1164.all;`
219			`use ieee.numeric_std.all;`
220			`library std;`
221			`use std.textio.all;`
222			`use work.rio_common.all;`
223			`use work.TestPortPackage.all;`
224
225
226			`-------------------------------------------------------------------------------`
227			`--`
228			`-------------------------------------------------------------------------------`
229			`entity TestPortPacketBuffer is`
230			`port(`
231			`clk : in std_logic;`
232			`areset_n : in std_logic;`
233
234	44	magro732	`readEmpty_o : out std_logic;`
235			`readWrite_i : in std_logic;`
236			`readMessage_i : in TestPortMessagePacketBuffer;`
237			`readAck_o : out std_logic;`
238	42	magro732
239	44	magro732	`writeEmpty_o : out std_logic;`
240			`writeWrite_i : in std_logic;`
241			`writeMessage_i : in TestPortMessagePacketBuffer;`
242			`writeAck_o : out std_logic;`
243	42	magro732
244			`readFrameEmpty_o : out std_logic;`
245			`readFrame_i : in std_logic;`
246			`readFrameRestart_i : in std_logic;`
247			`readFrameAborted_o : out std_logic;`
248			`readWindowEmpty_o : out std_logic;`
249			`readWindowReset_i : in std_logic;`
250			`readWindowNext_i : in std_logic;`
251			`readContentEmpty_o : out std_logic;`
252			`readContent_i : in std_logic;`
253			`readContentEnd_o : out std_logic;`
254			`readContentData_o : out std_logic_vector(31 downto 0);`
255
256			`-- writeFrameFull_o is missing yes, but you can control it from the testbench directly`
257			`-- instead.`
258			`writeFrame_i : in std_logic;`
259			`writeFrameAbort_i : in std_logic;`
260			`writeContent_i : in std_logic;`
261			`writeContentData_i : in std_logic_vector(31 downto 0));`
262			`end entity;`
263
264
265			`-------------------------------------------------------------------------------`
266			`--`
267			`-------------------------------------------------------------------------------`
268			`architecture TestPortPacketBufferPortImpl of TestPortPacketBuffer is`
269			`constant QUEUE_SIZE : natural := 63;`
270	44	magro732	`type QueueArray is array (natural range <>) of TestPortMessagePacketBuffer;`
271	42	magro732
272			`function QueueIndexInc(constant i : natural) return natural is`
273			`variable returnValue : natural;`
274			`begin`
275			`if(i = QUEUE_SIZE) then`
276			`returnValue := 0;`
277			`else`
278			`returnValue := i + 1;`
279			`end if;`
280			`return returnValue;`
281			`end function;`
282
283			`begin`
284
285			`-----------------------------------------------------------------------------`
286			`--`
287			`-----------------------------------------------------------------------------`
288	44	magro732	`Reader: process`
289	42	magro732	`variable frameQueue : QueueArray(0 to QUEUE_SIZE);`
290			`variable front, back, window : natural range 0 to QUEUE_SIZE;`
291			`variable frameIndex : natural;`
292			`begin`
293			`wait until areset_n = '1';`
294
295			`readFrameEmpty_o <= '1';`
296			`readFrameAborted_o <= '0';`
297			`readWindowEmpty_o <= '1';`
298			`readContentEmpty_o <= '1';`
299			`readContentEnd_o <= '0';`
300			`readContentData_o <= (others=>'0');`
301
302			`front := 0;`
303			`back := 0;`
304			`window := 0;`
305			`frameIndex := 0;`
306	44	magro732	`readEmpty_o <= '1';`
307			`readAck_o <= '0';`
308	42	magro732
309			`loop`
310	44	magro732	`wait until clk = '1' or readWrite_i = '1';`
311	42	magro732
312			`if (clk'event) then`
313			`if (readFrame_i = '1') then`
314			`if (back /= front) then`
315			`back := QueueIndexInc(back);`
316			`else`
317	44	magro732	`TestError("READ:BACK:reading when no frame is present");`
318	42	magro732	`end if;`
319			`end if;`
320
321			`if (readFrameRestart_i = '1') then`
322			`frameIndex := 0;`
323			`end if;`
324
325			`if (readWindowReset_i = '1') then`
326			`window := back;`
327			`frameIndex := 0;`
328			`end if;`
329
330			`if (readWindowNext_i = '1') then`
331			`if (window /= front) then`
332			`window := QueueIndexInc(window);`
333			`frameIndex := 0;`
334			`else`
335	44	magro732	`TestError("READ:WINDOW:reading when no frame is present");`
336	42	magro732	`end if;`
337			`end if;`
338
339			`if (readContent_i = '1') then`
340			`if (back /= front) then`
341			`if (frameIndex < frameQueue(window).frame.length) then`
342			`readContentData_o <= frameQueue(window).frame.payload(frameIndex);`
343			`frameIndex := frameIndex + 1;`
344			`if (frameIndex = frameQueue(window).frame.length) then`
345			`readContentEnd_o <= '1';`
346			`else`
347			`readContentEnd_o <= '0';`
348			`end if;`
349			`else`
350	44	magro732	`TestError("READ:CONTENT:reading when frame has ended");`
351	42	magro732	`end if;`
352			`else`
353	44	magro732	`TestError("READ:CONTENT:reading when no frame is present");`
354	42	magro732	`end if;`
355			`end if;`
356
357			`if (front = back) then`
358			`readFrameEmpty_o <= '1';`
359			`else`
360			`readFrameEmpty_o <= '0';`
361			`end if;`
362
363			`if (front = window) then`
364			`readWindowEmpty_o <= '1';`
365			`readContentEmpty_o <= '1';`
366			`else`
367			`readWindowEmpty_o <= '0';`
368			`if (frameIndex /= frameQueue(window).frame.length) then`
369			`readContentEmpty_o <= '0';`
370			`else`
371			`readContentEmpty_o <= '1';`
372			`end if;`
373			`end if;`
374
375			`if (front = back) then`
376	44	magro732	`readEmpty_o <= '1';`
377	42	magro732	`else`
378	44	magro732	`readEmpty_o <= '0';`
379	42	magro732	`end if;`
380	44	magro732	`elsif (readWrite_i'event) then`
381			`frameQueue(front) := readMessage_i;`
382	42	magro732	`front := QueueIndexInc(front);`
383
384	44	magro732	`readEmpty_o <= '0';`
385			`readAck_o <= '1';`
386			`wait until readWrite_i = '0';`
387			`readAck_o <= '0';`
388	42	magro732	`end if;`
389			`end loop;`
390			`end process;`
391
392			`-----------------------------------------------------------------------------`
393			`--`
394			`-----------------------------------------------------------------------------`
395	44	magro732	`Writer: process`
396	42	magro732	`variable frameQueue : QueueArray(0 to QUEUE_SIZE);`
397			`variable front, back : natural range 0 to QUEUE_SIZE;`
398			`variable frameIndex : natural range 0 to 69;`
399			`begin`
400			`wait until areset_n = '1';`
401
402	44	magro732	`writeEmpty_o <= '1';`
403			`writeAck_o <= '0';`
404	42	magro732
405			`front := 0;`
406			`back := 0;`
407			`frameIndex := 0;`
408
409			`loop`
410	44	magro732	`wait until clk = '1' or writeWrite_i = '1';`
411	42	magro732
412			`if (clk'event) then`
413
414			`if (writeFrame_i = '1') then`
415			`if (frameIndex = 0) then`
416	44	magro732	`TestError("WRITE:Empty frame written.");`
417	42	magro732	`end if;`
418			`if (frameIndex /= frameQueue(back).frame.length) then`
419	44	magro732	`TestError("WRITE:Frame with unmatching length was written.");`
420	42	magro732	`end if;`
421			`if (back /= front) then`
422			`back := QueueIndexInc(back);`
423			`else`
424	44	magro732	`TestError("WRITE:Unexpected frame written.");`
425	42	magro732	`end if;`
426			`frameIndex := 0;`
427			`end if;`
428
429			`if (writeFrameAbort_i = '1') then`
430			`if (back /= front) then`
431			`if (frameQueue(back).willAbort) then`
432	44	magro732	`TestCompare(frameIndex,`
433			`frameQueue(back).frame.length,`
434			`"frameIndex abort");`
435	42	magro732	`back := QueueIndexInc(back);`
436			`else`
437	44	magro732	`TestError("WRITE:Not expecting this frame to abort.");`
438	42	magro732	`end if;`
439			`end if;`
440			`frameIndex := 0;`
441			`end if;`
442
443			`if (writeContent_i = '1') then`
444			`if (frameIndex < frameQueue(back).frame.length) then`
445	44	magro732	`TestCompare(writeContentData_i,`
446			`frameQueue(back).frame.payload(frameIndex),`
447			`"frame content");`
448	42	magro732	`frameIndex := frameIndex + 1;`
449			`else`
450	44	magro732	`TestError("WRITE:Receiving more frame content than expected.");`
451	42	magro732	`end if;`
452			`end if;`
453
454			`if (front = back) then`
455	44	magro732	`writeEmpty_o <= '1';`
456	42	magro732	`else`
457	44	magro732	`writeEmpty_o <= '0';`
458	42	magro732	`end if;`
459	44	magro732	`elsif (writeWrite_i'event) then`
460			`frameQueue(front) := writeMessage_i;`
461	42	magro732	`front := QueueIndexInc(front);`
462
463	44	magro732	`writeEmpty_o <= '0';`
464			`writeAck_o <= '1';`
465			`wait until writeWrite_i = '0';`
466			`writeAck_o <= '0';`
467	42	magro732	`end if;`
468			`end loop;`
469			`end process;`
470
471			`end architecture;`
472
473
474
475			`-------------------------------------------------------------------------------`
476			`--`
477			`-------------------------------------------------------------------------------`
478			`library ieee;`
479			`use ieee.std_logic_1164.all;`
480			`use ieee.numeric_std.all;`
481			`library std;`
482			`use std.textio.all;`
483			`use work.rio_common.all;`
484			`use work.TestPortPackage.all;`
485
486
487			`-------------------------------------------------------------------------------`
488			`--`
489			`-------------------------------------------------------------------------------`
490			`entity TestPortWishbone is`
491			`port(`
492			`clk : in std_logic;`
493			`areset_n : in std_logic;`
494
495			`messageEmpty_o : out std_logic;`
496			`messageWrite_i : in std_logic;`
497			`message_i : in TestPortMessageWishbone;`
498			`messageAck_o : out std_logic;`
499
500			`cyc_i : in std_logic;`

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