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-------------------------------------------------------------------------------
-- 
-- RapidIO IP Library Core
-- 
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
-- 
-- Description
-- Contains automatic test code to verify a RioWbBridge implementation.
-- 
-- To Do:
-- - Move the testport package and entities to a seperate file.
-- - Add testcases to NWRITE to cover all possible access lengths, not just the
--   maximum as presently.
-- 
-- Author(s): 
-- - Magnus Rosenius, magro732@opencores.org 
-- 
-------------------------------------------------------------------------------
-- 
-- Copyright (C) 2013 Authors and OPENCORES.ORG 
-- 
-- This source file may be used and distributed without 
-- restriction provided that this copyright statement is not 
-- removed from the file and that any derivative work contains 
-- the original copyright notice and the associated disclaimer. 
-- 
-- This source file is free software; you can redistribute it 
-- and/or modify it under the terms of the GNU Lesser General 
-- Public License as published by the Free Software Foundation; 
-- either version 2.1 of the License, or (at your option) any 
-- later version. 
-- 
-- This source is distributed in the hope that it will be 
-- useful, but WITHOUT ANY WARRANTY; without even the implied 
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
-- PURPOSE. See the GNU Lesser General Public License for more 
-- details. 
-- 
-- You should have received a copy of the GNU Lesser General 
-- Public License along with this source; if not, download it 
-- from http://www.opencores.org/lgpl.shtml 
-- 
-------------------------------------------------------------------------------
 
 
-------------------------------------------------------------------------------
-- TestRioWbBridge.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
use work.rio_common.all;
use work.TestPortPackage.all;
 
 
-------------------------------------------------------------------------------
-- Entity for TestRioWbBridge.
-------------------------------------------------------------------------------
entity TestRioWbBridge is
end entity;
 
 
-------------------------------------------------------------------------------
-- Architecture for TestRioWbBridge.
-------------------------------------------------------------------------------
architecture TestRioWbBridgeImpl of TestRioWbBridge is
 
  component RioWbBridge is
    generic(
      EXTENDED_ADDRESS : natural range 0 to 2 := 0;
      DEVICE_IDENTITY : std_logic_vector(15 downto 0);
      DEVICE_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
      DEVICE_REV : std_logic_vector(31 downto 0);
      ASSY_IDENTITY : std_logic_vector(15 downto 0);
      ASSY_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
      ASSY_REV : std_logic_vector(15 downto 0));
    port(
      clk : in std_logic;
      areset_n : in std_logic;
      enable : in std_logic;
 
      readFrameEmpty_i : in std_logic;
      readFrame_o : out std_logic;
      readContent_o : out std_logic;
      readContentEnd_i : in std_logic;
      readContentData_i : in std_logic_vector(31 downto 0);
      writeFrameFull_i : in std_logic;
      writeFrame_o : out std_logic;
      writeFrameAbort_o : out std_logic;
      writeContent_o : out std_logic;
      writeContentData_o : out std_logic_vector(31 downto 0);
 
      cyc_o : out std_logic;
      stb_o : out std_logic;
      we_o : out std_logic;
      adr_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
      sel_o : out std_logic_vector(7 downto 0);
      dat_o : out std_logic_vector(63 downto 0);
      dat_i : in std_logic_vector(63 downto 0);
      err_i : in std_logic;
      ack_i : in std_logic);
  end component;
 
  -----------------------------------------------------------------------------
  -- 
  -----------------------------------------------------------------------------
 
  signal clk : std_logic;
  signal areset_n : std_logic;
  signal enable : std_logic;
 
  signal writeFrameFull : std_logic;
  signal writeFrame : std_logic;
  signal writeFrameAbort : std_logic;
  signal writeContent : std_logic;
  signal writeContentData : std_logic_vector(31 downto 0);
 
  signal readFrameEmpty : std_logic;
  signal readFrame : std_logic;
  signal readFrameRestart : std_logic;
  signal readFrameAborted : std_logic;
  signal readContentEmpty : std_logic;
  signal readContent : std_logic;
  signal readContentEnd : std_logic;
  signal readContentData : std_logic_vector(31 downto 0);
 
  signal wbCyc : std_logic;
  signal wbStb : std_logic;
  signal wbWe : std_logic;
  signal wbAdr : std_logic_vector(30 downto 0);
  signal wbSel : std_logic_vector(7 downto 0);
  signal wbDatWrite : std_logic_vector(63 downto 0);
  signal wbDatRead : std_logic_vector(63 downto 0);
  signal wbAck : std_logic;
  signal wbErr : std_logic;
 
  signal outboundEmpty : std_logic;
  signal outboundWrite : std_logic;
  signal outboundMessage : TestPortMessagePacketBuffer;
  signal outboundAck : std_logic;
 
  signal inboundEmpty : std_logic;
  signal inboundWrite : std_logic;
  signal inboundMessage : TestPortMessagePacketBuffer;
  signal inboundAck : std_logic;
 
  signal wbMessageEmpty : std_logic;
  signal wbMessageWrite : std_logic;
  signal wbMessage : TestPortMessageWishbone;
  signal wbMessageAck : std_logic;
 
begin
 
  -----------------------------------------------------------------------------
  -- Clock generation.
  -----------------------------------------------------------------------------
  ClockGenerator: process
  begin
    clk <= '0';
    wait for 20 ns;
    clk <= '1';
    wait for 20 ns;
  end process;
 
 
  -----------------------------------------------------------------------------
  -- Serial port emulator.
  -----------------------------------------------------------------------------
  TestDriver: process
 
    -----------------------------------------------------------------------------
    -- Procedures to handle outbound and inbound packets.
    -----------------------------------------------------------------------------
    procedure OutboundFrame(constant frame : in RioFrame) is
    begin
      TestPortPacketBufferWrite(outboundWrite, outboundMessage, outboundAck,
                                frame, false);
    end procedure;
 
    procedure InboundFrame(constant frame : in RioFrame) is
    begin
      TestPortPacketBufferWrite(inboundWrite, inboundMessage, inboundAck,
                                frame, false);
    end procedure;
 
    ---------------------------------------------------------------------------
    -- Procedure to handle wishbone accesses.
    ---------------------------------------------------------------------------
    procedure SetSlaveAccess(constant writeAccess : in boolean;
                             constant addressIn : in std_logic_vector(30 downto 0);
                             constant byteSelect : in std_logic_vector(7 downto 0);
                             constant length : in natural range 1 to 32;
                             constant dataIn : in DoublewordArray(0 to 31);
                             constant latency : natural := 1) is
      variable address : std_logic_vector(ADDRESS_WIDTH_MAX-1 downto 0);
    begin
      address := x"00000000" & '0' & addressIn;
      for i in 0 to length-1 loop
        if (i = (length-1)) then
          TestPortWishboneWrite(wbMessageWrite, wbMessage, wbMessageAck,
                                writeAccess, address, byteSelect, dataIn(i), false, latency);
        else
          TestPortWishboneWrite(wbMessageWrite, wbMessage, wbMessageAck,
                                writeAccess, address, byteSelect, dataIn(i), true, latency);
          address := std_logic_vector(unsigned(address)+1);
        end if;
      end loop;
    end procedure;
 
    ---------------------------------------------------------------------------
    -- 
    ---------------------------------------------------------------------------
    function getReadSize(constant rdsize : in std_logic_vector(3 downto 0);
                         constant wdptr : in std_logic) return natural is
    begin
      case rdsize is
        when "0000" | "0001" | "0010" | "0011" =>
          return 1;
        when "0100" | "0110" =>
          return 1;
        when "0101" =>
          return 1;
        when "1000" =>
          return 1;
        when "0111" =>
          return 1;
        when "1001" =>
          return 1;
        when "1010" =>
          return 1;
        when "1011" =>
          if (wdptr = '0') then
            return 1;
          else
            return 2;
          end if;
        when "1100" =>
          if (wdptr = '0') then
            return 4;
          else
            return 8;
          end if;
        when "1101" =>
          if (wdptr = '0') then
            return 12;
          else
            return 16;
          end if;
        when "1110" =>
          if (wdptr = '0') then
            return 20;
          else
            return 24;
          end if;
        when "1111" =>
          if (wdptr = '0') then
            return 28;
          else
            return 32;
          end if;
        when others =>
          return 0;
      end case;
    end function;
 
    function getReadMask(constant rdsize : in std_logic_vector(3 downto 0);
                         constant wdptr : in std_logic) return std_logic_vector is
    begin
      case rdsize is
        when "0000" =>
          if (wdptr = '0') then
            return "10000000";
          else
            return "00001000";
          end if;
        when "0001" =>
          if (wdptr = '0') then
            return "01000000";
          else
            return "00000100";
          end if;
        when "0010" =>
          if (wdptr = '0') then
            return "00100000";
          else
            return "00000010";
          end if;
        when "0011" =>
          if (wdptr = '0') then
            return "00010000";
          else
            return "00000001";
          end if;
        when "0100" =>
          if (wdptr = '0') then
            return "11000000";
          else
            return "00001100";
          end if;
        when "0110" =>
          if (wdptr = '0') then
            return "00110000";
          else
            return "00000011";
          end if;
        when "0101" =>
          if (wdptr = '0') then
            return "11100000";
          else
            return "00000111";
          end if;
        when "1000" =>
          if (wdptr = '0') then
            return "11110000";
          else
            return "00001111";
          end if;
        when "0111" =>
          if (wdptr = '0') then
            return "11111000";
          else
            return "00011111";
          end if;
        when "1001" =>
          if (wdptr = '0') then
            return "11111100";
          else
            return "00111111";
          end if;
        when "1010" =>
          if (wdptr = '0') then
            return "11111110";
          else
            return "01111111";
          end if;
        when others =>
          return "11111111";
      end case;
    end function;
 
    ---------------------------------------------------------------------------
    -- Local variables.
    ---------------------------------------------------------------------------
    variable seed1 : positive := 1;
    variable seed2: positive := 1;
 
    variable rdsize : std_logic_vector(3 downto 0);
    variable wrsize : std_logic_vector(3 downto 0);
    variable wdptr : std_logic;
    variable maintData : DoubleWordArray(0 to 7);
    variable ioData : DoubleWordArray(0 to 31);
    variable frame : RioFrame;
 
  begin
    areset_n <= '0';
    enable <= '1';
 
    inboundWrite <= '0';
    outboundWrite <= '0';
    wbMessageWrite <= '0';
 
    writeFrameFull <= '0';
 
    wait until clk'event and clk = '1';
    wait until clk'event and clk = '1';
    areset_n <= '1';
    wait until clk'event and clk = '1';
    wait until clk'event and clk = '1';
 
    ---------------------------------------------------------------------------
    PrintS("-----------------------------------------------------------------");
    PrintS("TG_RioWbBridge");
    PrintS("-----------------------------------------------------------------");
    PrintS("TG_RioWbBridge-TC1");
    PrintS("Description: Test maintenance requests.");
    PrintS("Requirement: XXXXX");
    PrintS("-----------------------------------------------------------------");
    PrintS("Step 1:");
    PrintS("Action: Send maintenance read request for one word on even offset.");
    PrintS("Result: Check the accesses on the external configuration port.");
    PrintS("-----------------------------------------------------------------");
    ---------------------------------------------------------------------------
    PrintR("TG_RioWbBridge-TC1-Step1");
    ---------------------------------------------------------------------------
 
    InboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
                                tt=>"01", ftype=>FTYPE_MAINTENANCE_CLASS,
                                sourceId=>x"dead", destId=>x"beef",
                                payload=>RioMaintenance(transaction=>"0000",
                                                        size=>"1000",
                                                        tid=>x"aa",
                                                        hopCount=>x"ff",
                                                        configOffset=>"000000000000000000000",
                                                        wdptr=>'0',
                                                        dataLength=>0,
                                                        data=>maintData)));
 
    maintData(0) := x"deadbeef00000000";
    OutboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
                                 tt=>"01", ftype=>FTYPE_MAINTENANCE_CLASS,
                                 sourceId=>x"beef", destId=>x"dead",
                                 payload=>RioMaintenance(transaction=>"0010",
                                                         size=>"0000",
                                                         tid=>x"aa",
                                                         hopCount=>x"ff",
                                                         configOffset=>"000000000000000000000",
                                                         wdptr=>'0',
                                                         dataLength=>1,
                                                         data=>maintData)));
 
    TestWait(inboundEmpty, '1', "inbound frame");
    TestWait(outboundEmpty, '1', "outbound frame");
 
    ---------------------------------------------------------------------------
    PrintS("-----------------------------------------------------------------");
    PrintS("TG_RioWbBridge-TC2");
    PrintS("Description: Test request class packets.");
    PrintS("Requirement: XXXXX");
    PrintS("-----------------------------------------------------------------");
    PrintS("Step 1:");
    PrintS("Action: Send request class NREAD packets for all sizes.");
    PrintS("Result: The Wishbone access should match the inbound packet.");
    PrintS("-----------------------------------------------------------------");
    ---------------------------------------------------------------------------
    PrintR("TG_RioWbBridge-TC2-Step1");
    ---------------------------------------------------------------------------
    -- REMARK: Change the address and tid also...
    for i in 0 to 15 loop
      for j in 0 to 1 loop
        rdsize := std_logic_vector(to_unsigned(i, 4));
        if (j = 0) then
          wdptr := '0';
        else
          wdptr := '1';
        end if;
 
        CreateRandomPayload(ioData, seed1, seed2);
 
        InboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
                                    tt=>"01", ftype=>FTYPE_REQUEST_CLASS,
                                    sourceId=>x"dead", destId=>x"beef",
                                    payload=>RioNread(rdsize=>rdsize,
                                                      tid=>x"aa",
                                                      address=>"00000000000000000000000000000",
                                                      wdptr=>wdptr,
                                                      xamsbs=>"00")));
 
        OutboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
                                     tt=>"01", ftype=>FTYPE_RESPONSE_CLASS,
                                     sourceId=>x"beef", destId=>x"dead",
                                     payload=>RioResponse(status=>"0000",
                                                          tid=>x"aa",
                                                          dataLength=>getReadSize(rdsize, wdptr),
                                                          data=>ioData)));
 
        SetSlaveAccess(false, "0000000000000000000000000000000",
                       getReadMask(rdsize, wdptr),
                       getReadSize(rdsize, wdptr),
                       ioData);
 
        TestWait(inboundEmpty, '1', "inbound frame");
        TestWait(outboundEmpty, '1', "outbound frame");
        TestWait(wbMessageEmpty, '1', "wishbone access");
      end loop;
    end loop;
 
    ---------------------------------------------------------------------------
    PrintS("-----------------------------------------------------------------");
    PrintS("TG_RioWbBridge-TC3");
    PrintS("Description: Test write class packets.");
    PrintS("Requirement: XXXXX");
    PrintS("-----------------------------------------------------------------");
    PrintS("Step 1:");
    PrintS("Action: Send write class NWRITER packets for all sizes.");
    PrintS("Result: The Wishbone access should match the inbound packet and a ");
    PrintS("        response should be sent.");
    PrintS("-----------------------------------------------------------------");
    ---------------------------------------------------------------------------
    PrintR("TG_RioWbBridge-TC3-Step1");
    ---------------------------------------------------------------------------
    -- REMARK: Change the address and tid also...
    -- REMARK: Not really all sizes, add sizes in between the fixed as well.
    for i in 0 to 15 loop
      for j in 0 to 1 loop
        wrsize := std_logic_vector(to_unsigned(i, 4));
        if (j = 0) then
          wdptr := '0';
        else
          wdptr := '1';
        end if;
 
        CreateRandomPayload(ioData, seed1, seed2);
 
        InboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
                                    tt=>"01", ftype=>FTYPE_WRITE_CLASS,
                                    sourceId=>x"dead", destId=>x"beef",
                                    payload=>RioNwriteR(wrsize=>wrsize,
                                                        tid=>x"aa",
                                                        address=>"00000000000000000000000000000",
                                                        wdptr=>wdptr,
                                                        xamsbs=>"00",
                                                        dataLength=>getReadSize(wrsize, wdptr),
                                                        data=>ioData)));
 
        OutboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
                                     tt=>"01", ftype=>FTYPE_RESPONSE_CLASS,
                                     sourceId=>x"beef", destId=>x"dead",
                                     payload=>RioResponse(status=>"0000",
                                                          tid=>x"aa",
                                                          dataLength=>0,
                                                          data=>ioData)));
 
        SetSlaveAccess(true, "0000000000000000000000000000000",
                       getReadMask(wrsize, wdptr),
                       getReadSize(wrsize, wdptr),
                       ioData);
 
        TestWait(inboundEmpty, '1', "inbound frame");
        TestWait(outboundEmpty, '1', "outbound frame");
        TestWait(wbMessageEmpty, '1', "wishbone access");
      end loop;
    end loop;
 
    ---------------------------------------------------------------------------
    PrintS("-----------------------------------------------------------------");
    PrintS("Step 2:");
    PrintS("Action: Send write class NWRITE packets for all sizes.");
    PrintS("Result: The Wishbone access should match the inbound packet.");
    PrintS("-----------------------------------------------------------------");
    ---------------------------------------------------------------------------
    PrintR("TG_RioWbBridge-TC3-Step2");
    ---------------------------------------------------------------------------
    -- REMARK: Change the address and tid also...
    for i in 0 to 15 loop
      for j in 0 to 1 loop
        wrsize := std_logic_vector(to_unsigned(i, 4));
        if (j = 0) then
          wdptr := '0';
        else
          wdptr:= '1';
        end if;
 
        CreateRandomPayload(ioData, seed1, seed2);
 
        InboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
                                    tt=>"01", ftype=>FTYPE_WRITE_CLASS,
                                    sourceId=>x"dead", destId=>x"beef",
                                    payload=>RioNwrite(wrsize=>wrsize,
                                                       address=>"00000000000000000000000000000",
                                                       wdptr=>wdptr,
                                                       xamsbs=>"00",
                                                       dataLength=>getReadSize(wrsize, wdptr),
                                                       data=>ioData)));
 
        SetSlaveAccess(true, "0000000000000000000000000000000",
                       getReadMask(wrsize, wdptr),
                       getReadSize(wrsize, wdptr),
                       ioData);
 
        TestWait(inboundEmpty, '1', "inbound frame");
        TestWait(outboundEmpty, '1', "outbound frame");
        TestWait(wbMessageEmpty, '1', "wishbone access");
      end loop;
    end loop;
 
    ---------------------------------------------------------------------------
    -- Test completed.
    ---------------------------------------------------------------------------
 
    TestEnd;
  end process;
 
  -----------------------------------------------------------------------------
  -- Instantiate the test object.
  -----------------------------------------------------------------------------
  TestObject: RioWbBridge
    generic map(
      EXTENDED_ADDRESS=>0,
      DEVICE_IDENTITY=>x"dead",
      DEVICE_VENDOR_IDENTITY=>x"beef",
      DEVICE_REV=>x"c0debabe",
      ASSY_IDENTITY=>x"1111",
      ASSY_VENDOR_IDENTITY=>x"2222",
      ASSY_REV=>x"3333")
    port map(
      clk=>clk,
      areset_n=>areset_n,
      enable=>enable,
      readFrameEmpty_i=>readFrameEmpty,
      readFrame_o=>readFrame,
      readContent_o=>readContent,
      readContentEnd_i=>readContentEnd,
      readContentData_i=>readContentData,
      writeFrameFull_i=>writeFrameFull,
      writeFrame_o=>writeFrame,
      writeFrameAbort_o=>writeFrameAbort,
      writeContent_o=>writeContent,
      writeContentData_o=>writeContentData,
      cyc_o=>wbCyc,
      stb_o=>wbStb,
      we_o=>wbWe,
      adr_o=>wbAdr,
      sel_o=>wbSel,
      dat_o=>wbDatWrite,
      dat_i=>wbDatRead,
      err_i=>wbErr,
      ack_i=>wbAck);
 
  -----------------------------------------------------------------------------
  -- Instantiate the test ports.
  -----------------------------------------------------------------------------
 
  TestPortPacketBufferInst: TestPortPacketBuffer
    generic map(READ_CONTENT_END_DATA_VALID=>false)
    port map(
      clk=>clk, areset_n=>areset_n,
      readEmpty_o=>inboundEmpty,
      readWrite_i=>inboundWrite,
      readMessage_i=>inboundMessage,
      readAck_o=>inboundAck,
      writeEmpty_o=>outboundEmpty,
      writeWrite_i=>outboundWrite,
      writeMessage_i=>outboundMessage,
      writeAck_o=>outboundAck,
      readFrameEmpty_o=>readFrameEmpty,
      readFrame_i=>readFrame,
      readFrameRestart_i=>'0',
      readFrameAborted_o=>readFrameAborted,
      readWindowEmpty_o=>open,
      readWindowReset_i=>'0',
      readWindowNext_i=>readFrame,
      readContentEmpty_o=>readContentEmpty,
      readContent_i=>readContent,
      readContentEnd_o=>readContentEnd,
      readContentData_o=>readContentData,
      writeFrame_i=>writeFrame,
      writeFrameAbort_i=>writeFrameAbort,
      writeContent_i=>writeContent,
      writeContentData_i=>writeContentData);
 
  TestPortWishboneInst: TestPortWishbone
    port map(
      clk=>clk,
      areset_n=>areset_n,
      messageEmpty_o=>wbMessageEmpty,
      messageWrite_i=>wbMessageWrite,
      message_i=>wbMessage,
      messageAck_o=>wbMessageAck,
      cyc_i=>wbCyc,
      stb_i=>wbStb,
      we_i=>wbWe,
      adr_i=>wbAdr,
      sel_i=>wbSel,
      dat_i=>wbDatWrite,
      dat_o=>wbDatRead,
      err_o=>wbErr,
      ack_o=>wbAck);
 
end architecture;

Line No.	Rev	Author	Line
1	42	magro732	`-------------------------------------------------------------------------------`
2			`--`
3			`-- RapidIO IP Library Core`
4			`--`
5			`-- This file is part of the RapidIO IP library project`
6			`-- http://www.opencores.org/cores/rio/`
7			`--`
8			`-- Description`
9			`-- Contains automatic test code to verify a RioWbBridge implementation.`
10			`--`
11			`-- To Do:`
12	47	magro732	`-- - Move the testport package and entities to a seperate file.`
13			`-- - Add testcases to NWRITE to cover all possible access lengths, not just the`
14			`-- maximum as presently.`
15	42	magro732	`--`
16			`-- Author(s):`
17			`-- - Magnus Rosenius, magro732@opencores.org`
18			`--`
19			`-------------------------------------------------------------------------------`
20			`--`
21			`-- Copyright (C) 2013 Authors and OPENCORES.ORG`
22			`--`
23			`-- This source file may be used and distributed without`
24			`-- restriction provided that this copyright statement is not`
25			`-- removed from the file and that any derivative work contains`
26			`-- the original copyright notice and the associated disclaimer.`
27			`--`
28			`-- This source file is free software; you can redistribute it`
29			`-- and/or modify it under the terms of the GNU Lesser General`
30			`-- Public License as published by the Free Software Foundation;`
31			`-- either version 2.1 of the License, or (at your option) any`
32			`-- later version.`
33			`--`
34			`-- This source is distributed in the hope that it will be`
35			`-- useful, but WITHOUT ANY WARRANTY; without even the implied`
36			`-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
37			`-- PURPOSE. See the GNU Lesser General Public License for more`
38			`-- details.`
39			`--`
40			`-- You should have received a copy of the GNU Lesser General`
41			`-- Public License along with this source; if not, download it`
42			`-- from http://www.opencores.org/lgpl.shtml`
43			`--`
44			`-------------------------------------------------------------------------------`
45
46
47			`-------------------------------------------------------------------------------`
48			`-- TestRioWbBridge.`
49			`-------------------------------------------------------------------------------`
50
51			`library ieee;`
52			`use ieee.std_logic_1164.all;`
53			`use ieee.numeric_std.all;`
54			`use ieee.math_real.all;`
55			`library std;`
56			`use std.textio.all;`
57			`use work.rio_common.all;`
58			`use work.TestPortPackage.all;`
59
60
61			`-------------------------------------------------------------------------------`
62			`-- Entity for TestRioWbBridge.`
63			`-------------------------------------------------------------------------------`
64			`entity TestRioWbBridge is`
65			`end entity;`
66
67
68			`-------------------------------------------------------------------------------`
69			`-- Architecture for TestRioWbBridge.`
70			`-------------------------------------------------------------------------------`
71			`architecture TestRioWbBridgeImpl of TestRioWbBridge is`
72
73			`component RioWbBridge is`
74			`generic(`
75			`EXTENDED_ADDRESS : natural range 0 to 2 := 0;`
76			`DEVICE_IDENTITY : std_logic_vector(15 downto 0);`
77			`DEVICE_VENDOR_IDENTITY : std_logic_vector(15 downto 0);`
78			`DEVICE_REV : std_logic_vector(31 downto 0);`
79			`ASSY_IDENTITY : std_logic_vector(15 downto 0);`
80			`ASSY_VENDOR_IDENTITY : std_logic_vector(15 downto 0);`
81			`ASSY_REV : std_logic_vector(15 downto 0));`
82			`port(`
83			`clk : in std_logic;`
84			`areset_n : in std_logic;`
85	44	magro732	`enable : in std_logic;`
86	42	magro732
87			`readFrameEmpty_i : in std_logic;`
88			`readFrame_o : out std_logic;`
89			`readContent_o : out std_logic;`
90			`readContentEnd_i : in std_logic;`
91			`readContentData_i : in std_logic_vector(31 downto 0);`
92			`writeFrameFull_i : in std_logic;`
93			`writeFrame_o : out std_logic;`
94			`writeFrameAbort_o : out std_logic;`
95			`writeContent_o : out std_logic;`
96			`writeContentData_o : out std_logic_vector(31 downto 0);`
97
98			`cyc_o : out std_logic;`
99			`stb_o : out std_logic;`
100			`we_o : out std_logic;`
101			`adr_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);`
102			`sel_o : out std_logic_vector(7 downto 0);`
103			`dat_o : out std_logic_vector(63 downto 0);`
104			`dat_i : in std_logic_vector(63 downto 0);`
105			`err_i : in std_logic;`
106			`ack_i : in std_logic);`
107			`end component;`
108
109			`-----------------------------------------------------------------------------`
110			`--`
111			`-----------------------------------------------------------------------------`
112
113			`signal clk : std_logic;`
114			`signal areset_n : std_logic;`
115			`signal enable : std_logic;`
116
117			`signal writeFrameFull : std_logic;`
118			`signal writeFrame : std_logic;`
119			`signal writeFrameAbort : std_logic;`
120			`signal writeContent : std_logic;`
121			`signal writeContentData : std_logic_vector(31 downto 0);`
122
123			`signal readFrameEmpty : std_logic;`
124			`signal readFrame : std_logic;`
125			`signal readFrameRestart : std_logic;`
126			`signal readFrameAborted : std_logic;`
127			`signal readContentEmpty : std_logic;`
128			`signal readContent : std_logic;`
129			`signal readContentEnd : std_logic;`
130			`signal readContentData : std_logic_vector(31 downto 0);`
131
132			`signal wbCyc : std_logic;`
133			`signal wbStb : std_logic;`
134			`signal wbWe : std_logic;`
135			`signal wbAdr : std_logic_vector(30 downto 0);`
136			`signal wbSel : std_logic_vector(7 downto 0);`
137			`signal wbDatWrite : std_logic_vector(63 downto 0);`
138			`signal wbDatRead : std_logic_vector(63 downto 0);`
139			`signal wbAck : std_logic;`
140			`signal wbErr : std_logic;`
141
142			`signal outboundEmpty : std_logic;`
143			`signal outboundWrite : std_logic;`
144			`signal outboundMessage : TestPortMessagePacketBuffer;`
145			`signal outboundAck : std_logic;`
146
147			`signal inboundEmpty : std_logic;`
148			`signal inboundWrite : std_logic;`
149			`signal inboundMessage : TestPortMessagePacketBuffer;`
150			`signal inboundAck : std_logic;`
151
152			`signal wbMessageEmpty : std_logic;`
153			`signal wbMessageWrite : std_logic;`
154			`signal wbMessage : TestPortMessageWishbone;`
155			`signal wbMessageAck : std_logic;`
156
157			`begin`
158
159			`-----------------------------------------------------------------------------`
160			`-- Clock generation.`
161			`-----------------------------------------------------------------------------`
162			`ClockGenerator: process`
163			`begin`
164			`clk <= '0';`
165			`wait for 20 ns;`
166			`clk <= '1';`
167			`wait for 20 ns;`
168			`end process;`
169
170
171			`-----------------------------------------------------------------------------`
172			`-- Serial port emulator.`
173			`-----------------------------------------------------------------------------`
174			`TestDriver: process`
175
176			`-----------------------------------------------------------------------------`
177			`-- Procedures to handle outbound and inbound packets.`
178			`-----------------------------------------------------------------------------`
179			`procedure OutboundFrame(constant frame : in RioFrame) is`
180			`begin`
181			`TestPortPacketBufferWrite(outboundWrite, outboundMessage, outboundAck,`
182			`frame, false);`
183			`end procedure;`
184
185			`procedure InboundFrame(constant frame : in RioFrame) is`
186			`begin`
187			`TestPortPacketBufferWrite(inboundWrite, inboundMessage, inboundAck,`
188			`frame, false);`
189			`end procedure;`
190
191			`---------------------------------------------------------------------------`
192			`-- Procedure to handle wishbone accesses.`
193			`---------------------------------------------------------------------------`
194			`procedure SetSlaveAccess(constant writeAccess : in boolean;`
195	47	magro732	`constant addressIn : in std_logic_vector(30 downto 0);`
196	42	magro732	`constant byteSelect : in std_logic_vector(7 downto 0);`
197	47	magro732	`constant length : in natural range 1 to 32;`
198			`constant dataIn : in DoublewordArray(0 to 31);`
199	44	magro732	`constant latency : natural := 1) is`
200	47	magro732	`variable address : std_logic_vector(ADDRESS_WIDTH_MAX-1 downto 0);`
201	42	magro732	`begin`
202	47	magro732	`address := x"00000000" & '0' & addressIn;`
203			`for i in 0 to length-1 loop`
204			`if (i = (length-1)) then`
205			`TestPortWishboneWrite(wbMessageWrite, wbMessage, wbMessageAck,`
206			`writeAccess, address, byteSelect, dataIn(i), false, latency);`
207			`else`
208			`TestPortWishboneWrite(wbMessageWrite, wbMessage, wbMessageAck,`
209			`writeAccess, address, byteSelect, dataIn(i), true, latency);`
210			`address := std_logic_vector(unsigned(address)+1);`
211			`end if;`
212			`end loop;`
213	42	magro732	`end procedure;`
214	44	magro732
215			`---------------------------------------------------------------------------`
216			`--`
217			`---------------------------------------------------------------------------`
218			`function getReadSize(constant rdsize : in std_logic_vector(3 downto 0);`
219			`constant wdptr : in std_logic) return natural is`
220			`begin`
221			`case rdsize is`
222			`when "0000" \| "0001" \| "0010" \| "0011" =>`
223			`return 1;`
224			`when "0100" \| "0110" =>`
225			`return 1;`
226			`when "0101" =>`
227			`return 1;`
228			`when "1000" =>`
229			`return 1;`
230			`when "0111" =>`
231			`return 1;`
232			`when "1001" =>`
233			`return 1;`
234			`when "1010" =>`
235			`return 1;`
236			`when "1011" =>`
237			`if (wdptr = '0') then`
238			`return 1;`
239			`else`
240			`return 2;`
241			`end if;`
242			`when "1100" =>`
243			`if (wdptr = '0') then`
244			`return 4;`
245			`else`
246			`return 8;`
247			`end if;`
248			`when "1101" =>`
249			`if (wdptr = '0') then`
250			`return 12;`
251			`else`
252			`return 16;`
253			`end if;`
254			`when "1110" =>`
255			`if (wdptr = '0') then`
256			`return 20;`
257			`else`
258			`return 24;`
259			`end if;`
260			`when "1111" =>`
261			`if (wdptr = '0') then`
262			`return 28;`
263			`else`
264			`return 32;`
265			`end if;`
266			`when others =>`
267			`return 0;`
268			`end case;`
269			`end function;`
270	42	magro732
271	44	magro732	`function getReadMask(constant rdsize : in std_logic_vector(3 downto 0);`
272			`constant wdptr : in std_logic) return std_logic_vector is`
273			`begin`
274			`case rdsize is`
275			`when "0000" =>`
276			`if (wdptr = '0') then`
277			`return "10000000";`
278			`else`
279			`return "00001000";`
280			`end if;`
281			`when "0001" =>`
282			`if (wdptr = '0') then`
283			`return "01000000";`
284			`else`
285			`return "00000100";`
286			`end if;`
287			`when "0010" =>`
288			`if (wdptr = '0') then`
289			`return "00100000";`
290			`else`
291			`return "00000010";`
292			`end if;`
293			`when "0011" =>`
294			`if (wdptr = '0') then`
295			`return "00010000";`
296			`else`
297			`return "00000001";`
298			`end if;`
299			`when "0100" =>`
300			`if (wdptr = '0') then`
301			`return "11000000";`
302			`else`
303			`return "00001100";`
304			`end if;`
305			`when "0110" =>`
306			`if (wdptr = '0') then`
307			`return "00110000";`
308			`else`
309			`return "00000011";`
310			`end if;`
311			`when "0101" =>`
312			`if (wdptr = '0') then`
313			`return "11100000";`
314			`else`
315			`return "00000111";`
316			`end if;`
317			`when "1000" =>`
318			`if (wdptr = '0') then`
319			`return "11110000";`
320			`else`
321			`return "00001111";`
322			`end if;`
323			`when "0111" =>`
324			`if (wdptr = '0') then`
325			`return "11111000";`
326			`else`
327			`return "00011111";`
328			`end if;`
329			`when "1001" =>`
330			`if (wdptr = '0') then`
331			`return "11111100";`
332			`else`
333			`return "00111111";`
334			`end if;`
335			`when "1010" =>`
336			`if (wdptr = '0') then`
337			`return "11111110";`
338			`else`
339			`return "01111111";`
340			`end if;`
341			`when others =>`
342			`return "11111111";`
343			`end case;`
344			`end function;`
345	42	magro732
346			`---------------------------------------------------------------------------`
347	45	magro732	`-- Local variables.`
348	42	magro732	`---------------------------------------------------------------------------`
349			`variable seed1 : positive := 1;`
350			`variable seed2: positive := 1;`
351
352	44	magro732	`variable rdsize : std_logic_vector(3 downto 0);`
353	45	magro732	`variable wrsize : std_logic_vector(3 downto 0);`
354	44	magro732	`variable wdptr : std_logic;`
355	45	magro732	`variable maintData : DoubleWordArray(0 to 7);`
356	42	magro732	`variable ioData : DoubleWordArray(0 to 31);`
357			`variable frame : RioFrame;`
358
359			`begin`
360			`areset_n <= '0';`
361	44	magro732	`enable <= '1';`
362	42	magro732
363	44	magro732	`inboundWrite <= '0';`
364			`outboundWrite <= '0';`
365			`wbMessageWrite <= '0';`
366
367	42	magro732	`writeFrameFull <= '0';`
368
369			`wait until clk'event and clk = '1';`
370			`wait until clk'event and clk = '1';`
371			`areset_n <= '1';`
372			`wait until clk'event and clk = '1';`
373			`wait until clk'event and clk = '1';`
374
375			`---------------------------------------------------------------------------`
376			`PrintS("-----------------------------------------------------------------");`
377	44	magro732	`PrintS("TG_RioWbBridge");`
378	42	magro732	`PrintS("-----------------------------------------------------------------");`
379	44	magro732	`PrintS("TG_RioWbBridge-TC1");`
380			`PrintS("Description: Test maintenance requests.");`
381	42	magro732	`PrintS("Requirement: XXXXX");`
382			`PrintS("-----------------------------------------------------------------");`
383			`PrintS("Step 1:");`
384			`PrintS("Action: Send maintenance read request for one word on even offset.");`
385			`PrintS("Result: Check the accesses on the external configuration port.");`
386			`PrintS("-----------------------------------------------------------------");`
387			`---------------------------------------------------------------------------`
388	44	magro732	`PrintR("TG_RioWbBridge-TC1-Step1");`
389	42	magro732	`---------------------------------------------------------------------------`
390	45	magro732
391			`InboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",`
392			`tt=>"01", ftype=>FTYPE_MAINTENANCE_CLASS,`
393			`sourceId=>x"dead", destId=>x"beef",`
394			`payload=>RioMaintenance(transaction=>"0000",`
395			`size=>"1000",`
396			`tid=>x"aa",`
397			`hopCount=>x"ff",`
398			`configOffset=>"000000000000000000000",`
399			`wdptr=>'0',`
400			`dataLength=>0,`
401			`data=>maintData)));`
402
403			`maintData(0) := x"deadbeef00000000";`
404			`OutboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",`
405			`tt=>"01", ftype=>FTYPE_MAINTENANCE_CLASS,`
406			`sourceId=>x"beef", destId=>x"dead",`
407			`payload=>RioMaintenance(transaction=>"0010",`
408			`size=>"0000",`
409			`tid=>x"aa",`
410			`hopCount=>x"ff",`
411			`configOffset=>"000000000000000000000",`
412			`wdptr=>'0',`
413			`dataLength=>1,`
414			`data=>maintData)));`
415	42	magro732
416	45	magro732	`TestWait(inboundEmpty, '1', "inbound frame");`
417			`TestWait(outboundEmpty, '1', "outbound frame");`
418
419	44	magro732	`---------------------------------------------------------------------------`
420			`PrintS("-----------------------------------------------------------------");`
421			`PrintS("TG_RioWbBridge-TC2");`
422			`PrintS("Description: Test request class packets.");`
423			`PrintS("Requirement: XXXXX");`
424			`PrintS("-----------------------------------------------------------------");`
425			`PrintS("Step 1:");`
426	45	magro732	`PrintS("Action: Send request class NREAD packets for all sizes.");`
427			`PrintS("Result: The Wishbone access should match the inbound packet.");`
428	44	magro732	`PrintS("-----------------------------------------------------------------");`
429			`---------------------------------------------------------------------------`
430			`PrintR("TG_RioWbBridge-TC2-Step1");`
431			`---------------------------------------------------------------------------`
432	45	magro732	`-- REMARK: Change the address and tid also...`
433	44	magro732	`for i in 0 to 15 loop`
434			`for j in 0 to 1 loop`
435			`rdsize := std_logic_vector(to_unsigned(i, 4));`
436			`if (j = 0) then`
437			`wdptr := '0';`
438			`else`
439	47	magro732	`wdptr := '1';`
440	44	magro732	`end if;`
441
442			`CreateRandomPayload(ioData, seed1, seed2);`
443	42	magro732
444	44	magro732	`InboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",`
445			`tt=>"01", ftype=>FTYPE_REQUEST_CLASS,`
446			`sourceId=>x"dead", destId=>x"beef",`
447			`payload=>RioNread(rdsize=>rdsize,`
448	42	magro732	`tid=>x"aa",`
449	44	magro732	`address=>"00000000000000000000000000000",`
450			`wdptr=>wdptr,`
451			`xamsbs=>"00")));`
452	42	magro732
453	44	magro732	`OutboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",`
454			`tt=>"01", ftype=>FTYPE_RESPONSE_CLASS,`
455			`sourceId=>x"beef", destId=>x"dead",`
456			`payload=>RioResponse(status=>"0000",`
457			`tid=>x"aa",`
458			`dataLength=>getReadSize(rdsize, wdptr),`
459			`data=>ioData)));`
460	42	magro732
461	44	magro732	`SetSlaveAccess(false, "0000000000000000000000000000000",`
462			`getReadMask(rdsize, wdptr),`
463			`getReadSize(rdsize, wdptr),`
464			`ioData);`
465
466			`TestWait(inboundEmpty, '1', "inbound frame");`
467			`TestWait(outboundEmpty, '1', "outbound frame");`
468			`TestWait(wbMessageEmpty, '1', "wishbone access");`
469			`end loop;`
470			`end loop;`
471	42	magro732
472			`---------------------------------------------------------------------------`
473	45	magro732	`PrintS("-----------------------------------------------------------------");`
474			`PrintS("TG_RioWbBridge-TC3");`
475			`PrintS("Description: Test write class packets.");`
476			`PrintS("Requirement: XXXXX");`
477			`PrintS("-----------------------------------------------------------------");`
478			`PrintS("Step 1:");`
479			`PrintS("Action: Send write class NWRITER packets for all sizes.");`
480			`PrintS("Result: The Wishbone access should match the inbound packet and a ");`
481			`PrintS(" response should be sent.");`
482			`PrintS("-----------------------------------------------------------------");`
483			`---------------------------------------------------------------------------`
484			`PrintR("TG_RioWbBridge-TC3-Step1");`
485			`---------------------------------------------------------------------------`
486			`-- REMARK: Change the address and tid also...`
487	47	magro732	`-- REMARK: Not really all sizes, add sizes in between the fixed as well.`
488	45	magro732	`for i in 0 to 15 loop`
489			`for j in 0 to 1 loop`
490			`wrsize := std_logic_vector(to_unsigned(i, 4));`
491			`if (j = 0) then`
492			`wdptr := '0';`
493			`else`
494	47	magro732	`wdptr := '1';`
495	45	magro732	`end if;`
496
497			`CreateRandomPayload(ioData, seed1, seed2);`
498
499			`InboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",`
500			`tt=>"01", ftype=>FTYPE_WRITE_CLASS,`

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