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1 2 magro732 
-------------------------------------------------------------------------------
2 
--
3 
-- RapidIO IP Library Core
4 
--
5 
-- This file is part of the RapidIO IP library project
6 
-- http://www.opencores.org/cores/rio/
7 
--
8 
-- Description
9 
-- Contains commonly used types, functions, procedures and entities used in
10 
-- the RapidIO IP library project.
11 
--
12 
-- To Do:
13 
-- -
14 
--
15 
-- Author(s):
16 
-- - Magnus Rosenius, magro732@opencores.org
17 
--
18 
-------------------------------------------------------------------------------
19 
--
20 
-- Copyright (C) 2013 Authors and OPENCORES.ORG
21 
--
22 
-- This source file may be used and distributed without
23 
-- restriction provided that this copyright statement is not
24 
-- removed from the file and that any derivative work contains
25 
-- the original copyright notice and the associated disclaimer.
26 
--
27 
-- This source file is free software; you can redistribute it
28 
-- and/or modify it under the terms of the GNU Lesser General
29 
-- Public License as published by the Free Software Foundation;
30 
-- either version 2.1 of the License, or (at your option) any
31 
-- later version.
32 
--
33 
-- This source is distributed in the hope that it will be
34 
-- useful, but WITHOUT ANY WARRANTY; without even the implied
35 
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
36 
-- PURPOSE. See the GNU Lesser General Public License for more
37 
-- details.
38 
--
39 
-- You should have received a copy of the GNU Lesser General
40 
-- Public License along with this source; if not, download it
41 
-- from http://www.opencores.org/lgpl.shtml
42 
--
43 
-------------------------------------------------------------------------------
44 
 
45 
 
46 
-------------------------------------------------------------------------------
47 
-- RioCommon library.
48 
-------------------------------------------------------------------------------
49 
library ieee;
50 
use ieee.std_logic_1164.all;
51 
use ieee.numeric_std.all;
52 
use ieee.math_real.all;
53 
use std.textio.all;
54 
 
55 
 
56 
-------------------------------------------------------------------------------
57 
-- RioCommon package description.
58 
-------------------------------------------------------------------------------
59 
package rio_common is
60 46 magro732 
 
61 2 magro732 
  -----------------------------------------------------------------------------
62 46 magro732 
  -- Primitive memory component declarations.
63 
  -----------------------------------------------------------------------------
64 
 
65 
  component MemorySimpleDualPort
66 
    generic(
67 
      ADDRESS_WIDTH : natural := 1;
68 
      DATA_WIDTH : natural := 1);
69 
    port(
70 
      clkA_i : in std_logic;
71 
      enableA_i : in std_logic;
72 
      addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
73 
      dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
74 
 
75 
      clkB_i : in std_logic;
76 
      enableB_i : in std_logic;
77 
      addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
78 
      dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
79 
  end component;
80 
 
81 
  component MemoryDualPort is
82 
    generic(
83 
      ADDRESS_WIDTH : natural := 1;
84 
      DATA_WIDTH : natural := 1);
85 
    port(
86 
      clkA_i : in std_logic;
87 
      enableA_i : in std_logic;
88 
      writeEnableA_i : in std_logic;
89 
      addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
90 
      dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
91 
      dataA_o : out std_logic_vector(DATA_WIDTH-1 downto 0);
92 
 
93 
      clkB_i : in std_logic;
94 
      enableB_i : in std_logic;
95 
      addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
96 
      dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
97 
  end component;
98 
 
99 
  -----------------------------------------------------------------------------
100 
  -- Logical layer component declarations.
101 
  -----------------------------------------------------------------------------
102 
 
103 
  component RioLogicalCommon is
104 
    generic(
105 
      PORTS : natural);
106 
    port(
107 
      clk : in std_logic;
108 
      areset_n : in std_logic;
109 
      enable : in std_logic;
110 
 
111 
      readFrameEmpty_i : in std_logic;
112 
      readFrame_o : out std_logic;
113 
      readContent_o : out std_logic;
114 
      readContentEnd_i : in std_logic;
115 
      readContentData_i : in std_logic_vector(31 downto 0);
116 
 
117 
      writeFrameFull_i : in std_logic;
118 
      writeFrame_o : out std_logic;
119 
      writeFrameAbort_o : out std_logic;
120 
      writeContent_o : out std_logic;
121 
      writeContentData_o : out std_logic_vector(31 downto 0);
122 
 
123 
      inboundCyc_o : out std_logic;
124 
      inboundStb_o : out std_logic;
125 
      inboundAdr_o : out std_logic_vector(7 downto 0);
126 
      inboundDat_o : out std_logic_vector(31 downto 0);
127 
      inboundAck_i : in std_logic;
128 
 
129 
      outboundCyc_i : in std_logic_vector(PORTS-1 downto 0);
130 
      outboundStb_i : in std_logic_vector(PORTS-1 downto 0);
131 
      outboundDat_i : in std_logic_vector(32*PORTS-1 downto 0);
132 
      outboundAck_o : out std_logic_vector(PORTS-1 downto 0));
133 
  end component;
134 
 
135 
  component RioLogicalMaintenance is
136 
    port(
137 
      clk : in std_logic;
138 
      areset_n : in std_logic;
139 
      enable : in std_logic;
140 
 
141 
      readRequestReady_i : in std_logic;
142 
      writeRequestReady_i : in std_logic;
143 
      offset_i : in std_logic_vector(20 downto 0);
144 
      wdptr_i : in std_logic;
145 
      payloadLength_i : in std_logic_vector(3 downto 0);
146 
      payloadIndex_o : out std_logic_vector(3 downto 0);
147 
      payload_i : in std_logic_vector(31 downto 0);
148 
      done_o : out std_logic;
149 
 
150 
      readResponseReady_o : out std_logic;
151 
      writeResponseReady_o : out std_logic;
152 
      wdptr_o : out std_logic;
153 
      payloadLength_o : out std_logic_vector(3 downto 0);
154 
      payloadIndex_i : in std_logic_vector(3 downto 0);
155 
      payload_o : out std_logic_vector(31 downto 0);
156 
      done_i : in std_logic;
157 
 
158 
      configStb_o : out std_logic;
159 
      configWe_o : out std_logic;
160 
      configAdr_o : out std_logic_vector(21 downto 0);
161 
      configDat_o : out std_logic_vector(31 downto 0);
162 
      configDat_i : in std_logic_vector(31 downto 0);
163 
      configAck_i : in std_logic);
164 
  end component;
165 
 
166 
  component MaintenanceInbound is
167 
    port(
168 
      clk : in std_logic;
169 
      areset_n : in std_logic;
170 
      enable : in std_logic;
171 
 
172 
      readRequestReady_o : out std_logic;
173 
      writeRequestReady_o : out std_logic;
174 
      readResponseReady_o : out std_logic;
175 
      writeResponseReady_o : out std_logic;
176 
      portWriteReady_o : out std_logic;
177 
      vc_o : out std_logic;
178 
      crf_o : out std_logic;
179 
      prio_o : out std_logic_vector(1 downto 0);
180 
      tt_o : out std_logic_vector(1 downto 0);
181 
      dstid_o : out std_logic_vector(31 downto 0);
182 
      srcid_o : out std_logic_vector(31 downto 0);
183 
      tid_o : out std_logic_vector(7 downto 0);
184 
      hop_o : out std_logic_vector(7 downto 0);
185 
      offset_o : out std_logic_vector(20 downto 0);
186 
      wdptr_o : out std_logic;
187 
      payloadLength_o : out std_logic_vector(3 downto 0);
188 
      payloadIndex_i : in std_logic_vector(3 downto 0);
189 
      payload_o : out std_logic_vector(31 downto 0);
190 
      done_i : in std_logic;
191 
 
192 
      inboundCyc_i : in std_logic;
193 
      inboundStb_i : in std_logic;
194 
      inboundAdr_i : in std_logic_vector(7 downto 0);
195 
      inboundDat_i : in std_logic_vector(31 downto 0);
196 
      inboundAck_o : out std_logic);
197 
  end component;
198 
 
199 
  component MaintenanceOutbound is
200 
    port(
201 
      clk : in std_logic;
202 
      areset_n : in std_logic;
203 
      enable : in std_logic;
204 
 
205 
      readRequestReady_i : in std_logic;
206 
      writeRequestReady_i : in std_logic;
207 
      readResponseReady_i : in std_logic;
208 
      writeResponseReady_i : in std_logic;
209 
      portWriteReady_i : in std_logic;
210 
      vc_i : in std_logic;
211 
      crf_i : in std_logic;
212 
      prio_i : in std_logic_vector(1 downto 0);
213 
      tt_i : in std_logic_vector(1 downto 0);
214 
      dstid_i : in std_logic_vector(31 downto 0);
215 
      srcid_i : in std_logic_vector(31 downto 0);
216 
      status_i : in std_logic_vector(3 downto 0);
217 
      tid_i : in std_logic_vector(7 downto 0);
218 
      hop_i : in std_logic_vector(7 downto 0);
219 
      offset_i : in std_logic_vector(20 downto 0);
220 
      wdptr_i : in std_logic;
221 
      payloadLength_i : in std_logic_vector(3 downto 0);
222 
      payloadIndex_o : out std_logic_vector(3 downto 0);
223 
      payload_i : in std_logic_vector(31 downto 0);
224 
      done_o : out std_logic;
225 
 
226 
      outboundCyc_o : out std_logic;
227 
      outboundStb_o : out std_logic;
228 
      outboundDat_o : out std_logic_vector(31 downto 0);
229 
      outboundAck_i : in std_logic);
230 
  end component;
231 
 
232 
  component RioPacketBuffer is
233 
    generic(
234 
      SIZE_ADDRESS_WIDTH : natural := 6;
235 
      CONTENT_ADDRESS_WIDTH : natural := 8);
236 
    port(
237 
      clk : in std_logic;
238 
      areset_n : in std_logic;
239 
 
240 
      inboundWriteFrameFull_o : out std_logic;
241 
      inboundWriteFrame_i : in std_logic;
242 
      inboundWriteFrameAbort_i : in std_logic;
243 
      inboundWriteContent_i : in std_logic;
244 
      inboundWriteContentData_i : in std_logic_vector(31 downto 0);
245 
      inboundReadFrameEmpty_o : out std_logic;
246 
      inboundReadFrame_i : in std_logic;
247 
      inboundReadFrameRestart_i : in std_logic;
248 
      inboundReadFrameAborted_o : out std_logic;
249 
      inboundReadContentEmpty_o : out std_logic;
250 
      inboundReadContent_i : in std_logic;
251 
      inboundReadContentEnd_o : out std_logic;
252 
      inboundReadContentData_o : out std_logic_vector(31 downto 0);
253 
 
254 
      outboundWriteFrameFull_o : out std_logic;
255 
      outboundWriteFrame_i : in std_logic;
256 
      outboundWriteFrameAbort_i : in std_logic;
257 
      outboundWriteContent_i : in std_logic;
258 
      outboundWriteContentData_i : in std_logic_vector(31 downto 0);
259 
      outboundReadFrameEmpty_o : out std_logic;
260 
      outboundReadFrame_i : in std_logic;
261 
      outboundReadFrameRestart_i : in std_logic;
262 
      outboundReadFrameAborted_o : out std_logic;
263 
      outboundReadContentEmpty_o : out std_logic;
264 
      outboundReadContent_i : in std_logic;
265 
      outboundReadContentEnd_o : out std_logic;
266 
      outboundReadContentData_o : out std_logic_vector(31 downto 0));
267 
  end component;
268 
 
269 
  -----------------------------------------------------------------------------
270 2 magro732 
  -- Commonly used types.
271 
  -----------------------------------------------------------------------------
272 
  type Array1 is array (natural range <>) of
273 
    std_logic;
274 
  type Array2 is array (natural range <>) of
275 
    std_logic_vector(1 downto 0);
276 
  type Array3 is array (natural range <>) of
277 
    std_logic_vector(2 downto 0);
278 
  type Array4 is array (natural range <>) of
279 
    std_logic_vector(3 downto 0);
280 
  type Array5 is array (natural range <>) of
281 
    std_logic_vector(4 downto 0);
282 
  type Array8 is array (natural range <>) of
283 
    std_logic_vector(7 downto 0);
284 
  type Array9 is array (natural range <>) of
285 
    std_logic_vector(8 downto 0);
286 
  type Array10 is array (natural range <>) of
287 
    std_logic_vector(9 downto 0);
288 
  type Array16 is array (natural range <>) of
289 
    std_logic_vector(15 downto 0);
290 
  type Array32 is array (natural range <>) of
291 
    std_logic_vector(31 downto 0);
292 
  type Array34 is array (natural range <>) of
293 
    std_logic_vector(33 downto 0);
294 
 
295 
  -----------------------------------------------------------------------------
296 
  -- Commonly used constants.
297 
  -----------------------------------------------------------------------------
298 
 
299 
  -- STYPE0 constants.
300 
  constant STYPE0_PACKET_ACCEPTED : std_logic_vector(2 downto 0) := "000";
301 
  constant STYPE0_PACKET_RETRY : std_logic_vector(2 downto 0) := "001";
302 
  constant STYPE0_PACKET_NOT_ACCEPTED : std_logic_vector(2 downto 0) := "010";
303 
  constant STYPE0_RESERVED : std_logic_vector(2 downto 0) := "011";
304 
  constant STYPE0_STATUS : std_logic_vector(2 downto 0) := "100";
305 
  constant STYPE0_VC_STATUS : std_logic_vector(2 downto 0) := "101";
306 
  constant STYPE0_LINK_RESPONSE : std_logic_vector(2 downto 0) := "110";
307 
  constant STYPE0_IMPLEMENTATION_DEFINED : std_logic_vector(2 downto 0) := "111";
308 
 
309 
  -- STYPE1 constants.
310 
  constant STYPE1_START_OF_PACKET : std_logic_vector(2 downto 0) := "000";
311 
  constant STYPE1_STOMP : std_logic_vector(2 downto 0) := "001";
312 
  constant STYPE1_END_OF_PACKET : std_logic_vector(2 downto 0) := "010";
313 
  constant STYPE1_RESTART_FROM_RETRY : std_logic_vector(2 downto 0) := "011";
314 
  constant STYPE1_LINK_REQUEST : std_logic_vector(2 downto 0) := "100";
315 
  constant STYPE1_MULTICAST_EVENT : std_logic_vector(2 downto 0) := "101";
316 
  constant STYPE1_RESERVED : std_logic_vector(2 downto 0) := "110";
317 
  constant STYPE1_NOP : std_logic_vector(2 downto 0) := "111";
318 
 
319 
  -- FTYPE constants.
320 
  constant FTYPE_REQUEST_CLASS : std_logic_vector(3 downto 0) := "0010";
321 
  constant FTYPE_WRITE_CLASS : std_logic_vector(3 downto 0) := "0101";
322 
  constant FTYPE_STREAMING_WRITE_CLASS : std_logic_vector(3 downto 0) := "0110";
323 
  constant FTYPE_MAINTENANCE_CLASS : std_logic_vector(3 downto 0) := "1000";
324 
  constant FTYPE_RESPONSE_CLASS : std_logic_vector(3 downto 0) := "1101";
325 
  constant FTYPE_DOORBELL_CLASS : std_logic_vector(3 downto 0) := "1010";
326 
  constant FTYPE_MESSAGE_CLASS : std_logic_vector(3 downto 0) := "0010";
327 
 
328 
  -- TTYPE Constants
329 
  constant TTYPE_MAINTENANCE_READ_REQUEST : std_logic_vector(3 downto 0) := "0000";
330 
  constant TTYPE_MAINTENANCE_WRITE_REQUEST : std_logic_vector(3 downto 0) := "0001";
331 
  constant TTYPE_MAINTENANCE_READ_RESPONSE : std_logic_vector(3 downto 0) := "0010";
332 
  constant TTYPE_MAINTENANCE_WRITE_RESPONSE : std_logic_vector(3 downto 0) := "0011";
333 
  constant TTYPE_NREAD_TRANSACTION : std_logic_vector(3 downto 0) := "0100";
334 
  constant TTYPE_NWRITE_TRANSACTION : std_logic_vector(3 downto 0) := "0100";
335 
 
336 
  constant LINK_REQUEST_CMD_RESET_DEVICE : std_logic_vector(2 downto 0) := "011";
337 
  constant LINK_REQUEST_CMD_INPUT_STATUS : std_logic_vector(2 downto 0) := "100";
338 
 
339 
  constant PACKET_NOT_ACCEPTED_CAUSE_UNEXPECTED_ACKID : std_logic_vector(4 downto 0) := "00001";
340 
  constant PACKET_NOT_ACCEPTED_CAUSE_CONTROL_CRC : std_logic_vector(4 downto 0) := "00010";
341 
  constant PACKET_NOT_ACCEPTED_CAUSE_NON_MAINTENANCE_STOPPED : std_logic_vector(4 downto 0) := "00011";
342 
  constant PACKET_NOT_ACCEPTED_CAUSE_PACKET_CRC : std_logic_vector(4 downto 0) := "00100";
343 
  constant PACKET_NOT_ACCEPTED_CAUSE_INVALID_CHARACTER : std_logic_vector(4 downto 0) := "00101";
344 
  constant PACKET_NOT_ACCEPTED_CAUSE_NO_RESOURCES : std_logic_vector(4 downto 0) := "00110";
345 
  constant PACKET_NOT_ACCEPTED_CAUSE_LOSS_DESCRAMBLER : std_logic_vector(4 downto 0) := "00111";
346 
  constant PACKET_NOT_ACCEPTED_CAUSE_GENERAL_ERROR : std_logic_vector(4 downto 0) := "11111";
347 
 
348 
  -----------------------------------------------------------------------------
349 
  -- Types used in simulations.
350 
  -----------------------------------------------------------------------------
351 
  type ByteArray is array (natural range <>) of
352 
    std_logic_vector(7 downto 0);
353 
  type HalfwordArray is array (natural range <>) of
354 
    std_logic_vector(15 downto 0);
355 
  type WordArray is array (natural range <>) of
356 
    std_logic_vector(31 downto 0);
357 
  type DoublewordArray is array (natural range <>) of
358 
    std_logic_vector(63 downto 0);
359 
 
360 
  -- Type defining a RapidIO frame.
361 
  type RioFrame is record
362 
    length : natural range 0 to 69;
363 
    payload : WordArray(0 to 68);
364 
  end record;
365 
  type RioFrameArray is array (natural range <>) of RioFrame;
366 
 
367 
  -- Type defining a RapidIO payload.
368 
  type RioPayload is record
369 
    length : natural range 0 to 133;
370 
    data : HalfwordArray(0 to 132);
371 
  end record;
372 
 
373 
  -----------------------------------------------------------------------------
374 
  -- Crc5 calculation function.
375 
  -- ITU, polynom=0x15.
376 
  -----------------------------------------------------------------------------
377 
  function Crc5(constant data : in std_logic_vector(18 downto 0);
378 
                constant crc : in std_logic_vector(4 downto 0))
379 
    return std_logic_vector;
380 
 
381 
  ---------------------------------------------------------------------------
382 
  -- Create a RapidIO physical layer control symbol.
383 
  ---------------------------------------------------------------------------
384 
  function RioControlSymbolCreate(
385 
    constant stype0 : in std_logic_vector(2 downto 0);
386 
    constant parameter0 : in std_logic_vector(4 downto 0);
387 
    constant parameter1 : in std_logic_vector(4 downto 0);
388 
    constant stype1 : in std_logic_vector(2 downto 0);
389 
    constant cmd : in std_logic_vector(2 downto 0))
390 
    return std_logic_vector;
391 
 
392 
  -----------------------------------------------------------------------------
393 
  -- Crc16 calculation function.
394 
  -- CITT, polynom=0x1021.
395 
  -----------------------------------------------------------------------------
396 
  function Crc16(constant data : in std_logic_vector(15 downto 0);
397 
                 constant crc : in std_logic_vector(15 downto 0))
398 
    return std_logic_vector;
399 
 
400 
  ---------------------------------------------------------------------------
401 
  -- Create a randomly initialized data array.
402 
  ---------------------------------------------------------------------------
403 
  procedure CreateRandomPayload(
404 
    variable payload : out HalfwordArray(0 to 132);
405 
    variable seed1 : inout positive;
406 
    variable seed2 : inout positive);
407 
  procedure CreateRandomPayload(
408 
    variable payload : out DoublewordArray(0 to 31);
409 
    variable seed1 : inout positive;
410 
    variable seed2 : inout positive);
411 
 
412 
  ---------------------------------------------------------------------------
413 
  -- Create a generic RapidIO frame.
414 
  ---------------------------------------------------------------------------
415 
  function RioFrameCreate(
416 
    constant ackId : in std_logic_vector(4 downto 0);
417 
    constant vc : in std_logic;
418 
    constant crf : in std_logic;
419 
    constant prio : in std_logic_vector(1 downto 0);
420 
    constant tt : in std_logic_vector(1 downto 0);
421 
    constant ftype : in std_logic_vector(3 downto 0);
422 
    constant sourceId : in std_logic_vector(15 downto 0);
423 
    constant destId : in std_logic_vector(15 downto 0);
424 
    constant payload : in RioPayload)
425 
    return RioFrame;
426 
 
427 
  ---------------------------------------------------------------------------
428 
  -- Create a NWRITE RapidIO frame.
429 
  ---------------------------------------------------------------------------
430 
  function RioNwrite(
431 
    constant wrsize : in std_logic_vector(3 downto 0);
432 45 magro732 
    constant address : in std_logic_vector(28 downto 0);
433 
    constant wdptr : in std_logic;
434 
    constant xamsbs : in std_logic_vector(1 downto 0);
435 
    constant dataLength : in natural range 1 to 32;
436 
    constant data : in DoublewordArray(0 to 31))
437 
    return RioPayload;
438 
 
439 
  ---------------------------------------------------------------------------
440 
  -- Create a NWRITER RapidIO frame.
441 
  ---------------------------------------------------------------------------
442 
  function RioNwriteR(
443 
    constant wrsize : in std_logic_vector(3 downto 0);
444 2 magro732 
    constant tid : in std_logic_vector(7 downto 0);
445 
    constant address : in std_logic_vector(28 downto 0);
446 
    constant wdptr : in std_logic;
447 
    constant xamsbs : in std_logic_vector(1 downto 0);
448 
    constant dataLength : in natural range 1 to 32;
449 
    constant data : in DoublewordArray(0 to 31))
450 
    return RioPayload;
451 
 
452 
  ---------------------------------------------------------------------------
453 
  -- Create a NREAD RapidIO frame.
454 
  ---------------------------------------------------------------------------
455 
  function RioNread(
456 
    constant rdsize : in std_logic_vector(3 downto 0);
457 
    constant tid : in std_logic_vector(7 downto 0);
458 
    constant address : in std_logic_vector(28 downto 0);
459 
    constant wdptr : in std_logic;
460 
    constant xamsbs : in std_logic_vector(1 downto 0))
461 
    return RioPayload;
462 
 
463 
  ---------------------------------------------------------------------------
464 
  -- Create a RESPONSE RapidIO frame.
465 
  ---------------------------------------------------------------------------
466 
  function RioResponse(
467 
    constant status : in std_logic_vector(3 downto 0);
468 
    constant tid : in std_logic_vector(7 downto 0);
469 
    constant dataLength : in natural range 0 to 32;
470 
    constant data : in DoublewordArray(0 to 31))
471 
    return RioPayload;
472 
 
473 
  ---------------------------------------------------------------------------
474 
  -- Create a Maintenance RapidIO frame.
475 
  ---------------------------------------------------------------------------
476 
  function RioMaintenance(
477 
    constant transaction : in std_logic_vector(3 downto 0);
478 
    constant size : in std_logic_vector(3 downto 0);
479 
    constant tid : in std_logic_vector(7 downto 0);
480 
    constant hopCount : in std_logic_vector(7 downto 0);
481 
    constant configOffset : in std_logic_vector(20 downto 0);
482 
    constant wdptr : in std_logic;
483 
    constant dataLength : in natural range 0 to 8;
484 
    constant data : in DoublewordArray(0 to 7))
485 
    return RioPayload;
486 
 
487 
  -----------------------------------------------------------------------------
488 
  -- Function to convert a std_logic_vector to a string.
489 
  -----------------------------------------------------------------------------
490 
  function byteToString(constant byte : std_logic_vector(7 downto 0))
491 
    return string;
492 
 
493 40 magro732 
  -----------------------------------------------------------------------------
494 
  -- Function to print a std_logic_vector.
495 
  -----------------------------------------------------------------------------
496 
  function to_string(constant value : std_logic_vector)
497 
    return string;
498 
 
499 2 magro732 
  ---------------------------------------------------------------------------
500 
  -- Procedure to print to report file and output
501 
  ---------------------------------------------------------------------------
502 
  procedure PrintR( constant str : string );
503 
 
504 
  ---------------------------------------------------------------------------
505 
  -- Procedure to print to spec file
506 
  ---------------------------------------------------------------------------
507 
  procedure PrintS( constant str : string );
508 
 
509 
  ---------------------------------------------------------------------------
510 
  -- Procedure to Assert Expression
511 
  ---------------------------------------------------------------------------
512 
  procedure AssertE( constant exp: boolean; constant str : string );
513 
 
514 
  ---------------------------------------------------------------------------
515 
  -- Procedure to Print Error
516 
  ---------------------------------------------------------------------------
517 
  procedure PrintE( constant str : string );
518 
 
519 
  ---------------------------------------------------------------------------
520 40 magro732 
  -- Procedures for test control.
521 2 magro732 
  ---------------------------------------------------------------------------
522 40 magro732 
 
523 
  procedure TestWarning(constant tag : in string);
524 
  procedure TestError(constant tag : in string;
525 
                      constant stopAtError : in boolean := true);
526 
  procedure TestCompare(constant expression : in boolean;
527 
                        constant tag : in string := "";
528 
                        constant stopAtError : in boolean := true);
529 
  procedure TestCompare(constant got : in std_logic;
530 
                        constant expected : in std_logic;
531 
                        constant tag : in string := "";
532 
                        constant stopAtError : in boolean := true);
533 
  procedure TestCompare(constant got : in std_logic_vector;
534 
                        constant expected : in std_logic_vector;
535 
                        constant tag : in string := "";
536 
                        constant stopAtError : in boolean := true);
537 
  procedure TestCompare(constant got : in natural;
538 
                        constant expected : in natural;
539 
                        constant tag : in string := "";
540 
                        constant stopAtError : in boolean := true);
541 
  procedure TestCompare(constant got : in time;
542 
                        constant expected : in time;
543 
                        constant tag : in string := "";
544 
                        constant stopAtError : in boolean := true);
545 
 
546 
  procedure TestWait(signal waitSignal : in std_logic;
547 
                     constant waitValue : in std_logic;
548 
                     constant tag : in string := "";
549 
                     constant waitTime : in time := 1 ms;
550 
                     constant stopAtError : in boolean := true);
551 
  procedure TestWait(signal waitSignal : in std_logic;
552 
                     constant waitValue : in std_logic;
553 
                     signal ackSignal : inout std_logic;
554 
                     constant tag : in string := "";
555 
                     constant waitTime : in time := 1 ms;
556 
                     constant stopAtError : in boolean := true);
557 
 
558 2 magro732 
  procedure TestEnd;
559 
 
560 
end package;
561 
 
562 
-------------------------------------------------------------------------------
563 
-- RioCommon package body description.
564 
-------------------------------------------------------------------------------
565 
package body rio_common is
566 
  -----------------------------------------------------------------------------
567 
  -- Crc5 calculation function.
568 
  -- ITU, polynom=0x15.
569 
  -----------------------------------------------------------------------------
570 
  function Crc5(constant data : in std_logic_vector(18 downto 0);
571 
                constant crc : in std_logic_vector(4 downto 0))
572 
    return std_logic_vector is
573 
    type crcTableType is array (0 to 31) of std_logic_vector(7 downto 0);
574 
    constant crcTable : crcTableType := (
575 
      x"00", x"15", x"1f", x"0a", x"0b", x"1e", x"14", x"01",
576 
      x"16", x"03", x"09", x"1c", x"1d", x"08", x"02", x"17",
577 
      x"19", x"0c", x"06", x"13", x"12", x"07", x"0d", x"18",
578 
      x"0f", x"1a", x"10", x"05", x"04", x"11", x"1b", x"0e" );
579 
    variable index : natural range 0 to 31;
580 
    variable result : std_logic_vector(4 downto 0);
581 
  begin
582 
    result := crc;
583 
    index := to_integer(unsigned(data(18 downto 14) xor result));
584 
    result := crcTable(index)(4 downto 0);
585 
    index := to_integer(unsigned(data(13 downto 9) xor result));
586 
    result := crcTable(index)(4 downto 0);
587 
    index := to_integer(unsigned(data(8 downto 4) xor result));
588 
    result := crcTable(index)(4 downto 0);
589 
    index := to_integer(unsigned((data(3 downto 0) & '0') xor result));
590 
    return crcTable(index)(4 downto 0);
591 
  end Crc5;
592 
 
593 
  ---------------------------------------------------------------------------
594 
  -- Create a RapidIO physical layer control symbol.
595 
  ---------------------------------------------------------------------------
596 
  function RioControlSymbolCreate(
597 
    constant stype0 : in std_logic_vector(2 downto 0);
598 
    constant parameter0 : in std_logic_vector(4 downto 0);
599 
    constant parameter1 : in std_logic_vector(4 downto 0);
600 
    constant stype1 : in std_logic_vector(2 downto 0);
601 
    constant cmd : in std_logic_vector(2 downto 0))
602 
    return std_logic_vector is
603 37 magro732 
    variable returnValue : std_logic_vector(23 downto 0);
604 2 magro732 
    variable symbolData : std_logic_vector(18 downto 0);
605 
  begin
606 
    symbolData(18 downto 16) := stype0;
607 
    symbolData(15 downto 11) := parameter0;
608 
    symbolData(10 downto 6) := parameter1;
609 
    symbolData(5 downto 3) := stype1;
610 
    symbolData(2 downto 0) := cmd;
611 
 
612 37 magro732 
    returnValue(23 downto 5) := symbolData;
613 
    returnValue(4 downto 0) := Crc5(symbolData, "11111");
614 2 magro732 
 
615 
    return returnValue;
616 
  end function;
617 
 
618 
  -----------------------------------------------------------------------------
619 
  -- Crc16 calculation function.
620 
  -- CITT, polynom=0x1021.
621 
  -----------------------------------------------------------------------------
622 
  function Crc16(constant data : in std_logic_vector(15 downto 0);
623 
                 constant crc : in std_logic_vector(15 downto 0))
624 
    return std_logic_vector is
625 
    type crcTableType is array (0 to 255) of std_logic_vector(15 downto 0);
626 
    constant crcTable : crcTableType := (
627 
      x"0000", x"1021", x"2042", x"3063", x"4084", x"50a5", x"60c6", x"70e7",
628 
      x"8108", x"9129", x"a14a", x"b16b", x"c18c", x"d1ad", x"e1ce", x"f1ef",
629 
      x"1231", x"0210", x"3273", x"2252", x"52b5", x"4294", x"72f7", x"62d6",
630 
      x"9339", x"8318", x"b37b", x"a35a", x"d3bd", x"c39c", x"f3ff", x"e3de",
631 
      x"2462", x"3443", x"0420", x"1401", x"64e6", x"74c7", x"44a4", x"5485",
632 
      x"a56a", x"b54b", x"8528", x"9509", x"e5ee", x"f5cf", x"c5ac", x"d58d",
633 
      x"3653", x"2672", x"1611", x"0630", x"76d7", x"66f6", x"5695", x"46b4",
634 
      x"b75b", x"a77a", x"9719", x"8738", x"f7df", x"e7fe", x"d79d", x"c7bc",
635 
      x"48c4", x"58e5", x"6886", x"78a7", x"0840", x"1861", x"2802", x"3823",
636 
      x"c9cc", x"d9ed", x"e98e", x"f9af", x"8948", x"9969", x"a90a", x"b92b",
637 
      x"5af5", x"4ad4", x"7ab7", x"6a96", x"1a71", x"0a50", x"3a33", x"2a12",
638 
      x"dbfd", x"cbdc", x"fbbf", x"eb9e", x"9b79", x"8b58", x"bb3b", x"ab1a",
639 
      x"6ca6", x"7c87", x"4ce4", x"5cc5", x"2c22", x"3c03", x"0c60", x"1c41",
640 
      x"edae", x"fd8f", x"cdec", x"ddcd", x"ad2a", x"bd0b", x"8d68", x"9d49",
641 
      x"7e97", x"6eb6", x"5ed5", x"4ef4", x"3e13", x"2e32", x"1e51", x"0e70",
642 
      x"ff9f", x"efbe", x"dfdd", x"cffc", x"bf1b", x"af3a", x"9f59", x"8f78",
643 
      x"9188", x"81a9", x"b1ca", x"a1eb", x"d10c", x"c12d", x"f14e", x"e16f",
644 
      x"1080", x"00a1", x"30c2", x"20e3", x"5004", x"4025", x"7046", x"6067",
645 
      x"83b9", x"9398", x"a3fb", x"b3da", x"c33d", x"d31c", x"e37f", x"f35e",
646 
      x"02b1", x"1290", x"22f3", x"32d2", x"4235", x"5214", x"6277", x"7256",
647 
      x"b5ea", x"a5cb", x"95a8", x"8589", x"f56e", x"e54f", x"d52c", x"c50d",
648 
      x"34e2", x"24c3", x"14a0", x"0481", x"7466", x"6447", x"5424", x"4405",
649 
      x"a7db", x"b7fa", x"8799", x"97b8", x"e75f", x"f77e", x"c71d", x"d73c",
650 
      x"26d3", x"36f2", x"0691", x"16b0", x"6657", x"7676", x"4615", x"5634",
651 
      x"d94c", x"c96d", x"f90e", x"e92f", x"99c8", x"89e9", x"b98a", x"a9ab",
652 
      x"5844", x"4865", x"7806", x"6827", x"18c0", x"08e1", x"3882", x"28a3",
653 
      x"cb7d", x"db5c", x"eb3f", x"fb1e", x"8bf9", x"9bd8", x"abbb", x"bb9a",
654 
      x"4a75", x"5a54", x"6a37", x"7a16", x"0af1", x"1ad0", x"2ab3", x"3a92",
655 
      x"fd2e", x"ed0f", x"dd6c", x"cd4d", x"bdaa", x"ad8b", x"9de8", x"8dc9",
656 
      x"7c26", x"6c07", x"5c64", x"4c45", x"3ca2", x"2c83", x"1ce0", x"0cc1",
657 
      x"ef1f", x"ff3e", x"cf5d", x"df7c", x"af9b", x"bfba", x"8fd9", x"9ff8",
658 
      x"6e17", x"7e36", x"4e55", x"5e74", x"2e93", x"3eb2", x"0ed1", x"1ef0" );
659 
    variable index : natural range 0 to 255;
660 
    variable result : std_logic_vector(15 downto 0);
661 
  begin
662 
    result := crc;
663 
    index := to_integer(unsigned(data(15 downto 8) xor result(15 downto 8)));
664 
    result := crcTable(index) xor (result(7 downto 0) & x"00");
665 
    index := to_integer(unsigned(data(7 downto 0) xor result(15 downto 8)));
666 
    result := crcTable(index) xor (result(7 downto 0) & x"00");
667 
    return result;
668 
  end Crc16;
669 
 
670 
  ---------------------------------------------------------------------------
671 
  -- Create a randomly initialized data array.
672 
  ---------------------------------------------------------------------------
673 
  procedure CreateRandomPayload(
674 
    variable payload : out HalfwordArray(0 to 132);
675 
    variable seed1 : inout positive;
676 
    variable seed2 : inout positive) is
677 
    variable rand: real;
678 
    variable int_rand: integer;
679 
    variable stim: std_logic_vector(7 downto 0);
680 
  begin
681 
    for i in payload'range loop
682 
      uniform(seed1, seed2, rand);
683 
      int_rand := integer(trunc(rand*256.0));
684 
      payload(i)(7 downto 0) := std_logic_vector(to_unsigned(int_rand, 8));
685 
      uniform(seed1, seed2, rand);
686 
      int_rand := integer(trunc(rand*256.0));
687 
      payload(i)(15 downto 8) := std_logic_vector(to_unsigned(int_rand, 8));
688 
    end loop;
689 
  end procedure;
690 
 
691 
  procedure CreateRandomPayload(
692 
    variable payload : out DoublewordArray(0 to 31);
693 
    variable seed1 : inout positive;
694 
    variable seed2 : inout positive) is
695 
    variable rand: real;
696 
    variable int_rand: integer;
697 
    variable stim: std_logic_vector(7 downto 0);
698 
  begin
699 
    for i in payload'range loop
700 
      uniform(seed1, seed2, rand);
701 
      int_rand := integer(trunc(rand*256.0));
702 
      payload(i)(7 downto 0) := std_logic_vector(to_unsigned(int_rand, 8));
703 
      uniform(seed1, seed2, rand);
704 
      int_rand := integer(trunc(rand*256.0));
705 
      payload(i)(15 downto 8) := std_logic_vector(to_unsigned(int_rand, 8));
706 
      uniform(seed1, seed2, rand);
707 
      int_rand := integer(trunc(rand*256.0));
708 
      payload(i)(23 downto 16) := std_logic_vector(to_unsigned(int_rand, 8));
709 
      uniform(seed1, seed2, rand);
710 
      int_rand := integer(trunc(rand*256.0));
711 
      payload(i)(31 downto 24) := std_logic_vector(to_unsigned(int_rand, 8));
712 
      uniform(seed1, seed2, rand);
713 
      int_rand := integer(trunc(rand*256.0));
714 
      payload(i)(39 downto 32) := std_logic_vector(to_unsigned(int_rand, 8));
715 
      uniform(seed1, seed2, rand);
716 
      int_rand := integer(trunc(rand*256.0));
717 
      payload(i)(47 downto 40) := std_logic_vector(to_unsigned(int_rand, 8));
718 
      uniform(seed1, seed2, rand);
719 
      int_rand := integer(trunc(rand*256.0));
720 
      payload(i)(55 downto 48) := std_logic_vector(to_unsigned(int_rand, 8));
721 
      uniform(seed1, seed2, rand);
722 
      int_rand := integer(trunc(rand*256.0));
723 
      payload(i)(63 downto 56) := std_logic_vector(to_unsigned(int_rand, 8));
724 
    end loop;
725 
  end procedure;
726 
  ---------------------------------------------------------------------------
727 
  -- Create a generic RapidIO frame.
728 
  ---------------------------------------------------------------------------
729 
  function RioFrameCreate(
730 
    constant ackId : in std_logic_vector(4 downto 0);
731 
    constant vc : in std_logic;
732 
    constant crf : in std_logic;
733 
    constant prio : in std_logic_vector(1 downto 0);
734 
    constant tt : in std_logic_vector(1 downto 0);
735 
    constant ftype : in std_logic_vector(3 downto 0);
736 
    constant sourceId : in std_logic_vector(15 downto 0);
737 
    constant destId : in std_logic_vector(15 downto 0);
738 
    constant payload : in RioPayload) return RioFrame is
739 
    variable frame : RioFrame;
740 
    variable result : HalfwordArray(0 to 137);
741 
    variable crc : std_logic_vector(15 downto 0) := x"ffff";
742 
  begin
743 
    -- Add the header and addresses.
744 
    result(0) := ackId & "0" & vc & crf & prio & tt & ftype;
745 
    result(1) := destId;
746 
    result(2) := sourceId;
747 
 
748 
    -- Update the calculated CRC with the header contents.
749 
    crc := Crc16("00000" & result(0)(10 downto 0), crc);
750 
    crc := Crc16(result(1), crc);
751 
    crc := Crc16(result(2), crc);
752 
 
753 
    -- Check if a single CRC should be added or two.
754 
    if (payload.length <= 37) then
755 
      -- Single CRC.
756 
      for i in 0 to payload.length-1 loop
757 
        result(i+3) := payload.data(i);
758 
        crc := Crc16(payload.data(i), crc);
759 
      end loop;
760 
      result(payload.length+3) := crc;
761 
 
762 
      -- Check if paddning is needed to make the payload even 32-bit.
763 
      if ((payload.length mod 2) = 1) then
764 
        result(payload.length+4) := x"0000";
765 
        frame.length := (payload.length+5) / 2;
766 
      else
767 
        frame.length := (payload.length+4) / 2;
768 
      end if;
769 
    else
770 
      -- Double CRC.
771 
      for i in 0 to 36 loop
772 
        result(i+3) := payload.data(i);
773 
        crc := Crc16(payload.data(i), crc);
774 
      end loop;
775 
 
776 
      -- Add in-the-middle crc.
777 
      result(40) := crc;
778 
      crc := Crc16(crc, crc);
779 
 
780 
      for i in 37 to payload.length-1 loop
781 
        result(i+4) := payload.data(i);
782 
        crc := Crc16(payload.data(i), crc);
783 
      end loop;
784 
      result(payload.length+4) := crc;
785 
 
786 
      -- Check if paddning is needed to make the payload even 32-bit.
787 
      if ((payload.length mod 2) = 0) then
788 
        result(payload.length+5) := x"0000";
789 
        frame.length := (payload.length+6) / 2;
790 
      else
791 
        frame.length := (payload.length+5) / 2;
792 
      end if;
793 
    end if;
794 
 
795 
    -- Update the result length.
796 
    for i in 0 to frame.length-1 loop
797 
      frame.payload(i) := result(2*i) & result(2*i+1);
798 
    end loop;
799 
 
800 
    return frame;
801 
  end function;
802 
 
803 
  -----------------------------------------------------------------------------
804 
  --
805 
  -----------------------------------------------------------------------------
806 
  function RioNwrite(
807 
    constant wrsize : in std_logic_vector(3 downto 0);
808 
    constant address : in std_logic_vector(28 downto 0);
809 
    constant wdptr : in std_logic;
810 
    constant xamsbs : in std_logic_vector(1 downto 0);
811 
    constant dataLength : in natural range 1 to 32;
812 
    constant data : in DoublewordArray(0 to 31))
813 
    return RioPayload is
814 
    variable payload : RioPayload;
815 
  begin
816 
    payload.data(0)(15 downto 12) := "0100";
817 
    payload.data(0)(11 downto 8) := wrsize;
818 45 magro732 
    payload.data(0)(7 downto 0) := (others=>'0');
819 
 
820 
    payload.data(1) := address(28 downto 13);
821 
 
822 
    payload.data(2)(15 downto 3) := address(12 downto 0);
823 
    payload.data(2)(2) := wdptr;
824 
    payload.data(2)(1 downto 0) := xamsbs;
825 
 
826 
    for i in 0 to dataLength-1 loop
827 
      payload.data(3+4*i) := data(i)(63 downto 48);
828 
      payload.data(4+4*i) := data(i)(47 downto 32);
829 
      payload.data(5+4*i) := data(i)(31 downto 16);
830 
      payload.data(6+4*i) := data(i)(15 downto 0);
831 
    end loop;
832 
 
833 
    payload.length := 3 + 4*dataLength;
834 
 
835 
    return payload;
836 
  end function;
837 
 
838 
  -----------------------------------------------------------------------------
839 
  --
840 
  -----------------------------------------------------------------------------
841 
  function RioNwriteR(
842 
    constant wrsize : in std_logic_vector(3 downto 0);
843 
    constant tid : in std_logic_vector(7 downto 0);
844 
    constant address : in std_logic_vector(28 downto 0);
845 
    constant wdptr : in std_logic;
846 
    constant xamsbs : in std_logic_vector(1 downto 0);
847 
    constant dataLength : in natural range 1 to 32;
848 
    constant data : in DoublewordArray(0 to 31))
849 
    return RioPayload is
850 
    variable payload : RioPayload;
851 
  begin
852 
    payload.data(0)(15 downto 12) := "0101";
853 
    payload.data(0)(11 downto 8) := wrsize;
854 2 magro732 
    payload.data(0)(7 downto 0) := tid;
855 
 
856 
    payload.data(1) := address(28 downto 13);
857 
 
858 
    payload.data(2)(15 downto 3) := address(12 downto 0);
859 
    payload.data(2)(2) := wdptr;
860 
    payload.data(2)(1 downto 0) := xamsbs;
861 
 
862 
    for i in 0 to dataLength-1 loop
863 
      payload.data(3+4*i) := data(i)(63 downto 48);
864 
      payload.data(4+4*i) := data(i)(47 downto 32);
865 
      payload.data(5+4*i) := data(i)(31 downto 16);
866 
      payload.data(6+4*i) := data(i)(15 downto 0);
867 
    end loop;
868 
 
869 
    payload.length := 3 + 4*dataLength;
870 
 
871 
    return payload;
872 
  end function;
873 
 
874 
  -----------------------------------------------------------------------------
875 
  --
876 
  -----------------------------------------------------------------------------
877 
  function RioNread(
878 
    constant rdsize : in std_logic_vector(3 downto 0);
879 
    constant tid : in std_logic_vector(7 downto 0);
880 
    constant address : in std_logic_vector(28 downto 0);
881 
    constant wdptr : in std_logic;
882 
    constant xamsbs : in std_logic_vector(1 downto 0))
883 
    return RioPayload is
884 
    variable payload : RioPayload;
885 
  begin
886 
    payload.data(0)(15 downto 12) := "0100";
887 
    payload.data(0)(11 downto 8) := rdsize;
888 
    payload.data(0)(7 downto 0) := tid;
889 
 
890 
    payload.data(1) := address(28 downto 13);
891 
 
892 
    payload.data(2)(15 downto 3) := address(12 downto 0);
893 
    payload.data(2)(2) := wdptr;
894 
    payload.data(2)(1 downto 0) := xamsbs;
895 
 
896 
    payload.length := 3;
897 
 
898 
    return payload;
899 
  end function;
900 
 
901 
  ---------------------------------------------------------------------------
902 
  -- Create a RESPONSE RapidIO frame.
903 
  ---------------------------------------------------------------------------
904 
  function RioResponse(
905 
    constant status : in std_logic_vector(3 downto 0);
906 
    constant tid : in std_logic_vector(7 downto 0);
907 
    constant dataLength : in natural range 0 to 32;
908 
    constant data : in DoublewordArray(0 to 31))
909 
    return RioPayload is
910 
    variable payload : RioPayload;
911 
  begin
912 
    payload.data(0)(11 downto 8) := status;
913 
    payload.data(0)(7 downto 0) := tid;
914 
 
915 
    if (dataLength = 0) then
916 
      payload.data(0)(15 downto 12) := "0000";
917 
      payload.length := 1;
918 
    else
919 
      payload.data(0)(15 downto 12) := "1000";
920 
 
921 
      for i in 0 to dataLength-1 loop
922 
        payload.data(1+4*i) := data(i)(63 downto 48);
923 
        payload.data(2+4*i) := data(i)(47 downto 32);
924 
        payload.data(3+4*i) := data(i)(31 downto 16);
925 
        payload.data(4+4*i) := data(i)(15 downto 0);
926 
      end loop;
927 
 
928 
      payload.length := 1 + 4*dataLength;
929 
    end if;
930 
 
931 
    return payload;
932 
  end function;
933 
 
934 
  ---------------------------------------------------------------------------
935 
  -- Create a Maintenance RapidIO frame.
936 
  ---------------------------------------------------------------------------
937 
  function RioMaintenance(
938 
    constant transaction : in std_logic_vector(3 downto 0);
939 
    constant size : in std_logic_vector(3 downto 0);
940 
    constant tid : in std_logic_vector(7 downto 0);
941 
    constant hopCount : in std_logic_vector(7 downto 0);
942 
    constant configOffset : in std_logic_vector(20 downto 0);
943 
    constant wdptr : in std_logic;
944 
    constant dataLength : in natural range 0 to 8;
945 
    constant data : in DoublewordArray(0 to 7))
946 
    return RioPayload is
947 
    variable payload : RioPayload;
948 
  begin
949 
    payload.data(0)(15 downto 12) := transaction;
950 
    payload.data(0)(11 downto 8) := size;
951 
    payload.data(0)(7 downto 0) := tid;
952 
 
953 
    payload.data(1)(15 downto 8) := hopCount;
954 
    payload.data(1)(7 downto 0) := configOffset(20 downto 13);
955 
 
956 
    payload.data(2)(15 downto 3) := configOffset(12 downto 0);
957 
    payload.data(2)(2) := wdptr;
958 
    payload.data(2)(1 downto 0) := "00";
959 
 
960 
    if (dataLength = 0) then
961 
      payload.length := 3;
962 
    else
963 
      for i in 0 to dataLength-1 loop
964 
        payload.data(3+4*i) := data(i)(63 downto 48);
965 
        payload.data(4+4*i) := data(i)(47 downto 32);
966 
        payload.data(5+4*i) := data(i)(31 downto 16);
967 
        payload.data(6+4*i) := data(i)(15 downto 0);
968 
      end loop;
969 
 
970 
      payload.length := 3 + 4*dataLength;
971 
    end if;
972 
 
973 
    return payload;
974 
  end function;
975 
 
976 
  -----------------------------------------------------------------------------
977 
  -- Function to convert a std_logic_vector to a string.
978 
  -----------------------------------------------------------------------------
979 
  function byteToString(constant byte : std_logic_vector(7 downto 0))
980 
    return string is
981 
    constant table : string(1 to 16) := "0123456789abcdef";
982 
    variable returnValue : string(1 to 2);
983 
  begin
984 
    returnValue(1) := table(to_integer(unsigned(byte(7 downto 4))) + 1);
985 
    returnValue(2) := table(to_integer(unsigned(byte(3 downto 0))) + 1);
986 
    return returnValue;
987 
  end function;
988 
 
989 40 magro732 
  -----------------------------------------------------------------------------
990 
  -- Function to print std_logic_vector.
991 
  -----------------------------------------------------------------------------
992 
  function to_string(constant value : std_logic) return string is
993 
    variable s : string(1 to 1);
994 
  begin
995 
    if (value = '0') then
996 
      s(1) := '0';
997 
    elsif (value = '1') then
998 
      s(1) := '1';
999 
    elsif (value = 'U') then
1000 
      s(1) := 'U';
1001 
    elsif (value = 'X') then
1002 
      s(1) := 'X';
1003 
    else
1004 
      s(1) := '?';
1005 
    end if;
1006 
    return s;
1007 
  end function;
1008 
  function to_string(constant value : std_logic_vector) return string is
1009 
    variable s : string(1 to value'length);
1010 
    variable index : positive;
1011 
    variable i : natural;
1012 
  begin
1013 
    index := 1;
1014 
    for i in value'range loop
1015 
      if (value(i) = '0') then
1016 
        s(index) := '0';
1017 
      elsif (value(i) = '1') then
1018 
        s(index) := '1';
1019 
      elsif (value(i) = 'U') then
1020 
        s(index) := 'U';
1021 
      elsif (value(i) = 'X') then
1022 
        s(index) := 'X';
1023 
      else
1024 
        s(index) := '?';
1025 
      end if;
1026 
      index := index + 1;
1027 
    end loop;
1028 
    return s;
1029 
  end function;
1030 
 
1031 2 magro732 
  ---------------------------------------------------------------------------
1032 
  -- Procedure to print test report
1033 
  ---------------------------------------------------------------------------
1034 
  procedure PrintR( constant str : string ) is
1035 
    file reportFile  : text;
1036 
    variable reportLine, outputLine : line;
1037 
    variable fStatus: FILE_OPEN_STATUS;
1038 
  begin
1039 
    --Write report note to wave/transcript window
1040 
    report str severity NOTE;
1041 
  end PrintR;
1042 
 
1043 
  ---------------------------------------------------------------------------
1044 
  -- Procedure to print test spec
1045 
  ---------------------------------------------------------------------------
1046 
  procedure PrintS( constant str : string ) is
1047 
    file specFile  : text;
1048 
    variable specLine, outputLine : line;
1049 
    variable fStatus: FILE_OPEN_STATUS;
1050 
  begin
1051 
    --Write to spec file
1052 
    file_open(fStatus, specFile, "testspec.txt", append_mode);
1053 
    write(specLine, string'(str));
1054 
    writeline (specFile, specLine);
1055 
    file_close(specFile);
1056 
  end PrintS;
1057 
 
1058 
  ---------------------------------------------------------------------------
1059 
  -- Procedure to Assert Expression
1060 
  ---------------------------------------------------------------------------
1061 
  procedure AssertE( constant exp: boolean; constant str : string ) is
1062 
    file reportFile  : text;
1063 
    variable reportLine, outputLine : line;
1064 
    variable fStatus: FILE_OPEN_STATUS;
1065 
  begin
1066 
    if (not exp) then
1067 
      --Write to STD_OUTPUT
1068 
      report(str) severity error;
1069 
    else
1070 
      PrintR("Status: Passed");
1071 
      PrintS("Status: Passed");
1072 
    end if;
1073 
  end AssertE;
1074 
 
1075 
  ---------------------------------------------------------------------------
1076 
  -- Procedure to Print Error
1077 
  ---------------------------------------------------------------------------
1078 
  procedure PrintE( constant str : string ) is
1079 
    file reportFile  : text;
1080 
    variable reportLine, outputLine : line;
1081 
    variable fStatus: FILE_OPEN_STATUS;
1082 
  begin
1083 
    --Write to STD_OUTPUT
1084 
    report str severity error;
1085 
  end PrintE;
1086 
 
1087 
  ---------------------------------------------------------------------------
1088 40 magro732 
  -- Procedures to handle tests.
1089 2 magro732 
  ---------------------------------------------------------------------------
1090 40 magro732 
 
1091 
  procedure TestWarning(constant tag : in string) is
1092 
    variable writeBuffer : line;
1093 
  begin
1094 
    write(writeBuffer, now);
1095 
    write(writeBuffer, string'(":WARNING:"));
1096 
    write(writeBuffer, tag);
1097 
    writeline(OUTPUT, writeBuffer);
1098 
  end procedure;
1099 
 
1100 
  procedure TestError(constant tag : in string;
1101 
                      constant stopAtError : in boolean := true) is
1102 
    variable writeBuffer : line;
1103 
  begin
1104 
    write(writeBuffer, now);
1105 
    write(writeBuffer, string'(":FAILED:"));
1106 
    write(writeBuffer, tag);
1107 
    writeline(OUTPUT, writeBuffer);
1108 
 
1109 
    if (stopAtError) then
1110 
      std.env.stop(0);
1111 
    end if;
1112 
  end procedure;
1113 
 
1114 
  procedure TestCompare(constant expression : in boolean;
1115 
                        constant tag : in string := "";
1116 
                        constant stopAtError : in boolean := true) is
1117 
    variable writeBuffer : line;
1118 
  begin
1119 
    write(writeBuffer, now);
1120 
    if (not expression) then
1121 
      write(writeBuffer, string'(":FAILED:"));
1122 
    else
1123 
      write(writeBuffer, string'(":PASSED:"));
1124 
    end if;
1125 
    write(writeBuffer, tag);
1126 
    writeline(OUTPUT, writeBuffer);
1127 
 
1128 
    if (stopAtError) and (not expression) then
1129 
      std.env.stop(0);
1130 
    end if;
1131 
  end procedure;
1132 
 
1133 
  procedure TestCompare(constant got : in std_logic;
1134 
                        constant expected : in std_logic;
1135 
                        constant tag : in string := "";
1136 
                        constant stopAtError : in boolean := true) is
1137 
    variable writeBuffer : line;
1138 
  begin
1139 
    write(writeBuffer, now);
1140 
    if (expected /= got) then
1141 
      write(writeBuffer, string'(":FAILED:"));
1142 
      write(writeBuffer, tag);
1143 
      write(writeBuffer, ":got=" & to_string(got));
1144 
      write(writeBuffer, ":expected=" & to_string(expected));
1145 
    else
1146 
      write(writeBuffer, string'(":PASSED:"));
1147 
      write(writeBuffer, tag);
1148 
    end if;
1149 
    writeline(OUTPUT, writeBuffer);
1150 
 
1151 
    if (stopAtError) and (expected /= got) then
1152 
      std.env.stop(0);
1153 
    end if;
1154 
  end procedure;
1155 
 
1156 
  procedure TestCompare(constant got : in std_logic_vector;
1157 
                        constant expected : in std_logic_vector;
1158 
                        constant tag : in string := "";
1159 
                        constant stopAtError : in boolean := true) is
1160 
    variable writeBuffer : line;
1161 
  begin
1162 
    write(writeBuffer, now);
1163 
    if (expected /= got) then
1164 
      write(writeBuffer, string'(":FAILED:"));
1165 
      write(writeBuffer, tag);
1166 
      write(writeBuffer, ":got=" & to_string(got));
1167 
      write(writeBuffer, ":expected=" & to_string(expected));
1168 
    else
1169 
      write(writeBuffer, string'(":PASSED:"));
1170 
      write(writeBuffer, tag);
1171 
    end if;
1172 
    writeline(OUTPUT, writeBuffer);
1173 
 
1174 
    if (stopAtError) and (expected /= got) then
1175 
      std.env.stop(0);
1176 
    end if;
1177 
  end procedure;
1178 
 
1179 
  procedure TestCompare(constant got : in natural;
1180 
                        constant expected : in natural;
1181 
                        constant tag : in string := "";
1182 
                        constant stopAtError : in boolean := true) is
1183 
    variable writeBuffer : line;
1184 
  begin
1185 
    write(writeBuffer, now);
1186 
    if (expected /= got) then
1187 
      write(writeBuffer, string'(":FAILED:"));
1188 
      write(writeBuffer, tag);
1189 
      write(writeBuffer, ":got=" & integer'image(got));
1190 
      write(writeBuffer, ":expected=" & integer'image(expected));
1191 
    else
1192 
      write(writeBuffer, string'(":PASSED:"));
1193 
      write(writeBuffer, tag);
1194 
    end if;
1195 
    writeline(OUTPUT, writeBuffer);
1196 
 
1197 
    if (stopAtError) and (expected /= got) then
1198 
      std.env.stop(0);
1199 
    end if;
1200 
  end procedure;
1201 
 
1202 
  procedure TestCompare(constant got : in time;
1203 
                        constant expected : in time;
1204 
                        constant tag : in string := "";
1205 
                        constant stopAtError : in boolean := true) is
1206 
    variable writeBuffer : line;
1207 
  begin
1208 
    write(writeBuffer, now);
1209 
    if (expected /= got) then
1210 
      write(writeBuffer, string'(":FAILED:"));
1211 
      write(writeBuffer, tag);
1212 
      write(writeBuffer, string'(":got="));
1213 
      write(writeBuffer, got);
1214 
      write(writeBuffer, string'(":expected="));
1215 
      write(writeBuffer, expected);
1216 
    else
1217 
      write(writeBuffer, string'(":PASSED:"));
1218 
      write(writeBuffer, tag);
1219 
    end if;
1220 
    writeline(OUTPUT, writeBuffer);
1221 
 
1222 
    if (stopAtError) and (expected /= got) then
1223 
      std.env.stop(0);
1224 
    end if;
1225 
  end procedure;
1226 
 
1227 
  procedure TestWait(signal waitSignal : in std_logic;
1228 
                     constant waitValue : in std_logic;
1229 
                     constant tag : in string := "";
1230 
                     constant waitTime : in time := 1 ms;
1231 
                     constant stopAtError : in boolean := true) is
1232 
    variable writeBuffer : line;
1233 
  begin
1234 
    if (waitSignal /= waitValue) then
1235 
      wait until waitSignal = waitValue for waitTime;
1236 
      if (waitSignal /= waitValue) then
1237 
        write(writeBuffer, now);
1238 
        write(writeBuffer, string'(":FAILED:"));
1239 
        write(writeBuffer, tag);
1240 
        writeline(OUTPUT, writeBuffer);
1241 
 
1242 
        if (stopAtError) then
1243 
          std.env.stop(0);
1244 
        end if;
1245 
      end if;
1246 
    end if;
1247 
  end procedure;
1248 
 
1249 
  procedure TestWait(signal waitSignal : in std_logic;
1250 
                     constant waitValue : in std_logic;
1251 
                     signal ackSignal : inout std_logic;
1252 
                     constant tag : in string := "";
1253 
                     constant waitTime : in time := 1 ms;
1254 
                     constant stopAtError : in boolean := true) is
1255 
    variable writeBuffer : line;
1256 
  begin
1257 
    if (waitSignal /= waitValue) then
1258 
 
1259 
      wait until waitSignal = waitValue for waitTime;
1260 
 
1261 
      if (waitSignal /= waitValue) then
1262 
        write(writeBuffer, now);
1263 
        write(writeBuffer, string'(":FAILED:"));
1264 
        write(writeBuffer, tag);
1265 
        writeline(OUTPUT, writeBuffer);
1266 
 
1267 
        if (stopAtError) then
1268 
          std.env.stop(0);
1269 
        end if;
1270 
      end if;
1271 
    end if;
1272 
 
1273 
    ackSignal <= not ackSignal;
1274 
 
1275 
    wait until waitSignal /= waitValue for waitTime;
1276 
 
1277 
    if (waitSignal = waitValue) then
1278 
      write(writeBuffer, now);
1279 
      write(writeBuffer, string'(":FAILED:"));
1280 
      write(writeBuffer, tag);
1281 
      writeline(OUTPUT, writeBuffer);
1282 
 
1283 
      if (stopAtError) then
1284 
        std.env.stop(0);
1285 
      end if;
1286 
    end if;
1287 
  end procedure;
1288 
 
1289 2 magro732 
  procedure TestEnd is
1290 40 magro732 
    variable writeBuffer : line;
1291 2 magro732 
  begin
1292 40 magro732 
    write(writeBuffer, now);
1293 
    write(writeBuffer, string'(":COMPLETED"));
1294 
    writeline(OUTPUT, writeBuffer);
1295 
    std.env.stop(0);
1296 2 magro732 
  end TestEnd;
1297 40 magro732 
 
1298 2 magro732 
end rio_common;
1299 
 
1300 
 
1301 
 
1302 
-------------------------------------------------------------------------------
1303 
-- Crc16CITT
1304 
-- A CRC-16 calculator following the implementation proposed in the 2.2
1305 
-- standard.
1306 
-------------------------------------------------------------------------------
1307 
library ieee;
1308 
use ieee.std_logic_1164.all;
1309 
 
1310 
 
1311 
-------------------------------------------------------------------------------
1312 
-- Entity for Crc16CITT.
1313 
-------------------------------------------------------------------------------
1314 
entity Crc16CITT is
1315 
  port(
1316 
    d_i : in  std_logic_vector(15 downto 0);
1317 
    crc_i : in std_logic_vector(15 downto 0);
1318 
    crc_o : out std_logic_vector(15 downto 0));
1319 
end entity;
1320 
 
1321 
 
1322 
-------------------------------------------------------------------------------
1323 
-- Architecture for Crc16CITT.
1324 
-------------------------------------------------------------------------------
1325 
architecture Crc16Impl of Crc16CITT is
1326 
  signal d : std_logic_vector(0 to 15);
1327 
  signal c : std_logic_vector(0 to 15);
1328 
  signal e : std_logic_vector(0 to 15);
1329 
  signal cc : std_logic_vector(0 to 15);
1330 
begin
1331 
 
1332 
  -- Reverse the bit vector indexes to make them the same as in the standard.
1333 
  d(15) <= d_i(0); d(14) <= d_i(1); d(13) <= d_i(2); d(12) <= d_i(3);
1334 
  d(11) <= d_i(4); d(10) <= d_i(5); d(9) <= d_i(6); d(8) <= d_i(7);
1335 
  d(7) <= d_i(8); d(6) <= d_i(9); d(5) <= d_i(10); d(4) <= d_i(11);
1336 
  d(3) <= d_i(12); d(2) <= d_i(13); d(1) <= d_i(14); d(0) <= d_i(15);
1337 
 
1338 
  -- Reverse the bit vector indexes to make them the same as in the standard.
1339 
  c(15) <= crc_i(0); c(14) <= crc_i(1); c(13) <= crc_i(2); c(12) <= crc_i(3);
1340 
  c(11) <= crc_i(4); c(10) <= crc_i(5); c(9) <= crc_i(6); c(8) <= crc_i(7);
1341 
  c(7) <= crc_i(8); c(6) <= crc_i(9); c(5) <= crc_i(10); c(4) <= crc_i(11);
1342 
  c(3) <= crc_i(12); c(2) <= crc_i(13); c(1) <= crc_i(14); c(0) <= crc_i(15);
1343 
 
1344 
  -- Calculate the resulting crc.
1345 
  e <= c xor d;
1346 
  cc(0) <= e(4) xor e(5) xor e(8) xor e(12);
1347 
  cc(1) <= e(5) xor e(6) xor e(9) xor e(13);
1348 
  cc(2) <= e(6) xor e(7) xor e(10) xor e(14);
1349 
  cc(3) <= e(0) xor e(7) xor e(8) xor e(11) xor e(15);
1350 
  cc(4) <= e(0) xor e(1) xor e(4) xor e(5) xor e(9);
1351 
  cc(5) <= e(1) xor e(2) xor e(5) xor e(6) xor e(10);
1352 
  cc(6) <= e(0) xor e(2) xor e(3) xor e(6) xor e(7) xor e(11);
1353 
  cc(7) <= e(0) xor e(1) xor e(3) xor e(4) xor e(7) xor e(8) xor e(12);
1354 
  cc(8) <= e(0) xor e(1) xor e(2) xor e(4) xor e(5) xor e(8) xor e(9) xor e(13);
1355 
  cc(9) <= e(1) xor e(2) xor e(3) xor e(5) xor e(6) xor e(9) xor e(10) xor e(14);
1356 
  cc(10) <= e(2) xor e(3) xor e(4) xor e(6) xor e(7) xor e(10) xor e(11) xor e(15);
1357 
  cc(11) <= e(0) xor e(3) xor e(7) xor e(11);
1358 
  cc(12) <= e(0) xor e(1) xor e(4) xor e(8) xor e(12);
1359 
  cc(13) <= e(1) xor e(2) xor e(5) xor e(9) xor e(13);
1360 
  cc(14) <= e(2) xor e(3) xor e(6) xor e(10) xor e(14);
1361 
  cc(15) <= e(3) xor e(4) xor e(7) xor e(11) xor e(15);
1362 
 
1363 
  -- Reverse the bit vector indexes to make them the same as in the standard.
1364 
  crc_o(15) <= cc(0); crc_o(14) <= cc(1); crc_o(13) <= cc(2); crc_o(12) <= cc(3);
1365 
  crc_o(11) <= cc(4); crc_o(10) <= cc(5); crc_o(9) <= cc(6); crc_o(8) <= cc(7);
1366 
  crc_o(7) <= cc(8); crc_o(6) <= cc(9); crc_o(5) <= cc(10); crc_o(4) <= cc(11);
1367 
  crc_o(3) <= cc(12); crc_o(2) <= cc(13); crc_o(1) <= cc(14); crc_o(0) <= cc(15);
1368 
 
1369 
end architecture;
1370 
 
1371 
 
1372 
 
1373 
-------------------------------------------------------------------------------
1374 
-- MemoryDualPort
1375 
-- Generic synchronous memory with one read/write port and one read port.
1376 
-------------------------------------------------------------------------------
1377 
 
1378 
library ieee;
1379 
use ieee.std_logic_1164.all;
1380 
use ieee.numeric_std.all;
1381 
 
1382 
 
1383 
-------------------------------------------------------------------------------
1384 
-- Entity for MemoryDualPort.
1385 
-------------------------------------------------------------------------------
1386 
entity MemoryDualPort is
1387 
  generic(
1388 
    ADDRESS_WIDTH : natural := 1;
1389 
    DATA_WIDTH : natural := 1);
1390 
  port(
1391 
    clkA_i : in std_logic;
1392 
    enableA_i : in std_logic;
1393 
    writeEnableA_i : in std_logic;
1394 
    addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
1395 
    dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
1396 
    dataA_o : out std_logic_vector(DATA_WIDTH-1 downto 0);
1397 
 
1398 
    clkB_i : in std_logic;
1399 
    enableB_i : in std_logic;
1400 
    addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
1401 
    dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
1402 
end entity;
1403 
 
1404 
 
1405 
-------------------------------------------------------------------------------
1406 
-- Architecture for MemoryDualPort.
1407 
-------------------------------------------------------------------------------
1408 
architecture MemoryDualPortImpl of MemoryDualPort is
1409 
  type MemoryType is array (natural range <>) of
1410 
    std_logic_vector(DATA_WIDTH-1 downto 0);
1411 
 
1412 
  signal memory : MemoryType(0 to (2**ADDRESS_WIDTH)-1);
1413 
 
1414 
begin
1415 
  process(clkA_i)
1416 
  begin
1417 
    if (clkA_i'event and clkA_i = '1') then
1418 
      if (enableA_i = '1') then
1419 
        if (writeEnableA_i = '1') then
1420 
          memory(to_integer(unsigned(addressA_i))) <= dataA_i;
1421 
        end if;
1422 
 
1423 
        dataA_o <= memory(to_integer(unsigned(addressA_i)));
1424 
      end if;
1425 
    end if;
1426 
  end process;
1427 
 
1428 
  process(clkB_i)
1429 
  begin
1430 
    if (clkB_i'event and clkB_i = '1') then
1431 
      if (enableB_i = '1') then
1432 
        dataB_o <= memory(to_integer(unsigned(addressB_i)));
1433 
      end if;
1434 
    end if;
1435 
  end process;
1436 
 
1437 
end architecture;
1438 
 
1439 
 
1440 
 
1441 
-------------------------------------------------------------------------------
1442 
-- MemorySimpleDualPort
1443 
-- Generic synchronous memory with one write port and one read port.
1444 
-------------------------------------------------------------------------------
1445 
 
1446 
library ieee;
1447 
use ieee.std_logic_1164.all;
1448 
use ieee.numeric_std.all;
1449 
 
1450 
 
1451 
-------------------------------------------------------------------------------
1452 
-- Entity for MemorySimpleDualPort.
1453 
-------------------------------------------------------------------------------
1454 
entity MemorySimpleDualPort is
1455 
  generic(
1456 
    ADDRESS_WIDTH : natural := 1;
1457 
    DATA_WIDTH : natural := 1);
1458 
  port(
1459 
    clkA_i : in std_logic;
1460 
    enableA_i : in std_logic;
1461 
    addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
1462 
    dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
1463 
 
1464 
    clkB_i : in std_logic;
1465 
    enableB_i : in std_logic;
1466 
    addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
1467 
    dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
1468 
end entity;
1469 
 
1470 
 
1471 
-------------------------------------------------------------------------------
1472 
-- Architecture for MemorySimpleDualPort.
1473 
-------------------------------------------------------------------------------
1474 
architecture MemorySimpleDualPortImpl of MemorySimpleDualPort is
1475 
  type MemoryType is array (natural range <>) of
1476 
    std_logic_vector(DATA_WIDTH-1 downto 0);
1477 
 
1478 
  signal memory : MemoryType(0 to (2**ADDRESS_WIDTH)-1);
1479 
 
1480 
begin
1481 
  process(clkA_i)
1482 
  begin
1483 
    if (clkA_i'event and clkA_i = '1') then
1484 
      if (enableA_i = '1') then
1485 
        memory(to_integer(unsigned(addressA_i))) <= dataA_i;
1486 
      end if;
1487 
    end if;
1488 
  end process;
1489 
 
1490 
  process(clkB_i)
1491 
  begin
1492 
    if (clkB_i'event and clkB_i = '1') then
1493 
      if (enableB_i = '1') then
1494 
        dataB_o <= memory(to_integer(unsigned(addressB_i)));
1495 
      end if;
1496 
    end if;
1497 
  end process;
1498 
 
1499 
end architecture;
1500 
 
1501 
 
1502 
 
1503 
-------------------------------------------------------------------------------
1504 
-- MemorySinglePort
1505 
-- Generic synchronous memory with one read/write port.
1506 
-------------------------------------------------------------------------------
1507 
 
1508 
library ieee;
1509 
use ieee.std_logic_1164.all;
1510 
use ieee.numeric_std.all;
1511 
 
1512 
 
1513 
-------------------------------------------------------------------------------
1514 
-- Entity for MemorySinglePort.
1515 
-------------------------------------------------------------------------------
1516 
entity MemorySinglePort is
1517 
  generic(
1518 
    ADDRESS_WIDTH : natural := 1;
1519 
    DATA_WIDTH : natural := 1);
1520 
  port(
1521 
    clk_i : in std_logic;
1522 
    enable_i : in std_logic;
1523 
    writeEnable_i : in std_logic;
1524 
    address_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
1525 
    data_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
1526 
    data_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
1527 
end entity;
1528 
 
1529 
 
1530 
-------------------------------------------------------------------------------
1531 
-- Architecture for MemorySinglePort.
1532 
-------------------------------------------------------------------------------
1533 
architecture MemorySinglePortImpl of MemorySinglePort is
1534 
  type MemoryType is array (natural range <>) of
1535 
    std_logic_vector(DATA_WIDTH-1 downto 0);
1536 
 
1537 
  signal memory : MemoryType(0 to (2**ADDRESS_WIDTH)-1);
1538 
 
1539 
begin
1540 
  process(clk_i)
1541 
  begin
1542 
    if (clk_i'event and clk_i = '1') then
1543 
      if (enable_i = '1') then
1544 
        if (writeEnable_i = '1') then
1545 
          memory(to_integer(unsigned(address_i))) <= data_i;
1546 
        end if;
1547 
 
1548 
        data_o <= memory(to_integer(unsigned(address_i)));
1549 
      end if;
1550 
    end if;
1551 
  end process;
1552 
 
1553 
end architecture;
1554 
 
1555 
 
1556 
 
1557 
 
1558 
-------------------------------------------------------------------------------
1559 
-- MemorySimpleDualPortAsync
1560 
-- Generic memory with one synchronous write port and one asynchronous read port.
1561 
-------------------------------------------------------------------------------
1562 
 
1563 
library ieee;
1564 
use ieee.std_logic_1164.all;
1565 
use ieee.numeric_std.all;
1566 
 
1567 
 
1568 
-------------------------------------------------------------------------------
1569 
-- Entity for MemorySimpleDualPortAsync.
1570 
-------------------------------------------------------------------------------
1571 
entity MemorySimpleDualPortAsync is
1572 
  generic(
1573 
    ADDRESS_WIDTH : natural := 1;
1574 
    DATA_WIDTH : natural := 1;
1575 
    INIT_VALUE : std_logic := 'U');
1576 
  port(
1577 
    clkA_i : in std_logic;
1578 
    enableA_i : in std_logic;
1579 
    addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
1580 
    dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
1581 
 
1582 
    addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
1583 
    dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
1584 
end entity;
1585 
 
1586 
 
1587 
-------------------------------------------------------------------------------
1588 
-- Architecture for MemorySimpleDualPortAsync.
1589 
-------------------------------------------------------------------------------
1590 
architecture MemorySimpleDualPortAsyncImpl of MemorySimpleDualPortAsync is
1591 
  type MemoryType is array (natural range <>) of
1592 
    std_logic_vector(DATA_WIDTH-1 downto 0);
1593 
 
1594 
  signal memory : MemoryType(0 to (2**ADDRESS_WIDTH)-1) := (others=>(others=>INIT_VALUE));
1595 
 
1596 
begin
1597 
  process(clkA_i)
1598 
  begin
1599 
    if (clkA_i'event and clkA_i = '1') then
1600 
      if (enableA_i = '1') then
1601 
        memory(to_integer(unsigned(addressA_i))) <= dataA_i;
1602 
      end if;
1603 
    end if;
1604 
  end process;
1605 
 
1606 
  dataB_o <= memory(to_integer(unsigned(addressB_i)));
1607 
 
1608 
end architecture;
1609 
 
1610 
 
1611 
 
1612 
 
1613 
 

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