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1 2 magro732 
-------------------------------------------------------------------------------
2 
--
3 
-- RapidIO IP Library Core
4 
--
5 
-- This file is part of the RapidIO IP library project
6 
-- http://www.opencores.org/cores/rio/
7 
--
8 
-- Description
9 
-- Contains commonly used types, functions, procedures and entities used in
10 
-- the RapidIO IP library project.
11 
--
12 
-- To Do:
13 
-- -
14 
--
15 
-- Author(s):
16 
-- - Magnus Rosenius, magro732@opencores.org
17 
--
18 
-------------------------------------------------------------------------------
19 
--
20 
-- Copyright (C) 2013 Authors and OPENCORES.ORG
21 
--
22 
-- This source file may be used and distributed without
23 
-- restriction provided that this copyright statement is not
24 
-- removed from the file and that any derivative work contains
25 
-- the original copyright notice and the associated disclaimer.
26 
--
27 
-- This source file is free software; you can redistribute it
28 
-- and/or modify it under the terms of the GNU Lesser General
29 
-- Public License as published by the Free Software Foundation;
30 
-- either version 2.1 of the License, or (at your option) any
31 
-- later version.
32 
--
33 
-- This source is distributed in the hope that it will be
34 
-- useful, but WITHOUT ANY WARRANTY; without even the implied
35 
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
36 
-- PURPOSE. See the GNU Lesser General Public License for more
37 
-- details.
38 
--
39 
-- You should have received a copy of the GNU Lesser General
40 
-- Public License along with this source; if not, download it
41 
-- from http://www.opencores.org/lgpl.shtml
42 
--
43 
-------------------------------------------------------------------------------
44 
 
45 
 
46 
-------------------------------------------------------------------------------
47 
-- RioCommon library.
48 
-------------------------------------------------------------------------------
49 
library ieee;
50 
use ieee.std_logic_1164.all;
51 
use ieee.numeric_std.all;
52 
use ieee.math_real.all;
53 
use std.textio.all;
54 
 
55 
 
56 
-------------------------------------------------------------------------------
57 
-- RioCommon package description.
58 
-------------------------------------------------------------------------------
59 
package rio_common is
60 46 magro732 
 
61 2 magro732 
  -----------------------------------------------------------------------------
62 46 magro732 
  -- Primitive memory component declarations.
63 
  -----------------------------------------------------------------------------
64 
 
65 
  component MemorySimpleDualPort
66 
    generic(
67 
      ADDRESS_WIDTH : natural := 1;
68 
      DATA_WIDTH : natural := 1);
69 
    port(
70 
      clkA_i : in std_logic;
71 
      enableA_i : in std_logic;
72 
      addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
73 
      dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
74 
 
75 
      clkB_i : in std_logic;
76 
      enableB_i : in std_logic;
77 
      addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
78 
      dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
79 
  end component;
80 
 
81 
  component MemoryDualPort is
82 
    generic(
83 
      ADDRESS_WIDTH : natural := 1;
84 
      DATA_WIDTH : natural := 1);
85 
    port(
86 
      clkA_i : in std_logic;
87 
      enableA_i : in std_logic;
88 
      writeEnableA_i : in std_logic;
89 
      addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
90 
      dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
91 
      dataA_o : out std_logic_vector(DATA_WIDTH-1 downto 0);
92 
 
93 
      clkB_i : in std_logic;
94 
      enableB_i : in std_logic;
95 
      addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
96 
      dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
97 
  end component;
98 
 
99 48 magro732 
  component Crc16CITT is
100 
    port(
101 
      d_i : in  std_logic_vector(15 downto 0);
102 
      crc_i : in  std_logic_vector(15 downto 0);
103 
      crc_o : out std_logic_vector(15 downto 0));
104 
  end component;
105 
 
106 46 magro732 
  -----------------------------------------------------------------------------
107 
  -- Logical layer component declarations.
108 
  -----------------------------------------------------------------------------
109 
 
110 
  component RioLogicalCommon is
111 
    generic(
112 
      PORTS : natural);
113 
    port(
114 
      clk : in std_logic;
115 
      areset_n : in std_logic;
116 
      enable : in std_logic;
117 
 
118 
      readFrameEmpty_i : in std_logic;
119 
      readFrame_o : out std_logic;
120 
      readContent_o : out std_logic;
121 
      readContentEnd_i : in std_logic;
122 
      readContentData_i : in std_logic_vector(31 downto 0);
123 
 
124 
      writeFrameFull_i : in std_logic;
125 
      writeFrame_o : out std_logic;
126 
      writeFrameAbort_o : out std_logic;
127 
      writeContent_o : out std_logic;
128 
      writeContentData_o : out std_logic_vector(31 downto 0);
129 
 
130 
      inboundStb_o : out std_logic;
131 48 magro732 
      inboundAdr_o : out std_logic_vector(3 downto 0);
132 46 magro732 
      inboundDat_o : out std_logic_vector(31 downto 0);
133 48 magro732 
      inboundStall_i : in std_logic;
134 46 magro732 
 
135 
      outboundStb_i : in std_logic_vector(PORTS-1 downto 0);
136 48 magro732 
      outboundAdr_i : in std_logic_vector(PORTS-1 downto 0);
137 46 magro732 
      outboundDat_i : in std_logic_vector(32*PORTS-1 downto 0);
138 48 magro732 
      outboundStall_o : out std_logic_vector(PORTS-1 downto 0));
139 46 magro732 
  end component;
140 
 
141 
  component RioLogicalMaintenance is
142 
    port(
143 
      clk : in std_logic;
144 
      areset_n : in std_logic;
145 
      enable : in std_logic;
146 
 
147 
      readRequestReady_i : in std_logic;
148 
      writeRequestReady_i : in std_logic;
149 47 magro732 
      size_i : in std_logic_vector(3 downto 0);
150 46 magro732 
      offset_i : in std_logic_vector(20 downto 0);
151 
      wdptr_i : in std_logic;
152 47 magro732 
      payloadLength_i : in std_logic_vector(2 downto 0);
153 
      payloadIndex_o : out std_logic_vector(2 downto 0);
154 
      payload_i : in std_logic_vector(63 downto 0);
155 46 magro732 
      done_o : out std_logic;
156 
 
157 
      readResponseReady_o : out std_logic;
158 
      writeResponseReady_o : out std_logic;
159 47 magro732 
      status_o : out std_logic_vector(3 downto 0);
160 
      payloadLength_o : out std_logic_vector(2 downto 0);
161 
      payloadIndex_i : in std_logic_vector(2 downto 0);
162 
      payload_o : out std_logic_vector(63 downto 0);
163 46 magro732 
      done_i : in std_logic;
164 
 
165 
      configStb_o : out std_logic;
166 
      configWe_o : out std_logic;
167 
      configAdr_o : out std_logic_vector(21 downto 0);
168 
      configDat_o : out std_logic_vector(31 downto 0);
169 
      configDat_i : in std_logic_vector(31 downto 0);
170 
      configAck_i : in std_logic);
171 
  end component;
172 
 
173 
  component MaintenanceInbound is
174 48 magro732 
    generic(
175 
      ENABLE_READ_REQUEST : boolean := true;
176 
      ENABLE_WRITE_REQUEST : boolean := true;
177 
      ENABLE_READ_RESPONSE : boolean := true;
178 
      ENABLE_WRITE_RESPONSE : boolean := true;
179 
      ENABLE_PORT_WRITE : boolean := true);
180 46 magro732 
    port(
181 
      clk : in std_logic;
182 
      areset_n : in std_logic;
183 
      enable : in std_logic;
184 
 
185 
      readRequestReady_o : out std_logic;
186 
      writeRequestReady_o : out std_logic;
187 
      readResponseReady_o : out std_logic;
188 
      writeResponseReady_o : out std_logic;
189 
      portWriteReady_o : out std_logic;
190 48 magro732 
 
191 46 magro732 
      vc_o : out std_logic;
192 
      crf_o : out std_logic;
193 
      prio_o : out std_logic_vector(1 downto 0);
194 
      tt_o : out std_logic_vector(1 downto 0);
195 
      dstid_o : out std_logic_vector(31 downto 0);
196 
      srcid_o : out std_logic_vector(31 downto 0);
197 47 magro732 
      size_o : out std_logic_vector(3 downto 0);
198 
      status_o : out std_logic_vector(3 downto 0);
199 46 magro732 
      tid_o : out std_logic_vector(7 downto 0);
200 
      hop_o : out std_logic_vector(7 downto 0);
201 
      offset_o : out std_logic_vector(20 downto 0);
202 
      wdptr_o : out std_logic;
203 47 magro732 
      payloadLength_o : out std_logic_vector(2 downto 0);
204 
      payloadIndex_i : in std_logic_vector(2 downto 0);
205 
      payload_o : out std_logic_vector(63 downto 0);
206 46 magro732 
      done_i : in std_logic;
207 
 
208 
      inboundStb_i : in std_logic;
209 48 magro732 
      inboundAdr_i : in std_logic_vector(3 downto 0);
210 46 magro732 
      inboundDat_i : in std_logic_vector(31 downto 0);
211 48 magro732 
      inboundStall_o : out std_logic);
212 46 magro732 
  end component;
213 
 
214 48 magro732 
  component RequestClassInbound is
215 
    generic(
216 
      EXTENDED_ADDRESS : natural range 0 to 2 := 0);
217 
    port(
218 
      clk : in std_logic;
219 
      areset_n : in std_logic;
220 
      enable : in std_logic;
221 
 
222 
      nreadReady_o : out std_logic;
223 
 
224 
      vc_o : out std_logic;
225 
      crf_o : out std_logic;
226 
      prio_o : out std_logic_vector(1 downto 0);
227 
      tt_o : out std_logic_vector(1 downto 0);
228 
      dstId_o : out std_logic_vector(31 downto 0);
229 
      srcId_o : out std_logic_vector(31 downto 0);
230 
      tid_o : out std_logic_vector(7 downto 0);
231 
      address_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
232 
      length_o : out std_logic_vector(4 downto 0);
233 
      select_o : out std_logic_vector(7 downto 0);
234 
      done_i : in std_logic;
235 
 
236 
      inboundStb_i : in std_logic;
237 
      inboundAdr_i : in std_logic_vector(3 downto 0);
238 
      inboundDat_i : in std_logic_vector(31 downto 0);
239 
      inboundStall_o : out std_logic);
240 
  end component;
241 
 
242 
  component WriteClassInbound is
243 
    generic(
244 
      ENABLE_NWRITE : boolean := true;
245 
      ENABLE_NWRITER : boolean := true;
246 
      EXTENDED_ADDRESS : natural range 0 to 2 := 0);
247 
    port(
248 
      clk : in std_logic;
249 
      areset_n : in std_logic;
250 
      enable : in std_logic;
251 
 
252 
      nwriteReady_o : out std_logic;
253 
      nwriterReady_o : out std_logic;
254 
 
255 
      vc_o : out std_logic;
256 
      crf_o : out std_logic;
257 
      prio_o : out std_logic_vector(1 downto 0);
258 
      tt_o : out std_logic_vector(1 downto 0);
259 
      dstId_o : out std_logic_vector(31 downto 0);
260 
      srcId_o : out std_logic_vector(31 downto 0);
261 
      tid_o : out std_logic_vector(7 downto 0);
262 
      address_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
263 
      length_o : out std_logic_vector(4 downto 0);
264 
      select_o : out std_logic_vector(7 downto 0);
265 
      payloadIndex_i : in std_logic_vector(4 downto 0);
266 
      payload_o : out std_logic_vector(63 downto 0);
267 
      done_i : in std_logic;
268 
 
269 
      inboundStb_i : in std_logic;
270 
      inboundAdr_i : in std_logic_vector(3 downto 0);
271 
      inboundDat_i : in std_logic_vector(31 downto 0);
272 
      inboundStall_o : out std_logic);
273 
  end component;
274 
 
275 46 magro732 
  component MaintenanceOutbound is
276 
    port(
277 
      clk : in std_logic;
278 
      areset_n : in std_logic;
279 
      enable : in std_logic;
280 
 
281 
      readRequestReady_i : in std_logic;
282 
      writeRequestReady_i : in std_logic;
283 
      readResponseReady_i : in std_logic;
284 
      writeResponseReady_i : in std_logic;
285 
      portWriteReady_i : in std_logic;
286 48 magro732 
 
287 46 magro732 
      vc_i : in std_logic;
288 
      crf_i : in std_logic;
289 
      prio_i : in std_logic_vector(1 downto 0);
290 
      tt_i : in std_logic_vector(1 downto 0);
291 
      dstid_i : in std_logic_vector(31 downto 0);
292 
      srcid_i : in std_logic_vector(31 downto 0);
293 47 magro732 
      size_i : in std_logic_vector(3 downto 0);
294 46 magro732 
      status_i : in std_logic_vector(3 downto 0);
295 
      tid_i : in std_logic_vector(7 downto 0);
296 
      hop_i : in std_logic_vector(7 downto 0);
297 
      offset_i : in std_logic_vector(20 downto 0);
298 
      wdptr_i : in std_logic;
299 47 magro732 
      payloadLength_i : in std_logic_vector(2 downto 0);
300 
      payloadIndex_o : out std_logic_vector(2 downto 0);
301 
      payload_i : in std_logic_vector(63 downto 0);
302 46 magro732 
      done_o : out std_logic;
303 
 
304 
      outboundStb_o : out std_logic;
305 48 magro732 
      outboundAdr_o : out std_logic;
306 46 magro732 
      outboundDat_o : out std_logic_vector(31 downto 0);
307 48 magro732 
      outboundStall_i : in std_logic);
308 46 magro732 
  end component;
309 
 
310 48 magro732 
  component ResponseClassOutbound is
311 
    port(
312 
      clk : in std_logic;
313 
      areset_n : in std_logic;
314 
      enable : in std_logic;
315 
 
316 
      doneNoPayloadReady_i : in std_logic;
317 
      doneWithPayloadReady_i :  in std_logic;
318 
      errorReady_i : in std_logic;
319 
 
320 
      vc_i : in std_logic;
321 
      crf_i : in std_logic;
322 
      prio_i : in std_logic_vector(1 downto 0);
323 
      tt_i : in std_logic_vector(1 downto 0);
324 
      dstid_i : in std_logic_vector(31 downto 0);
325 
      srcid_i : in std_logic_vector(31 downto 0);
326 
      tid_i : in std_logic_vector(7 downto 0);
327 
      payloadLength_i : in std_logic_vector(4 downto 0);
328 
      payloadIndex_o : out std_logic_vector(4 downto 0);
329 
      payload_i : in std_logic_vector(63 downto 0);
330 
      done_o : out std_logic;
331 
 
332 
      outboundStb_o : out std_logic;
333 
      outboundAdr_o : out std_logic;
334 
      outboundDat_o : out std_logic_vector(31 downto 0);
335 
      outboundStall_i : in std_logic);
336 
  end component;
337 
 
338 46 magro732 
  component RioPacketBuffer is
339 
    generic(
340 
      SIZE_ADDRESS_WIDTH : natural := 6;
341 
      CONTENT_ADDRESS_WIDTH : natural := 8);
342 
    port(
343 
      clk : in std_logic;
344 
      areset_n : in std_logic;
345 
 
346 
      inboundWriteFrameFull_o : out std_logic;
347 
      inboundWriteFrame_i : in std_logic;
348 
      inboundWriteFrameAbort_i : in std_logic;
349 
      inboundWriteContent_i : in std_logic;
350 
      inboundWriteContentData_i : in std_logic_vector(31 downto 0);
351 
      inboundReadFrameEmpty_o : out std_logic;
352 
      inboundReadFrame_i : in std_logic;
353 
      inboundReadFrameRestart_i : in std_logic;
354 
      inboundReadFrameAborted_o : out std_logic;
355 
      inboundReadContentEmpty_o : out std_logic;
356 
      inboundReadContent_i : in std_logic;
357 
      inboundReadContentEnd_o : out std_logic;
358 
      inboundReadContentData_o : out std_logic_vector(31 downto 0);
359 
 
360 
      outboundWriteFrameFull_o : out std_logic;
361 
      outboundWriteFrame_i : in std_logic;
362 
      outboundWriteFrameAbort_i : in std_logic;
363 
      outboundWriteContent_i : in std_logic;
364 
      outboundWriteContentData_i : in std_logic_vector(31 downto 0);
365 
      outboundReadFrameEmpty_o : out std_logic;
366 
      outboundReadFrame_i : in std_logic;
367 
      outboundReadFrameRestart_i : in std_logic;
368 
      outboundReadFrameAborted_o : out std_logic;
369 
      outboundReadContentEmpty_o : out std_logic;
370 
      outboundReadContent_i : in std_logic;
371 
      outboundReadContentEnd_o : out std_logic;
372 
      outboundReadContentData_o : out std_logic_vector(31 downto 0));
373 
  end component;
374 
 
375 
  -----------------------------------------------------------------------------
376 2 magro732 
  -- Commonly used types.
377 
  -----------------------------------------------------------------------------
378 
  type Array1 is array (natural range <>) of
379 
    std_logic;
380 
  type Array2 is array (natural range <>) of
381 
    std_logic_vector(1 downto 0);
382 
  type Array3 is array (natural range <>) of
383 
    std_logic_vector(2 downto 0);
384 
  type Array4 is array (natural range <>) of
385 
    std_logic_vector(3 downto 0);
386 
  type Array5 is array (natural range <>) of
387 
    std_logic_vector(4 downto 0);
388 
  type Array8 is array (natural range <>) of
389 
    std_logic_vector(7 downto 0);
390 
  type Array9 is array (natural range <>) of
391 
    std_logic_vector(8 downto 0);
392 
  type Array10 is array (natural range <>) of
393 
    std_logic_vector(9 downto 0);
394 
  type Array16 is array (natural range <>) of
395 
    std_logic_vector(15 downto 0);
396 
  type Array32 is array (natural range <>) of
397 
    std_logic_vector(31 downto 0);
398 
  type Array34 is array (natural range <>) of
399 
    std_logic_vector(33 downto 0);
400 
 
401 
  -----------------------------------------------------------------------------
402 
  -- Commonly used constants.
403 
  -----------------------------------------------------------------------------
404 
 
405 
  -- STYPE0 constants.
406 
  constant STYPE0_PACKET_ACCEPTED : std_logic_vector(2 downto 0) := "000";
407 
  constant STYPE0_PACKET_RETRY : std_logic_vector(2 downto 0) := "001";
408 
  constant STYPE0_PACKET_NOT_ACCEPTED : std_logic_vector(2 downto 0) := "010";
409 
  constant STYPE0_RESERVED : std_logic_vector(2 downto 0) := "011";
410 
  constant STYPE0_STATUS : std_logic_vector(2 downto 0) := "100";
411 
  constant STYPE0_VC_STATUS : std_logic_vector(2 downto 0) := "101";
412 
  constant STYPE0_LINK_RESPONSE : std_logic_vector(2 downto 0) := "110";
413 
  constant STYPE0_IMPLEMENTATION_DEFINED : std_logic_vector(2 downto 0) := "111";
414 
 
415 
  -- STYPE1 constants.
416 
  constant STYPE1_START_OF_PACKET : std_logic_vector(2 downto 0) := "000";
417 
  constant STYPE1_STOMP : std_logic_vector(2 downto 0) := "001";
418 
  constant STYPE1_END_OF_PACKET : std_logic_vector(2 downto 0) := "010";
419 
  constant STYPE1_RESTART_FROM_RETRY : std_logic_vector(2 downto 0) := "011";
420 
  constant STYPE1_LINK_REQUEST : std_logic_vector(2 downto 0) := "100";
421 
  constant STYPE1_MULTICAST_EVENT : std_logic_vector(2 downto 0) := "101";
422 
  constant STYPE1_RESERVED : std_logic_vector(2 downto 0) := "110";
423 
  constant STYPE1_NOP : std_logic_vector(2 downto 0) := "111";
424 
 
425 
  -- FTYPE constants.
426 
  constant FTYPE_REQUEST_CLASS : std_logic_vector(3 downto 0) := "0010";
427 
  constant FTYPE_WRITE_CLASS : std_logic_vector(3 downto 0) := "0101";
428 
  constant FTYPE_STREAMING_WRITE_CLASS : std_logic_vector(3 downto 0) := "0110";
429 
  constant FTYPE_MAINTENANCE_CLASS : std_logic_vector(3 downto 0) := "1000";
430 
  constant FTYPE_RESPONSE_CLASS : std_logic_vector(3 downto 0) := "1101";
431 
  constant FTYPE_DOORBELL_CLASS : std_logic_vector(3 downto 0) := "1010";
432 
  constant FTYPE_MESSAGE_CLASS : std_logic_vector(3 downto 0) := "0010";
433 
 
434 
  -- TTYPE Constants
435 
  constant TTYPE_MAINTENANCE_READ_REQUEST : std_logic_vector(3 downto 0) := "0000";
436 
  constant TTYPE_MAINTENANCE_WRITE_REQUEST : std_logic_vector(3 downto 0) := "0001";
437 
  constant TTYPE_MAINTENANCE_READ_RESPONSE : std_logic_vector(3 downto 0) := "0010";
438 
  constant TTYPE_MAINTENANCE_WRITE_RESPONSE : std_logic_vector(3 downto 0) := "0011";
439 48 magro732 
  constant TTYPE_MAINTENANCE_PORT_WRITE : std_logic_vector(3 downto 0) := "0100";
440 2 magro732 
  constant TTYPE_NREAD_TRANSACTION : std_logic_vector(3 downto 0) := "0100";
441 
  constant TTYPE_NWRITE_TRANSACTION : std_logic_vector(3 downto 0) := "0100";
442 48 magro732 
  constant TTYPE_NWRITER_TRANSACTION : std_logic_vector(3 downto 0) := "0101";
443 
  constant TTYPE_RESPONSE_NO_PAYLOAD : std_logic_vector(3 downto 0) := "0000";
444 
  constant TTYPE_RESPONSE_WITH_PAYLOAD : std_logic_vector(3 downto 0) := "1000";
445 2 magro732 
 
446 
  constant LINK_REQUEST_CMD_RESET_DEVICE : std_logic_vector(2 downto 0) := "011";
447 
  constant LINK_REQUEST_CMD_INPUT_STATUS : std_logic_vector(2 downto 0) := "100";
448 
 
449 
  constant PACKET_NOT_ACCEPTED_CAUSE_UNEXPECTED_ACKID : std_logic_vector(4 downto 0) := "00001";
450 
  constant PACKET_NOT_ACCEPTED_CAUSE_CONTROL_CRC : std_logic_vector(4 downto 0) := "00010";
451 
  constant PACKET_NOT_ACCEPTED_CAUSE_NON_MAINTENANCE_STOPPED : std_logic_vector(4 downto 0) := "00011";
452 
  constant PACKET_NOT_ACCEPTED_CAUSE_PACKET_CRC : std_logic_vector(4 downto 0) := "00100";
453 
  constant PACKET_NOT_ACCEPTED_CAUSE_INVALID_CHARACTER : std_logic_vector(4 downto 0) := "00101";
454 
  constant PACKET_NOT_ACCEPTED_CAUSE_NO_RESOURCES : std_logic_vector(4 downto 0) := "00110";
455 
  constant PACKET_NOT_ACCEPTED_CAUSE_LOSS_DESCRAMBLER : std_logic_vector(4 downto 0) := "00111";
456 
  constant PACKET_NOT_ACCEPTED_CAUSE_GENERAL_ERROR : std_logic_vector(4 downto 0) := "11111";
457 
 
458 
  -----------------------------------------------------------------------------
459 
  -- Types used in simulations.
460 
  -----------------------------------------------------------------------------
461 
  type ByteArray is array (natural range <>) of
462 
    std_logic_vector(7 downto 0);
463 
  type HalfwordArray is array (natural range <>) of
464 
    std_logic_vector(15 downto 0);
465 
  type WordArray is array (natural range <>) of
466 
    std_logic_vector(31 downto 0);
467 
  type DoublewordArray is array (natural range <>) of
468 
    std_logic_vector(63 downto 0);
469 
 
470 
  -- Type defining a RapidIO frame.
471 
  type RioFrame is record
472 
    length : natural range 0 to 69;
473 
    payload : WordArray(0 to 68);
474 
  end record;
475 
  type RioFrameArray is array (natural range <>) of RioFrame;
476 
 
477 
  -- Type defining a RapidIO payload.
478 
  type RioPayload is record
479 
    length : natural range 0 to 133;
480 
    data : HalfwordArray(0 to 132);
481 
  end record;
482 
 
483 
  -----------------------------------------------------------------------------
484 
  -- Crc5 calculation function.
485 
  -- ITU, polynom=0x15.
486 
  -----------------------------------------------------------------------------
487 
  function Crc5(constant data : in std_logic_vector(18 downto 0);
488 
                constant crc : in std_logic_vector(4 downto 0))
489 
    return std_logic_vector;
490 
 
491 
  ---------------------------------------------------------------------------
492 
  -- Create a RapidIO physical layer control symbol.
493 
  ---------------------------------------------------------------------------
494 
  function RioControlSymbolCreate(
495 
    constant stype0 : in std_logic_vector(2 downto 0);
496 
    constant parameter0 : in std_logic_vector(4 downto 0);
497 
    constant parameter1 : in std_logic_vector(4 downto 0);
498 
    constant stype1 : in std_logic_vector(2 downto 0);
499 
    constant cmd : in std_logic_vector(2 downto 0))
500 
    return std_logic_vector;
501 
 
502 
  -----------------------------------------------------------------------------
503 
  -- Crc16 calculation function.
504 
  -- CITT, polynom=0x1021.
505 
  -----------------------------------------------------------------------------
506 
  function Crc16(constant data : in std_logic_vector(15 downto 0);
507 
                 constant crc : in std_logic_vector(15 downto 0))
508 
    return std_logic_vector;
509 
 
510 
  ---------------------------------------------------------------------------
511 
  -- Create a randomly initialized data array.
512 
  ---------------------------------------------------------------------------
513 
  procedure CreateRandomPayload(
514 47 magro732 
    variable payload : out HalfwordArray;
515 2 magro732 
    variable seed1 : inout positive;
516 
    variable seed2 : inout positive);
517 
  procedure CreateRandomPayload(
518 47 magro732 
    variable payload : out DoublewordArray;
519 2 magro732 
    variable seed1 : inout positive;
520 
    variable seed2 : inout positive);
521 
 
522 
  ---------------------------------------------------------------------------
523 
  -- Create a generic RapidIO frame.
524 
  ---------------------------------------------------------------------------
525 
  function RioFrameCreate(
526 
    constant ackId : in std_logic_vector(4 downto 0);
527 
    constant vc : in std_logic;
528 
    constant crf : in std_logic;
529 
    constant prio : in std_logic_vector(1 downto 0);
530 
    constant tt : in std_logic_vector(1 downto 0);
531 
    constant ftype : in std_logic_vector(3 downto 0);
532 
    constant sourceId : in std_logic_vector(15 downto 0);
533 
    constant destId : in std_logic_vector(15 downto 0);
534 
    constant payload : in RioPayload)
535 
    return RioFrame;
536 
 
537 
  ---------------------------------------------------------------------------
538 
  -- Create a NWRITE RapidIO frame.
539 
  ---------------------------------------------------------------------------
540 
  function RioNwrite(
541 
    constant wrsize : in std_logic_vector(3 downto 0);
542 45 magro732 
    constant address : in std_logic_vector(28 downto 0);
543 
    constant wdptr : in std_logic;
544 
    constant xamsbs : in std_logic_vector(1 downto 0);
545 
    constant dataLength : in natural range 1 to 32;
546 
    constant data : in DoublewordArray(0 to 31))
547 
    return RioPayload;
548 
 
549 
  ---------------------------------------------------------------------------
550 
  -- Create a NWRITER RapidIO frame.
551 
  ---------------------------------------------------------------------------
552 
  function RioNwriteR(
553 
    constant wrsize : in std_logic_vector(3 downto 0);
554 2 magro732 
    constant tid : in std_logic_vector(7 downto 0);
555 
    constant address : in std_logic_vector(28 downto 0);
556 
    constant wdptr : in std_logic;
557 
    constant xamsbs : in std_logic_vector(1 downto 0);
558 
    constant dataLength : in natural range 1 to 32;
559 
    constant data : in DoublewordArray(0 to 31))
560 
    return RioPayload;
561 
 
562 
  ---------------------------------------------------------------------------
563 
  -- Create a NREAD RapidIO frame.
564 
  ---------------------------------------------------------------------------
565 
  function RioNread(
566 
    constant rdsize : in std_logic_vector(3 downto 0);
567 
    constant tid : in std_logic_vector(7 downto 0);
568 
    constant address : in std_logic_vector(28 downto 0);
569 
    constant wdptr : in std_logic;
570 
    constant xamsbs : in std_logic_vector(1 downto 0))
571 
    return RioPayload;
572 
 
573 
  ---------------------------------------------------------------------------
574 
  -- Create a RESPONSE RapidIO frame.
575 
  ---------------------------------------------------------------------------
576 
  function RioResponse(
577 
    constant status : in std_logic_vector(3 downto 0);
578 
    constant tid : in std_logic_vector(7 downto 0);
579 
    constant dataLength : in natural range 0 to 32;
580 
    constant data : in DoublewordArray(0 to 31))
581 
    return RioPayload;
582 
 
583 
  ---------------------------------------------------------------------------
584 
  -- Create a Maintenance RapidIO frame.
585 
  ---------------------------------------------------------------------------
586 
  function RioMaintenance(
587 
    constant transaction : in std_logic_vector(3 downto 0);
588 
    constant size : in std_logic_vector(3 downto 0);
589 
    constant tid : in std_logic_vector(7 downto 0);
590 
    constant hopCount : in std_logic_vector(7 downto 0);
591 
    constant configOffset : in std_logic_vector(20 downto 0);
592 
    constant wdptr : in std_logic;
593 
    constant dataLength : in natural range 0 to 8;
594 
    constant data : in DoublewordArray(0 to 7))
595 
    return RioPayload;
596 
 
597 
  -----------------------------------------------------------------------------
598 
  -- Function to convert a std_logic_vector to a string.
599 
  -----------------------------------------------------------------------------
600 
  function byteToString(constant byte : std_logic_vector(7 downto 0))
601 
    return string;
602 
 
603 
  ---------------------------------------------------------------------------
604 
  -- Procedure to print to report file and output
605 
  ---------------------------------------------------------------------------
606 
  procedure PrintR( constant str : string );
607 
 
608 
  ---------------------------------------------------------------------------
609 
  -- Procedure to print to spec file
610 
  ---------------------------------------------------------------------------
611 
  procedure PrintS( constant str : string );
612 
 
613 
  ---------------------------------------------------------------------------
614 
  -- Procedure to Assert Expression
615 
  ---------------------------------------------------------------------------
616 
  procedure AssertE( constant exp: boolean; constant str : string );
617 
 
618 
  ---------------------------------------------------------------------------
619 
  -- Procedure to Print Error
620 
  ---------------------------------------------------------------------------
621 
  procedure PrintE( constant str : string );
622 
 
623 
end package;
624 
 
625 
-------------------------------------------------------------------------------
626 
-- RioCommon package body description.
627 
-------------------------------------------------------------------------------
628 
package body rio_common is
629 
  -----------------------------------------------------------------------------
630 
  -- Crc5 calculation function.
631 
  -- ITU, polynom=0x15.
632 
  -----------------------------------------------------------------------------
633 
  function Crc5(constant data : in std_logic_vector(18 downto 0);
634 
                constant crc : in std_logic_vector(4 downto 0))
635 
    return std_logic_vector is
636 
    type crcTableType is array (0 to 31) of std_logic_vector(7 downto 0);
637 
    constant crcTable : crcTableType := (
638 
      x"00", x"15", x"1f", x"0a", x"0b", x"1e", x"14", x"01",
639 
      x"16", x"03", x"09", x"1c", x"1d", x"08", x"02", x"17",
640 
      x"19", x"0c", x"06", x"13", x"12", x"07", x"0d", x"18",
641 
      x"0f", x"1a", x"10", x"05", x"04", x"11", x"1b", x"0e" );
642 
    variable index : natural range 0 to 31;
643 
    variable result : std_logic_vector(4 downto 0);
644 
  begin
645 
    result := crc;
646 
    index := to_integer(unsigned(data(18 downto 14) xor result));
647 
    result := crcTable(index)(4 downto 0);
648 
    index := to_integer(unsigned(data(13 downto 9) xor result));
649 
    result := crcTable(index)(4 downto 0);
650 
    index := to_integer(unsigned(data(8 downto 4) xor result));
651 
    result := crcTable(index)(4 downto 0);
652 
    index := to_integer(unsigned((data(3 downto 0) & '0') xor result));
653 
    return crcTable(index)(4 downto 0);
654 
  end Crc5;
655 
 
656 
  ---------------------------------------------------------------------------
657 
  -- Create a RapidIO physical layer control symbol.
658 
  ---------------------------------------------------------------------------
659 
  function RioControlSymbolCreate(
660 
    constant stype0 : in std_logic_vector(2 downto 0);
661 
    constant parameter0 : in std_logic_vector(4 downto 0);
662 
    constant parameter1 : in std_logic_vector(4 downto 0);
663 
    constant stype1 : in std_logic_vector(2 downto 0);
664 
    constant cmd : in std_logic_vector(2 downto 0))
665 
    return std_logic_vector is
666 37 magro732 
    variable returnValue : std_logic_vector(23 downto 0);
667 2 magro732 
    variable symbolData : std_logic_vector(18 downto 0);
668 
  begin
669 
    symbolData(18 downto 16) := stype0;
670 
    symbolData(15 downto 11) := parameter0;
671 
    symbolData(10 downto 6) := parameter1;
672 
    symbolData(5 downto 3) := stype1;
673 
    symbolData(2 downto 0) := cmd;
674 
 
675 37 magro732 
    returnValue(23 downto 5) := symbolData;
676 
    returnValue(4 downto 0) := Crc5(symbolData, "11111");
677 2 magro732 
 
678 
    return returnValue;
679 
  end function;
680 
 
681 
  -----------------------------------------------------------------------------
682 
  -- Crc16 calculation function.
683 
  -- CITT, polynom=0x1021.
684 
  -----------------------------------------------------------------------------
685 
  function Crc16(constant data : in std_logic_vector(15 downto 0);
686 
                 constant crc : in std_logic_vector(15 downto 0))
687 
    return std_logic_vector is
688 
    type crcTableType is array (0 to 255) of std_logic_vector(15 downto 0);
689 
    constant crcTable : crcTableType := (
690 
      x"0000", x"1021", x"2042", x"3063", x"4084", x"50a5", x"60c6", x"70e7",
691 
      x"8108", x"9129", x"a14a", x"b16b", x"c18c", x"d1ad", x"e1ce", x"f1ef",
692 
      x"1231", x"0210", x"3273", x"2252", x"52b5", x"4294", x"72f7", x"62d6",
693 
      x"9339", x"8318", x"b37b", x"a35a", x"d3bd", x"c39c", x"f3ff", x"e3de",
694 
      x"2462", x"3443", x"0420", x"1401", x"64e6", x"74c7", x"44a4", x"5485",
695 
      x"a56a", x"b54b", x"8528", x"9509", x"e5ee", x"f5cf", x"c5ac", x"d58d",
696 
      x"3653", x"2672", x"1611", x"0630", x"76d7", x"66f6", x"5695", x"46b4",
697 
      x"b75b", x"a77a", x"9719", x"8738", x"f7df", x"e7fe", x"d79d", x"c7bc",
698 
      x"48c4", x"58e5", x"6886", x"78a7", x"0840", x"1861", x"2802", x"3823",
699 
      x"c9cc", x"d9ed", x"e98e", x"f9af", x"8948", x"9969", x"a90a", x"b92b",
700 
      x"5af5", x"4ad4", x"7ab7", x"6a96", x"1a71", x"0a50", x"3a33", x"2a12",
701 
      x"dbfd", x"cbdc", x"fbbf", x"eb9e", x"9b79", x"8b58", x"bb3b", x"ab1a",
702 
      x"6ca6", x"7c87", x"4ce4", x"5cc5", x"2c22", x"3c03", x"0c60", x"1c41",
703 
      x"edae", x"fd8f", x"cdec", x"ddcd", x"ad2a", x"bd0b", x"8d68", x"9d49",
704 
      x"7e97", x"6eb6", x"5ed5", x"4ef4", x"3e13", x"2e32", x"1e51", x"0e70",
705 
      x"ff9f", x"efbe", x"dfdd", x"cffc", x"bf1b", x"af3a", x"9f59", x"8f78",
706 
      x"9188", x"81a9", x"b1ca", x"a1eb", x"d10c", x"c12d", x"f14e", x"e16f",
707 
      x"1080", x"00a1", x"30c2", x"20e3", x"5004", x"4025", x"7046", x"6067",
708 
      x"83b9", x"9398", x"a3fb", x"b3da", x"c33d", x"d31c", x"e37f", x"f35e",
709 
      x"02b1", x"1290", x"22f3", x"32d2", x"4235", x"5214", x"6277", x"7256",
710 
      x"b5ea", x"a5cb", x"95a8", x"8589", x"f56e", x"e54f", x"d52c", x"c50d",
711 
      x"34e2", x"24c3", x"14a0", x"0481", x"7466", x"6447", x"5424", x"4405",
712 
      x"a7db", x"b7fa", x"8799", x"97b8", x"e75f", x"f77e", x"c71d", x"d73c",
713 
      x"26d3", x"36f2", x"0691", x"16b0", x"6657", x"7676", x"4615", x"5634",
714 
      x"d94c", x"c96d", x"f90e", x"e92f", x"99c8", x"89e9", x"b98a", x"a9ab",
715 
      x"5844", x"4865", x"7806", x"6827", x"18c0", x"08e1", x"3882", x"28a3",
716 
      x"cb7d", x"db5c", x"eb3f", x"fb1e", x"8bf9", x"9bd8", x"abbb", x"bb9a",
717 
      x"4a75", x"5a54", x"6a37", x"7a16", x"0af1", x"1ad0", x"2ab3", x"3a92",
718 
      x"fd2e", x"ed0f", x"dd6c", x"cd4d", x"bdaa", x"ad8b", x"9de8", x"8dc9",
719 
      x"7c26", x"6c07", x"5c64", x"4c45", x"3ca2", x"2c83", x"1ce0", x"0cc1",
720 
      x"ef1f", x"ff3e", x"cf5d", x"df7c", x"af9b", x"bfba", x"8fd9", x"9ff8",
721 
      x"6e17", x"7e36", x"4e55", x"5e74", x"2e93", x"3eb2", x"0ed1", x"1ef0" );
722 
    variable index : natural range 0 to 255;
723 
    variable result : std_logic_vector(15 downto 0);
724 
  begin
725 
    result := crc;
726 
    index := to_integer(unsigned(data(15 downto 8) xor result(15 downto 8)));
727 
    result := crcTable(index) xor (result(7 downto 0) & x"00");
728 
    index := to_integer(unsigned(data(7 downto 0) xor result(15 downto 8)));
729 
    result := crcTable(index) xor (result(7 downto 0) & x"00");
730 
    return result;
731 
  end Crc16;
732 
 
733 
  ---------------------------------------------------------------------------
734 
  -- Create a randomly initialized data array.
735 
  ---------------------------------------------------------------------------
736 
  procedure CreateRandomPayload(
737 47 magro732 
    variable payload : out HalfwordArray;
738 2 magro732 
    variable seed1 : inout positive;
739 
    variable seed2 : inout positive) is
740 
    variable rand: real;
741 
    variable int_rand: integer;
742 
    variable stim: std_logic_vector(7 downto 0);
743 
  begin
744 
    for i in payload'range loop
745 
      uniform(seed1, seed2, rand);
746 
      int_rand := integer(trunc(rand*256.0));
747 
      payload(i)(7 downto 0) := std_logic_vector(to_unsigned(int_rand, 8));
748 
      uniform(seed1, seed2, rand);
749 
      int_rand := integer(trunc(rand*256.0));
750 
      payload(i)(15 downto 8) := std_logic_vector(to_unsigned(int_rand, 8));
751 
    end loop;
752 
  end procedure;
753 
 
754 
  procedure CreateRandomPayload(
755 47 magro732 
    variable payload : out DoublewordArray;
756 2 magro732 
    variable seed1 : inout positive;
757 
    variable seed2 : inout positive) is
758 
    variable rand: real;
759 
    variable int_rand: integer;
760 
    variable stim: std_logic_vector(7 downto 0);
761 
  begin
762 
    for i in payload'range loop
763 
      uniform(seed1, seed2, rand);
764 
      int_rand := integer(trunc(rand*256.0));
765 
      payload(i)(7 downto 0) := std_logic_vector(to_unsigned(int_rand, 8));
766 
      uniform(seed1, seed2, rand);
767 
      int_rand := integer(trunc(rand*256.0));
768 
      payload(i)(15 downto 8) := std_logic_vector(to_unsigned(int_rand, 8));
769 
      uniform(seed1, seed2, rand);
770 
      int_rand := integer(trunc(rand*256.0));
771 
      payload(i)(23 downto 16) := std_logic_vector(to_unsigned(int_rand, 8));
772 
      uniform(seed1, seed2, rand);
773 
      int_rand := integer(trunc(rand*256.0));
774 
      payload(i)(31 downto 24) := std_logic_vector(to_unsigned(int_rand, 8));
775 
      uniform(seed1, seed2, rand);
776 
      int_rand := integer(trunc(rand*256.0));
777 
      payload(i)(39 downto 32) := std_logic_vector(to_unsigned(int_rand, 8));
778 
      uniform(seed1, seed2, rand);
779 
      int_rand := integer(trunc(rand*256.0));
780 
      payload(i)(47 downto 40) := std_logic_vector(to_unsigned(int_rand, 8));
781 
      uniform(seed1, seed2, rand);
782 
      int_rand := integer(trunc(rand*256.0));
783 
      payload(i)(55 downto 48) := std_logic_vector(to_unsigned(int_rand, 8));
784 
      uniform(seed1, seed2, rand);
785 
      int_rand := integer(trunc(rand*256.0));
786 
      payload(i)(63 downto 56) := std_logic_vector(to_unsigned(int_rand, 8));
787 
    end loop;
788 
  end procedure;
789 
  ---------------------------------------------------------------------------
790 
  -- Create a generic RapidIO frame.
791 
  ---------------------------------------------------------------------------
792 
  function RioFrameCreate(
793 
    constant ackId : in std_logic_vector(4 downto 0);
794 
    constant vc : in std_logic;
795 
    constant crf : in std_logic;
796 
    constant prio : in std_logic_vector(1 downto 0);
797 
    constant tt : in std_logic_vector(1 downto 0);
798 
    constant ftype : in std_logic_vector(3 downto 0);
799 
    constant sourceId : in std_logic_vector(15 downto 0);
800 
    constant destId : in std_logic_vector(15 downto 0);
801 
    constant payload : in RioPayload) return RioFrame is
802 
    variable frame : RioFrame;
803 
    variable result : HalfwordArray(0 to 137);
804 
    variable crc : std_logic_vector(15 downto 0) := x"ffff";
805 
  begin
806 
    -- Add the header and addresses.
807 
    result(0) := ackId & "0" & vc & crf & prio & tt & ftype;
808 
    result(1) := destId;
809 
    result(2) := sourceId;
810 
 
811 
    -- Update the calculated CRC with the header contents.
812 
    crc := Crc16("00000" & result(0)(10 downto 0), crc);
813 
    crc := Crc16(result(1), crc);
814 
    crc := Crc16(result(2), crc);
815 
 
816 
    -- Check if a single CRC should be added or two.
817 
    if (payload.length <= 37) then
818 
      -- Single CRC.
819 
      for i in 0 to payload.length-1 loop
820 
        result(i+3) := payload.data(i);
821 
        crc := Crc16(payload.data(i), crc);
822 
      end loop;
823 
      result(payload.length+3) := crc;
824 
 
825 
      -- Check if paddning is needed to make the payload even 32-bit.
826 
      if ((payload.length mod 2) = 1) then
827 
        result(payload.length+4) := x"0000";
828 
        frame.length := (payload.length+5) / 2;
829 
      else
830 
        frame.length := (payload.length+4) / 2;
831 
      end if;
832 
    else
833 
      -- Double CRC.
834 
      for i in 0 to 36 loop
835 
        result(i+3) := payload.data(i);
836 
        crc := Crc16(payload.data(i), crc);
837 
      end loop;
838 
 
839 
      -- Add in-the-middle crc.
840 
      result(40) := crc;
841 
      crc := Crc16(crc, crc);
842 
 
843 
      for i in 37 to payload.length-1 loop
844 
        result(i+4) := payload.data(i);
845 
        crc := Crc16(payload.data(i), crc);
846 
      end loop;
847 
      result(payload.length+4) := crc;
848 
 
849 
      -- Check if paddning is needed to make the payload even 32-bit.
850 
      if ((payload.length mod 2) = 0) then
851 
        result(payload.length+5) := x"0000";
852 
        frame.length := (payload.length+6) / 2;
853 
      else
854 
        frame.length := (payload.length+5) / 2;
855 
      end if;
856 
    end if;
857 
 
858 
    -- Update the result length.
859 
    for i in 0 to frame.length-1 loop
860 
      frame.payload(i) := result(2*i) & result(2*i+1);
861 
    end loop;
862 
 
863 
    return frame;
864 
  end function;
865 
 
866 
  -----------------------------------------------------------------------------
867 
  --
868 
  -----------------------------------------------------------------------------
869 
  function RioNwrite(
870 
    constant wrsize : in std_logic_vector(3 downto 0);
871 
    constant address : in std_logic_vector(28 downto 0);
872 
    constant wdptr : in std_logic;
873 
    constant xamsbs : in std_logic_vector(1 downto 0);
874 
    constant dataLength : in natural range 1 to 32;
875 
    constant data : in DoublewordArray(0 to 31))
876 
    return RioPayload is
877 
    variable payload : RioPayload;
878 
  begin
879 
    payload.data(0)(15 downto 12) := "0100";
880 
    payload.data(0)(11 downto 8) := wrsize;
881 45 magro732 
    payload.data(0)(7 downto 0) := (others=>'0');
882 
 
883 
    payload.data(1) := address(28 downto 13);
884 
 
885 
    payload.data(2)(15 downto 3) := address(12 downto 0);
886 
    payload.data(2)(2) := wdptr;
887 
    payload.data(2)(1 downto 0) := xamsbs;
888 
 
889 
    for i in 0 to dataLength-1 loop
890 
      payload.data(3+4*i) := data(i)(63 downto 48);
891 
      payload.data(4+4*i) := data(i)(47 downto 32);
892 
      payload.data(5+4*i) := data(i)(31 downto 16);
893 
      payload.data(6+4*i) := data(i)(15 downto 0);
894 
    end loop;
895 
 
896 
    payload.length := 3 + 4*dataLength;
897 
 
898 
    return payload;
899 
  end function;
900 
 
901 
  -----------------------------------------------------------------------------
902 
  --
903 
  -----------------------------------------------------------------------------
904 
  function RioNwriteR(
905 
    constant wrsize : in std_logic_vector(3 downto 0);
906 
    constant tid : in std_logic_vector(7 downto 0);
907 
    constant address : in std_logic_vector(28 downto 0);
908 
    constant wdptr : in std_logic;
909 
    constant xamsbs : in std_logic_vector(1 downto 0);
910 
    constant dataLength : in natural range 1 to 32;
911 
    constant data : in DoublewordArray(0 to 31))
912 
    return RioPayload is
913 
    variable payload : RioPayload;
914 
  begin
915 
    payload.data(0)(15 downto 12) := "0101";
916 
    payload.data(0)(11 downto 8) := wrsize;
917 2 magro732 
    payload.data(0)(7 downto 0) := tid;
918 
 
919 
    payload.data(1) := address(28 downto 13);
920 
 
921 
    payload.data(2)(15 downto 3) := address(12 downto 0);
922 
    payload.data(2)(2) := wdptr;
923 
    payload.data(2)(1 downto 0) := xamsbs;
924 
 
925 
    for i in 0 to dataLength-1 loop
926 
      payload.data(3+4*i) := data(i)(63 downto 48);
927 
      payload.data(4+4*i) := data(i)(47 downto 32);
928 
      payload.data(5+4*i) := data(i)(31 downto 16);
929 
      payload.data(6+4*i) := data(i)(15 downto 0);
930 
    end loop;
931 
 
932 
    payload.length := 3 + 4*dataLength;
933 
 
934 
    return payload;
935 
  end function;
936 
 
937 
  -----------------------------------------------------------------------------
938 
  --
939 
  -----------------------------------------------------------------------------
940 
  function RioNread(
941 
    constant rdsize : in std_logic_vector(3 downto 0);
942 
    constant tid : in std_logic_vector(7 downto 0);
943 
    constant address : in std_logic_vector(28 downto 0);
944 
    constant wdptr : in std_logic;
945 
    constant xamsbs : in std_logic_vector(1 downto 0))
946 
    return RioPayload is
947 
    variable payload : RioPayload;
948 
  begin
949 
    payload.data(0)(15 downto 12) := "0100";
950 
    payload.data(0)(11 downto 8) := rdsize;
951 
    payload.data(0)(7 downto 0) := tid;
952 
 
953 
    payload.data(1) := address(28 downto 13);
954 
 
955 
    payload.data(2)(15 downto 3) := address(12 downto 0);
956 
    payload.data(2)(2) := wdptr;
957 
    payload.data(2)(1 downto 0) := xamsbs;
958 
 
959 
    payload.length := 3;
960 
 
961 
    return payload;
962 
  end function;
963 
 
964 
  ---------------------------------------------------------------------------
965 
  -- Create a RESPONSE RapidIO frame.
966 
  ---------------------------------------------------------------------------
967 
  function RioResponse(
968 
    constant status : in std_logic_vector(3 downto 0);
969 
    constant tid : in std_logic_vector(7 downto 0);
970 
    constant dataLength : in natural range 0 to 32;
971 
    constant data : in DoublewordArray(0 to 31))
972 
    return RioPayload is
973 
    variable payload : RioPayload;
974 
  begin
975 
    payload.data(0)(11 downto 8) := status;
976 
    payload.data(0)(7 downto 0) := tid;
977 
 
978 
    if (dataLength = 0) then
979 
      payload.data(0)(15 downto 12) := "0000";
980 
      payload.length := 1;
981 
    else
982 
      payload.data(0)(15 downto 12) := "1000";
983 
 
984 
      for i in 0 to dataLength-1 loop
985 
        payload.data(1+4*i) := data(i)(63 downto 48);
986 
        payload.data(2+4*i) := data(i)(47 downto 32);
987 
        payload.data(3+4*i) := data(i)(31 downto 16);
988 
        payload.data(4+4*i) := data(i)(15 downto 0);
989 
      end loop;
990 
 
991 
      payload.length := 1 + 4*dataLength;
992 
    end if;
993 
 
994 
    return payload;
995 
  end function;
996 
 
997 
  ---------------------------------------------------------------------------
998 
  -- Create a Maintenance RapidIO frame.
999 
  ---------------------------------------------------------------------------
1000 
  function RioMaintenance(
1001 
    constant transaction : in std_logic_vector(3 downto 0);
1002 
    constant size : in std_logic_vector(3 downto 0);
1003 
    constant tid : in std_logic_vector(7 downto 0);
1004 
    constant hopCount : in std_logic_vector(7 downto 0);
1005 
    constant configOffset : in std_logic_vector(20 downto 0);
1006 
    constant wdptr : in std_logic;
1007 
    constant dataLength : in natural range 0 to 8;
1008 
    constant data : in DoublewordArray(0 to 7))
1009 
    return RioPayload is
1010 
    variable payload : RioPayload;
1011 
  begin
1012 
    payload.data(0)(15 downto 12) := transaction;
1013 
    payload.data(0)(11 downto 8) := size;
1014 
    payload.data(0)(7 downto 0) := tid;
1015 
 
1016 
    payload.data(1)(15 downto 8) := hopCount;
1017 
    payload.data(1)(7 downto 0) := configOffset(20 downto 13);
1018 
 
1019 
    payload.data(2)(15 downto 3) := configOffset(12 downto 0);
1020 
    payload.data(2)(2) := wdptr;
1021 
    payload.data(2)(1 downto 0) := "00";
1022 
 
1023 
    if (dataLength = 0) then
1024 
      payload.length := 3;
1025 
    else
1026 
      for i in 0 to dataLength-1 loop
1027 
        payload.data(3+4*i) := data(i)(63 downto 48);
1028 
        payload.data(4+4*i) := data(i)(47 downto 32);
1029 
        payload.data(5+4*i) := data(i)(31 downto 16);
1030 
        payload.data(6+4*i) := data(i)(15 downto 0);
1031 
      end loop;
1032 
 
1033 
      payload.length := 3 + 4*dataLength;
1034 
    end if;
1035 
 
1036 
    return payload;
1037 
  end function;
1038 
 
1039 
  -----------------------------------------------------------------------------
1040 
  -- Function to convert a std_logic_vector to a string.
1041 
  -----------------------------------------------------------------------------
1042 
  function byteToString(constant byte : std_logic_vector(7 downto 0))
1043 
    return string is
1044 
    constant table : string(1 to 16) := "0123456789abcdef";
1045 
    variable returnValue : string(1 to 2);
1046 
  begin
1047 
    returnValue(1) := table(to_integer(unsigned(byte(7 downto 4))) + 1);
1048 
    returnValue(2) := table(to_integer(unsigned(byte(3 downto 0))) + 1);
1049 
    return returnValue;
1050 
  end function;
1051 
 
1052 
  ---------------------------------------------------------------------------
1053 
  -- Procedure to print test report
1054 
  ---------------------------------------------------------------------------
1055 
  procedure PrintR( constant str : string ) is
1056 
    file reportFile  : text;
1057 
    variable reportLine, outputLine : line;
1058 
    variable fStatus: FILE_OPEN_STATUS;
1059 
  begin
1060 
    --Write report note to wave/transcript window
1061 
    report str severity NOTE;
1062 
  end PrintR;
1063 
 
1064 
  ---------------------------------------------------------------------------
1065 
  -- Procedure to print test spec
1066 
  ---------------------------------------------------------------------------
1067 
  procedure PrintS( constant str : string ) is
1068 
    file specFile  : text;
1069 
    variable specLine, outputLine : line;
1070 
    variable fStatus: FILE_OPEN_STATUS;
1071 
  begin
1072 
    --Write to spec file
1073 
    file_open(fStatus, specFile, "testspec.txt", append_mode);
1074 
    write(specLine, string'(str));
1075 
    writeline (specFile, specLine);
1076 
    file_close(specFile);
1077 
  end PrintS;
1078 
 
1079 
  ---------------------------------------------------------------------------
1080 
  -- Procedure to Assert Expression
1081 
  ---------------------------------------------------------------------------
1082 
  procedure AssertE( constant exp: boolean; constant str : string ) is
1083 
    file reportFile  : text;
1084 
    variable reportLine, outputLine : line;
1085 
    variable fStatus: FILE_OPEN_STATUS;
1086 
  begin
1087 
    if (not exp) then
1088 
      --Write to STD_OUTPUT
1089 
      report(str) severity error;
1090 
    else
1091 
      PrintR("Status: Passed");
1092 
      PrintS("Status: Passed");
1093 
    end if;
1094 
  end AssertE;
1095 
 
1096 
  ---------------------------------------------------------------------------
1097 
  -- Procedure to Print Error
1098 
  ---------------------------------------------------------------------------
1099 
  procedure PrintE( constant str : string ) is
1100 
    file reportFile  : text;
1101 
    variable reportLine, outputLine : line;
1102 
    variable fStatus: FILE_OPEN_STATUS;
1103 
  begin
1104 
    --Write to STD_OUTPUT
1105 
    report str severity error;
1106 
  end PrintE;
1107 
 
1108 
end rio_common;
1109 
 
1110 
 
1111 
 
1112 
-------------------------------------------------------------------------------
1113 
-- Crc16CITT
1114 
-- A CRC-16 calculator following the implementation proposed in the 2.2
1115 
-- standard.
1116 
-------------------------------------------------------------------------------
1117 
library ieee;
1118 
use ieee.std_logic_1164.all;
1119 
 
1120 
 
1121 
-------------------------------------------------------------------------------
1122 
-- Entity for Crc16CITT.
1123 
-------------------------------------------------------------------------------
1124 
entity Crc16CITT is
1125 
  port(
1126 
    d_i : in  std_logic_vector(15 downto 0);
1127 
    crc_i : in std_logic_vector(15 downto 0);
1128 
    crc_o : out std_logic_vector(15 downto 0));
1129 
end entity;
1130 
 
1131 
 
1132 
-------------------------------------------------------------------------------
1133 
-- Architecture for Crc16CITT.
1134 
-------------------------------------------------------------------------------
1135 
architecture Crc16Impl of Crc16CITT is
1136 
  signal d : std_logic_vector(0 to 15);
1137 
  signal c : std_logic_vector(0 to 15);
1138 
  signal e : std_logic_vector(0 to 15);
1139 
  signal cc : std_logic_vector(0 to 15);
1140 
begin
1141 
 
1142 
  -- Reverse the bit vector indexes to make them the same as in the standard.
1143 
  d(15) <= d_i(0); d(14) <= d_i(1); d(13) <= d_i(2); d(12) <= d_i(3);
1144 
  d(11) <= d_i(4); d(10) <= d_i(5); d(9) <= d_i(6); d(8) <= d_i(7);
1145 
  d(7) <= d_i(8); d(6) <= d_i(9); d(5) <= d_i(10); d(4) <= d_i(11);
1146 
  d(3) <= d_i(12); d(2) <= d_i(13); d(1) <= d_i(14); d(0) <= d_i(15);
1147 
 
1148 
  -- Reverse the bit vector indexes to make them the same as in the standard.
1149 
  c(15) <= crc_i(0); c(14) <= crc_i(1); c(13) <= crc_i(2); c(12) <= crc_i(3);
1150 
  c(11) <= crc_i(4); c(10) <= crc_i(5); c(9) <= crc_i(6); c(8) <= crc_i(7);
1151 
  c(7) <= crc_i(8); c(6) <= crc_i(9); c(5) <= crc_i(10); c(4) <= crc_i(11);
1152 
  c(3) <= crc_i(12); c(2) <= crc_i(13); c(1) <= crc_i(14); c(0) <= crc_i(15);
1153 
 
1154 
  -- Calculate the resulting crc.
1155 
  e <= c xor d;
1156 
  cc(0) <= e(4) xor e(5) xor e(8) xor e(12);
1157 
  cc(1) <= e(5) xor e(6) xor e(9) xor e(13);
1158 
  cc(2) <= e(6) xor e(7) xor e(10) xor e(14);
1159 
  cc(3) <= e(0) xor e(7) xor e(8) xor e(11) xor e(15);
1160 
  cc(4) <= e(0) xor e(1) xor e(4) xor e(5) xor e(9);
1161 
  cc(5) <= e(1) xor e(2) xor e(5) xor e(6) xor e(10);
1162 
  cc(6) <= e(0) xor e(2) xor e(3) xor e(6) xor e(7) xor e(11);
1163 
  cc(7) <= e(0) xor e(1) xor e(3) xor e(4) xor e(7) xor e(8) xor e(12);
1164 
  cc(8) <= e(0) xor e(1) xor e(2) xor e(4) xor e(5) xor e(8) xor e(9) xor e(13);
1165 
  cc(9) <= e(1) xor e(2) xor e(3) xor e(5) xor e(6) xor e(9) xor e(10) xor e(14);
1166 
  cc(10) <= e(2) xor e(3) xor e(4) xor e(6) xor e(7) xor e(10) xor e(11) xor e(15);
1167 
  cc(11) <= e(0) xor e(3) xor e(7) xor e(11);
1168 
  cc(12) <= e(0) xor e(1) xor e(4) xor e(8) xor e(12);
1169 
  cc(13) <= e(1) xor e(2) xor e(5) xor e(9) xor e(13);
1170 
  cc(14) <= e(2) xor e(3) xor e(6) xor e(10) xor e(14);
1171 
  cc(15) <= e(3) xor e(4) xor e(7) xor e(11) xor e(15);
1172 
 
1173 
  -- Reverse the bit vector indexes to make them the same as in the standard.
1174 
  crc_o(15) <= cc(0); crc_o(14) <= cc(1); crc_o(13) <= cc(2); crc_o(12) <= cc(3);
1175 
  crc_o(11) <= cc(4); crc_o(10) <= cc(5); crc_o(9) <= cc(6); crc_o(8) <= cc(7);
1176 
  crc_o(7) <= cc(8); crc_o(6) <= cc(9); crc_o(5) <= cc(10); crc_o(4) <= cc(11);
1177 
  crc_o(3) <= cc(12); crc_o(2) <= cc(13); crc_o(1) <= cc(14); crc_o(0) <= cc(15);
1178 
 
1179 
end architecture;
1180 
 
1181 
 
1182 
 
1183 
-------------------------------------------------------------------------------
1184 
-- MemoryDualPort
1185 
-- Generic synchronous memory with one read/write port and one read port.
1186 
-------------------------------------------------------------------------------
1187 
 
1188 
library ieee;
1189 
use ieee.std_logic_1164.all;
1190 
use ieee.numeric_std.all;
1191 
 
1192 
 
1193 
-------------------------------------------------------------------------------
1194 
-- Entity for MemoryDualPort.
1195 
-------------------------------------------------------------------------------
1196 
entity MemoryDualPort is
1197 
  generic(
1198 
    ADDRESS_WIDTH : natural := 1;
1199 
    DATA_WIDTH : natural := 1);
1200 
  port(
1201 
    clkA_i : in std_logic;
1202 
    enableA_i : in std_logic;
1203 
    writeEnableA_i : in std_logic;
1204 
    addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
1205 
    dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
1206 
    dataA_o : out std_logic_vector(DATA_WIDTH-1 downto 0);
1207 
 
1208 
    clkB_i : in std_logic;
1209 
    enableB_i : in std_logic;
1210 
    addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
1211 
    dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
1212 
end entity;
1213 
 
1214 
 
1215 
-------------------------------------------------------------------------------
1216 
-- Architecture for MemoryDualPort.
1217 
-------------------------------------------------------------------------------
1218 
architecture MemoryDualPortImpl of MemoryDualPort is
1219 
  type MemoryType is array (natural range <>) of
1220 
    std_logic_vector(DATA_WIDTH-1 downto 0);
1221 
 
1222 
  signal memory : MemoryType(0 to (2**ADDRESS_WIDTH)-1);
1223 
 
1224 
begin
1225 
  process(clkA_i)
1226 
  begin
1227 
    if (clkA_i'event and clkA_i = '1') then
1228 
      if (enableA_i = '1') then
1229 
        if (writeEnableA_i = '1') then
1230 
          memory(to_integer(unsigned(addressA_i))) <= dataA_i;
1231 
        end if;
1232 
 
1233 
        dataA_o <= memory(to_integer(unsigned(addressA_i)));
1234 
      end if;
1235 
    end if;
1236 
  end process;
1237 
 
1238 
  process(clkB_i)
1239 
  begin
1240 
    if (clkB_i'event and clkB_i = '1') then
1241 
      if (enableB_i = '1') then
1242 
        dataB_o <= memory(to_integer(unsigned(addressB_i)));
1243 
      end if;
1244 
    end if;
1245 
  end process;
1246 
 
1247 
end architecture;
1248 
 
1249 
 
1250 
 
1251 
-------------------------------------------------------------------------------
1252 
-- MemorySimpleDualPort
1253 
-- Generic synchronous memory with one write port and one read port.
1254 
-------------------------------------------------------------------------------
1255 
 
1256 
library ieee;
1257 
use ieee.std_logic_1164.all;
1258 
use ieee.numeric_std.all;
1259 
 
1260 
 
1261 
-------------------------------------------------------------------------------
1262 
-- Entity for MemorySimpleDualPort.
1263 
-------------------------------------------------------------------------------
1264 
entity MemorySimpleDualPort is
1265 
  generic(
1266 
    ADDRESS_WIDTH : natural := 1;
1267 
    DATA_WIDTH : natural := 1);
1268 
  port(
1269 
    clkA_i : in std_logic;
1270 
    enableA_i : in std_logic;
1271 
    addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
1272 
    dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
1273 
 
1274 
    clkB_i : in std_logic;
1275 
    enableB_i : in std_logic;
1276 
    addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
1277 
    dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
1278 
end entity;
1279 
 
1280 
 
1281 
-------------------------------------------------------------------------------
1282 
-- Architecture for MemorySimpleDualPort.
1283 
-------------------------------------------------------------------------------
1284 
architecture MemorySimpleDualPortImpl of MemorySimpleDualPort is
1285 
  type MemoryType is array (natural range <>) of
1286 
    std_logic_vector(DATA_WIDTH-1 downto 0);
1287 
 
1288 
  signal memory : MemoryType(0 to (2**ADDRESS_WIDTH)-1);
1289 
 
1290 
begin
1291 
  process(clkA_i)
1292 
  begin
1293 
    if (clkA_i'event and clkA_i = '1') then
1294 
      if (enableA_i = '1') then
1295 
        memory(to_integer(unsigned(addressA_i))) <= dataA_i;
1296 
      end if;
1297 
    end if;
1298 
  end process;
1299 
 
1300 
  process(clkB_i)
1301 
  begin
1302 
    if (clkB_i'event and clkB_i = '1') then
1303 
      if (enableB_i = '1') then
1304 
        dataB_o <= memory(to_integer(unsigned(addressB_i)));
1305 
      end if;
1306 
    end if;
1307 
  end process;
1308 
 
1309 
end architecture;
1310 
 
1311 
 
1312 
 
1313 
-------------------------------------------------------------------------------
1314 
-- MemorySinglePort
1315 
-- Generic synchronous memory with one read/write port.
1316 
-------------------------------------------------------------------------------
1317 
 
1318 
library ieee;
1319 
use ieee.std_logic_1164.all;
1320 
use ieee.numeric_std.all;
1321 
 
1322 
 
1323 
-------------------------------------------------------------------------------
1324 
-- Entity for MemorySinglePort.
1325 
-------------------------------------------------------------------------------
1326 
entity MemorySinglePort is
1327 
  generic(
1328 
    ADDRESS_WIDTH : natural := 1;
1329 
    DATA_WIDTH : natural := 1);
1330 
  port(
1331 
    clk_i : in std_logic;
1332 
    enable_i : in std_logic;
1333 
    writeEnable_i : in std_logic;
1334 
    address_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
1335 
    data_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
1336 
    data_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
1337 
end entity;
1338 
 
1339 
 
1340 
-------------------------------------------------------------------------------
1341 
-- Architecture for MemorySinglePort.
1342 
-------------------------------------------------------------------------------
1343 
architecture MemorySinglePortImpl of MemorySinglePort is
1344 
  type MemoryType is array (natural range <>) of
1345 
    std_logic_vector(DATA_WIDTH-1 downto 0);
1346 
 
1347 
  signal memory : MemoryType(0 to (2**ADDRESS_WIDTH)-1);
1348 
 
1349 
begin
1350 
  process(clk_i)
1351 
  begin
1352 
    if (clk_i'event and clk_i = '1') then
1353 
      if (enable_i = '1') then
1354 
        if (writeEnable_i = '1') then
1355 
          memory(to_integer(unsigned(address_i))) <= data_i;
1356 
        end if;
1357 
 
1358 
        data_o <= memory(to_integer(unsigned(address_i)));
1359 
      end if;
1360 
    end if;
1361 
  end process;
1362 
 
1363 
end architecture;
1364 
 
1365 
 
1366 
 
1367 
 
1368 
-------------------------------------------------------------------------------
1369 
-- MemorySimpleDualPortAsync
1370 
-- Generic memory with one synchronous write port and one asynchronous read port.
1371 
-------------------------------------------------------------------------------
1372 
 
1373 
library ieee;
1374 
use ieee.std_logic_1164.all;
1375 
use ieee.numeric_std.all;
1376 
 
1377 
 
1378 
-------------------------------------------------------------------------------
1379 
-- Entity for MemorySimpleDualPortAsync.
1380 
-------------------------------------------------------------------------------
1381 
entity MemorySimpleDualPortAsync is
1382 
  generic(
1383 
    ADDRESS_WIDTH : natural := 1;
1384 
    DATA_WIDTH : natural := 1;
1385 
    INIT_VALUE : std_logic := 'U');
1386 
  port(
1387 
    clkA_i : in std_logic;
1388 
    enableA_i : in std_logic;
1389 
    addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
1390 
    dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
1391 
 
1392 
    addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
1393 
    dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
1394 
end entity;
1395 
 
1396 
 
1397 
-------------------------------------------------------------------------------
1398 
-- Architecture for MemorySimpleDualPortAsync.
1399 
-------------------------------------------------------------------------------
1400 
architecture MemorySimpleDualPortAsyncImpl of MemorySimpleDualPortAsync is
1401 
  type MemoryType is array (natural range <>) of
1402 
    std_logic_vector(DATA_WIDTH-1 downto 0);
1403 
 
1404 
  signal memory : MemoryType(0 to (2**ADDRESS_WIDTH)-1) := (others=>(others=>INIT_VALUE));
1405 
 
1406 
begin
1407 
  process(clkA_i)
1408 
  begin
1409 
    if (clkA_i'event and clkA_i = '1') then
1410 
      if (enableA_i = '1') then
1411 
        memory(to_integer(unsigned(addressA_i))) <= dataA_i;
1412 
      end if;
1413 
    end if;
1414 
  end process;
1415 
 
1416 
  dataB_o <= memory(to_integer(unsigned(addressB_i)));
1417 
 
1418 
end architecture;
1419 
 
1420 
 
1421 
 
1422 
 
1423 
 

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