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magro732 |
-------------------------------------------------------------------------------
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--
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-- RapidIO IP Library Core
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--
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-- This file is part of the RapidIO IP library project
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-- http://www.opencores.org/cores/rio/
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--
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-- Description
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-- Containing RapidIO packet switching functionality contained in the top
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-- entity RioSwitch.
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--
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-- To Do:
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magro732 |
-- - Add support for portWrite maintenance packets.
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-- - Add a real crossbar as interconnect.
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-- - Change the internal addressing to one-hot.
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-- - Remove acknowledge cycle when transfering packets between ports to double
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-- the bandwidth.
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-- - Add hot-swap.
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-- - Connect linkInitialized to all ports and read it from the source port
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-- using the interconnect. This will allow alternative routes since the
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-- sending port can see if a receiving port is up or not.
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-- - Add support for extended route.
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-- - Add validity-bit to know if a route has been activly set for a particular
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-- deviceId.
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magro732 |
--
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-- Author(s):
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-- - Magnus Rosenius, magro732@opencores.org
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--
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-------------------------------------------------------------------------------
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--
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-- Copyright (C) 2013 Authors and OPENCORES.ORG
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- either version 2.1 of the License, or (at your option) any
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-- later version.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.opencores.org/lgpl.shtml
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--
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-------------------------------------------------------------------------------
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magro732 |
-- Revision history.
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-- - Adding support for all sizes of maintenance packets.
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-- - Adding configAck to external config-space interface.
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-------------------------------------------------------------------------------
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2 |
magro732 |
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-------------------------------------------------------------------------------
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-- RioSwitch
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.rio_common.all;
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-------------------------------------------------------------------------------
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-- Entity for RioSwitch.
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-------------------------------------------------------------------------------
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entity RioSwitch is
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generic(
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SWITCH_PORTS : natural range 3 to 255 := 4;
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DEVICE_IDENTITY : std_logic_vector(15 downto 0);
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DEVICE_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
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DEVICE_REV : std_logic_vector(31 downto 0);
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ASSY_IDENTITY : std_logic_vector(15 downto 0);
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ASSY_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
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ASSY_REV : std_logic_vector(15 downto 0));
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port(
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clk : in std_logic;
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areset_n : in std_logic;
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writeFrameFull_i : in Array1(SWITCH_PORTS-1 downto 0);
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writeFrame_o : out Array1(SWITCH_PORTS-1 downto 0);
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writeFrameAbort_o : out Array1(SWITCH_PORTS-1 downto 0);
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writeContent_o : out Array1(SWITCH_PORTS-1 downto 0);
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writeContentData_o : out Array32(SWITCH_PORTS-1 downto 0);
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readFrameEmpty_i : in Array1(SWITCH_PORTS-1 downto 0);
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readFrame_o : out Array1(SWITCH_PORTS-1 downto 0);
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readFrameRestart_o : out Array1(SWITCH_PORTS-1 downto 0);
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readFrameAborted_i : in Array1(SWITCH_PORTS-1 downto 0);
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readContentEmpty_i : in Array1(SWITCH_PORTS-1 downto 0);
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readContent_o : out Array1(SWITCH_PORTS-1 downto 0);
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readContentEnd_i : in Array1(SWITCH_PORTS-1 downto 0);
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readContentData_i : in Array32(SWITCH_PORTS-1 downto 0);
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portLinkTimeout_o : out std_logic_vector(23 downto 0);
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linkInitialized_i : in Array1(SWITCH_PORTS-1 downto 0);
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outputPortEnable_o : out Array1(SWITCH_PORTS-1 downto 0);
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inputPortEnable_o : out Array1(SWITCH_PORTS-1 downto 0);
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localAckIdWrite_o : out Array1(SWITCH_PORTS-1 downto 0);
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clrOutstandingAckId_o : out Array1(SWITCH_PORTS-1 downto 0);
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inboundAckId_o : out Array5(SWITCH_PORTS-1 downto 0);
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outstandingAckId_o : out Array5(SWITCH_PORTS-1 downto 0);
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outboundAckId_o : out Array5(SWITCH_PORTS-1 downto 0);
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inboundAckId_i : in Array5(SWITCH_PORTS-1 downto 0);
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outstandingAckId_i : in Array5(SWITCH_PORTS-1 downto 0);
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outboundAckId_i : in Array5(SWITCH_PORTS-1 downto 0);
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configStb_o : out std_logic;
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configWe_o : out std_logic;
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configAddr_o : out std_logic_vector(23 downto 0);
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configData_o : out std_logic_vector(31 downto 0);
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magro732 |
configData_i : in std_logic_vector(31 downto 0);
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configAck_i : in std_logic);
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2 |
magro732 |
end entity;
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-------------------------------------------------------------------------------
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-- Architecture for RioSwitch.
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-------------------------------------------------------------------------------
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architecture RioSwitchImpl of RioSwitch is
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component RouteTableInterconnect is
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generic(
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WIDTH : natural range 1 to 256 := 8);
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port(
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clk : in std_logic;
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areset_n : in std_logic;
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stb_i : in Array1(WIDTH-1 downto 0);
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addr_i : in Array16(WIDTH-1 downto 0);
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dataM_o : out Array8(WIDTH-1 downto 0);
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ack_o : out Array1(WIDTH-1 downto 0);
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stb_o : out std_logic;
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addr_o : out std_logic_vector(15 downto 0);
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dataS_i : in std_logic_vector(7 downto 0);
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ack_i : in std_logic);
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end component;
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component SwitchPortInterconnect is
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generic(
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WIDTH : natural range 1 to 256 := 8);
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port(
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clk : in std_logic;
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areset_n : in std_logic;
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masterCyc_i : in Array1(WIDTH-1 downto 0);
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masterStb_i : in Array1(WIDTH-1 downto 0);
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masterWe_i : in Array1(WIDTH-1 downto 0);
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masterAddr_i : in Array10(WIDTH-1 downto 0);
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masterData_i : in Array32(WIDTH-1 downto 0);
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masterData_o : out Array1(WIDTH-1 downto 0);
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masterAck_o : out Array1(WIDTH-1 downto 0);
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slaveCyc_o : out Array1(WIDTH-1 downto 0);
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slaveStb_o : out Array1(WIDTH-1 downto 0);
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slaveWe_o : out Array1(WIDTH-1 downto 0);
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slaveAddr_o : out Array10(WIDTH-1 downto 0);
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slaveData_o : out Array32(WIDTH-1 downto 0);
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slaveData_i : in Array1(WIDTH-1 downto 0);
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slaveAck_i : in Array1(WIDTH-1 downto 0));
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end component;
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component SwitchPortMaintenance is
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generic(
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SWITCH_PORTS : natural range 0 to 255;
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DEVICE_IDENTITY : std_logic_vector(15 downto 0);
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DEVICE_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
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DEVICE_REV : std_logic_vector(31 downto 0);
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ASSY_IDENTITY : std_logic_vector(15 downto 0);
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ASSY_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
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ASSY_REV : std_logic_vector(15 downto 0));
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port(
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clk : in std_logic;
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areset_n : in std_logic;
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185 |
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lookupStb_i : in std_logic;
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lookupAddr_i : in std_logic_vector(15 downto 0);
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lookupData_o : out std_logic_vector(7 downto 0);
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lookupAck_o : out std_logic;
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masterCyc_o : out std_logic;
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masterStb_o : out std_logic;
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masterWe_o : out std_logic;
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masterAddr_o : out std_logic_vector(9 downto 0);
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194 |
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masterData_o : out std_logic_vector(31 downto 0);
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masterData_i : in std_logic;
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masterAck_i : in std_logic;
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slaveCyc_i : in std_logic;
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slaveStb_i : in std_logic;
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slaveWe_i : in std_logic;
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slaveAddr_i : in std_logic_vector(9 downto 0);
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slaveData_i : in std_logic_vector(31 downto 0);
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203 |
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slaveData_o : out std_logic;
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204 |
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slaveAck_o : out std_logic;
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206 |
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lookupStb_o : out std_logic;
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lookupAddr_o : out std_logic_vector(15 downto 0);
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lookupData_i : in std_logic_vector(7 downto 0);
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lookupAck_i : in std_logic;
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portLinkTimeout_o : out std_logic_vector(23 downto 0);
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linkInitialized_i : in Array1(SWITCH_PORTS-1 downto 0);
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outputPortEnable_o : out Array1(SWITCH_PORTS-1 downto 0);
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215 |
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inputPortEnable_o : out Array1(SWITCH_PORTS-1 downto 0);
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216 |
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localAckIdWrite_o : out Array1(SWITCH_PORTS-1 downto 0);
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217 |
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clrOutstandingAckId_o : out Array1(SWITCH_PORTS-1 downto 0);
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218 |
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inboundAckId_o : out Array5(SWITCH_PORTS-1 downto 0);
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219 |
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outstandingAckId_o : out Array5(SWITCH_PORTS-1 downto 0);
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220 |
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outboundAckId_o : out Array5(SWITCH_PORTS-1 downto 0);
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221 |
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inboundAckId_i : in Array5(SWITCH_PORTS-1 downto 0);
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222 |
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outstandingAckId_i : in Array5(SWITCH_PORTS-1 downto 0);
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223 |
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outboundAckId_i : in Array5(SWITCH_PORTS-1 downto 0);
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224 |
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225 |
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configStb_o : out std_logic;
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226 |
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configWe_o : out std_logic;
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227 |
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configAddr_o : out std_logic_vector(23 downto 0);
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228 |
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configData_o : out std_logic_vector(31 downto 0);
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229 |
47 |
magro732 |
configData_i : in std_logic_vector(31 downto 0);
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230 |
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configAck_i : in std_logic);
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231 |
2 |
magro732 |
end component;
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232 |
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233 |
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component SwitchPort is
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234 |
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generic(
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235 |
46 |
magro732 |
MAINTENANCE_LOOKUP : boolean;
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236 |
2 |
magro732 |
PORT_INDEX : natural);
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237 |
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port(
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238 |
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clk : in std_logic;
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239 |
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areset_n : in std_logic;
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240 |
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241 |
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masterCyc_o : out std_logic;
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242 |
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masterStb_o : out std_logic;
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243 |
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masterWe_o : out std_logic;
|
244 |
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masterAddr_o : out std_logic_vector(9 downto 0);
|
245 |
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masterData_o : out std_logic_vector(31 downto 0);
|
246 |
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masterData_i : in std_logic;
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247 |
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masterAck_i : in std_logic;
|
248 |
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|
249 |
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slaveCyc_i : in std_logic;
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250 |
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slaveStb_i : in std_logic;
|
251 |
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slaveWe_i : in std_logic;
|
252 |
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slaveAddr_i : in std_logic_vector(9 downto 0);
|
253 |
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slaveData_i : in std_logic_vector(31 downto 0);
|
254 |
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slaveData_o : out std_logic;
|
255 |
|
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slaveAck_o : out std_logic;
|
256 |
|
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|
257 |
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lookupStb_o : out std_logic;
|
258 |
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lookupAddr_o : out std_logic_vector(15 downto 0);
|
259 |
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lookupData_i : in std_logic_vector(7 downto 0);
|
260 |
|
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lookupAck_i : in std_logic;
|
261 |
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|
262 |
|
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readFrameEmpty_i : in std_logic;
|
263 |
|
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readFrame_o : out std_logic;
|
264 |
|
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readFrameRestart_o : out std_logic;
|
265 |
|
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readFrameAborted_i : in std_logic;
|
266 |
|
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readContentEmpty_i : in std_logic;
|
267 |
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readContent_o : out std_logic;
|
268 |
|
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readContentEnd_i : in std_logic;
|
269 |
|
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readContentData_i : in std_logic_vector(31 downto 0);
|
270 |
46 |
magro732 |
writeFramePort_o : out std_logic_vector(9 downto 0);
|
271 |
2 |
magro732 |
writeFrameFull_i : in std_logic;
|
272 |
|
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writeFrame_o : out std_logic;
|
273 |
|
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writeFrameAbort_o : out std_logic;
|
274 |
|
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writeContent_o : out std_logic;
|
275 |
|
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writeContentData_o : out std_logic_vector(31 downto 0));
|
276 |
|
|
end component;
|
277 |
|
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|
278 |
|
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signal masterLookupStb : Array1(SWITCH_PORTS downto 0);
|
279 |
|
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signal masterLookupAddr : Array16(SWITCH_PORTS downto 0);
|
280 |
|
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signal masterLookupData : Array8(SWITCH_PORTS downto 0);
|
281 |
|
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signal masterLookupAck : Array1(SWITCH_PORTS downto 0);
|
282 |
|
|
|
283 |
|
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signal slaveLookupStb : std_logic;
|
284 |
|
|
signal slaveLookupAddr : std_logic_vector(15 downto 0);
|
285 |
|
|
signal slaveLookupData : std_logic_vector(7 downto 0);
|
286 |
|
|
signal slaveLookupAck : std_logic;
|
287 |
|
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|
288 |
|
|
signal masterCyc : Array1(SWITCH_PORTS downto 0);
|
289 |
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signal masterStb : Array1(SWITCH_PORTS downto 0);
|
290 |
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signal masterWe : Array1(SWITCH_PORTS downto 0);
|
291 |
|
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signal masterAddr : Array10(SWITCH_PORTS downto 0);
|
292 |
|
|
signal masterDataWrite : Array32(SWITCH_PORTS downto 0);
|
293 |
|
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signal masterDataRead : Array1(SWITCH_PORTS downto 0);
|
294 |
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signal masterAck : Array1(SWITCH_PORTS downto 0);
|
295 |
|
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|
296 |
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signal slaveCyc : Array1(SWITCH_PORTS downto 0);
|
297 |
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signal slaveStb : Array1(SWITCH_PORTS downto 0);
|
298 |
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signal slaveWe : Array1(SWITCH_PORTS downto 0);
|
299 |
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signal slaveAddr : Array10(SWITCH_PORTS downto 0);
|
300 |
|
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signal slaveDataWrite : Array32(SWITCH_PORTS downto 0);
|
301 |
|
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signal slaveDataRead : Array1(SWITCH_PORTS downto 0);
|
302 |
|
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signal slaveAck : Array1(SWITCH_PORTS downto 0);
|
303 |
|
|
|
304 |
|
|
begin
|
305 |
|
|
|
306 |
|
|
-----------------------------------------------------------------------------
|
307 |
|
|
-- The routing table interconnect.
|
308 |
|
|
-----------------------------------------------------------------------------
|
309 |
|
|
RouteInterconnect: RouteTableInterconnect
|
310 |
|
|
generic map(
|
311 |
|
|
WIDTH=>SWITCH_PORTS+1)
|
312 |
|
|
port map(
|
313 |
|
|
clk=>clk, areset_n=>areset_n,
|
314 |
|
|
stb_i=>masterLookupStb, addr_i=>masterLookupAddr,
|
315 |
|
|
dataM_o=>masterLookupData, ack_o=>masterLookupAck,
|
316 |
|
|
stb_o=>slaveLookupStb, addr_o=>slaveLookupAddr,
|
317 |
|
|
dataS_i=>slaveLookupData, ack_i=>slaveLookupAck);
|
318 |
|
|
|
319 |
|
|
-----------------------------------------------------------------------------
|
320 |
|
|
-- The port interconnect.
|
321 |
|
|
-----------------------------------------------------------------------------
|
322 |
|
|
PortInterconnect: SwitchPortInterconnect
|
323 |
|
|
generic map(
|
324 |
|
|
WIDTH=>SWITCH_PORTS+1)
|
325 |
|
|
port map(
|
326 |
|
|
clk=>clk, areset_n=>areset_n,
|
327 |
|
|
masterCyc_i=>masterCyc, masterStb_i=>masterStb, masterWe_i=>masterWe, masterAddr_i=>masterAddr,
|
328 |
|
|
masterData_i=>masterDataWrite, masterData_o=>masterDataRead, masterAck_o=>masterAck,
|
329 |
|
|
slaveCyc_o=>slaveCyc, slaveStb_o=>slaveStb, slaveWe_o=>slaveWe, slaveAddr_o=>slaveAddr,
|
330 |
|
|
slaveData_o=>slaveDataWrite, slaveData_i=>slaveDataRead, slaveAck_i=>slaveAck);
|
331 |
|
|
|
332 |
|
|
-----------------------------------------------------------------------------
|
333 |
|
|
-- Data relaying port instantiation.
|
334 |
|
|
-----------------------------------------------------------------------------
|
335 |
|
|
PortGeneration: for portIndex in 0 to SWITCH_PORTS-1 generate
|
336 |
|
|
PortInst: SwitchPort
|
337 |
|
|
generic map(
|
338 |
46 |
magro732 |
MAINTENANCE_LOOKUP=>false,
|
339 |
2 |
magro732 |
PORT_INDEX=>portIndex)
|
340 |
|
|
port map(
|
341 |
|
|
clk=>clk, areset_n=>areset_n,
|
342 |
|
|
masterCyc_o=>masterCyc(portIndex), masterStb_o=>masterStb(portIndex),
|
343 |
|
|
masterWe_o=>masterWe(portIndex), masterAddr_o=>masterAddr(portIndex),
|
344 |
|
|
masterData_o=>masterDataWrite(portIndex),
|
345 |
|
|
masterData_i=>masterDataRead(portIndex), masterAck_i=>masterAck(portIndex),
|
346 |
|
|
slaveCyc_i=>slaveCyc(portIndex), slaveStb_i=>slaveStb(portIndex),
|
347 |
|
|
slaveWe_i=>slaveWe(portIndex), slaveAddr_i=>slaveAddr(portIndex),
|
348 |
|
|
slaveData_i=>slaveDataWrite(portIndex),
|
349 |
|
|
slaveData_o=>slaveDataRead(portIndex), slaveAck_o=>slaveAck(portIndex),
|
350 |
|
|
lookupStb_o=>masterLookupStb(portIndex),
|
351 |
|
|
lookupAddr_o=>masterLookupAddr(portIndex),
|
352 |
|
|
lookupData_i=>masterLookupData(portIndex), lookupAck_i=>masterLookupAck(portIndex),
|
353 |
|
|
readFrameEmpty_i=>readFrameEmpty_i(portIndex), readFrame_o=>readFrame_o(portIndex),
|
354 |
|
|
readFrameRestart_o=>readFrameRestart_o(portIndex),
|
355 |
|
|
readFrameAborted_i=>readFrameAborted_i(portIndex),
|
356 |
|
|
readContentEmpty_i=>readContentEmpty_i(portIndex), readContent_o=>readContent_o(portIndex),
|
357 |
|
|
readContentEnd_i=>readContentEnd_i(portIndex), readContentData_i=>readContentData_i(portIndex),
|
358 |
46 |
magro732 |
writeFramePort_o=>open,
|
359 |
2 |
magro732 |
writeFrameFull_i=>writeFrameFull_i(portIndex), writeFrame_o=>writeFrame_o(portIndex),
|
360 |
|
|
writeFrameAbort_o=>writeFrameAbort_o(portIndex), writeContent_o=>writeContent_o(portIndex),
|
361 |
|
|
writeContentData_o=>writeContentData_o(portIndex));
|
362 |
|
|
end generate;
|
363 |
|
|
|
364 |
|
|
-----------------------------------------------------------------------------
|
365 |
|
|
-- Maintenance port instantiation.
|
366 |
|
|
-----------------------------------------------------------------------------
|
367 |
|
|
MaintenancePort: SwitchPortMaintenance
|
368 |
|
|
generic map(
|
369 |
|
|
SWITCH_PORTS=>SWITCH_PORTS,
|
370 |
|
|
DEVICE_IDENTITY=>DEVICE_IDENTITY,
|
371 |
|
|
DEVICE_VENDOR_IDENTITY=>DEVICE_VENDOR_IDENTITY,
|
372 |
|
|
DEVICE_REV=>DEVICE_REV,
|
373 |
|
|
ASSY_IDENTITY=>ASSY_IDENTITY,
|
374 |
|
|
ASSY_VENDOR_IDENTITY=>ASSY_VENDOR_IDENTITY,
|
375 |
|
|
ASSY_REV=>ASSY_REV)
|
376 |
|
|
port map(
|
377 |
|
|
clk=>clk, areset_n=>areset_n,
|
378 |
|
|
lookupStb_i=>slaveLookupStb, lookupAddr_i=>slaveLookupAddr,
|
379 |
|
|
lookupData_o=>slaveLookupData, lookupAck_o=>slaveLookupAck,
|
380 |
|
|
masterCyc_o=>masterCyc(SWITCH_PORTS), masterStb_o=>masterStb(SWITCH_PORTS),
|
381 |
|
|
masterWe_o=>masterWe(SWITCH_PORTS), masterAddr_o=>masterAddr(SWITCH_PORTS),
|
382 |
|
|
masterData_o=>masterDataWrite(SWITCH_PORTS),
|
383 |
|
|
masterData_i=>masterDataRead(SWITCH_PORTS), masterAck_i=>masterAck(SWITCH_PORTS),
|
384 |
|
|
slaveCyc_i=>slaveCyc(SWITCH_PORTS), slaveStb_i=>slaveStb(SWITCH_PORTS),
|
385 |
|
|
slaveWe_i=>slaveWe(SWITCH_PORTS), slaveAddr_i=>slaveAddr(SWITCH_PORTS),
|
386 |
|
|
slaveData_i=>slaveDataWrite(SWITCH_PORTS),
|
387 |
|
|
slaveData_o=>slaveDataRead(SWITCH_PORTS), slaveAck_o=>slaveAck(SWITCH_PORTS),
|
388 |
|
|
lookupStb_o=>masterLookupStb(SWITCH_PORTS),
|
389 |
|
|
lookupAddr_o=>masterLookupAddr(SWITCH_PORTS),
|
390 |
|
|
lookupData_i=>masterLookupData(SWITCH_PORTS), lookupAck_i=>masterLookupAck(SWITCH_PORTS),
|
391 |
|
|
portLinkTimeout_o=>portLinkTimeout_o,
|
392 |
|
|
linkInitialized_i=>linkInitialized_i,
|
393 |
|
|
outputPortEnable_o=>outputPortEnable_o, inputPortEnable_o=>inputPortEnable_o,
|
394 |
|
|
localAckIdWrite_o=>localAckIdWrite_o, clrOutstandingAckId_o=>clrOutstandingAckId_o,
|
395 |
|
|
inboundAckId_o=>inboundAckId_o, outstandingAckId_o=>outstandingAckId_o,
|
396 |
|
|
outboundAckId_o=>outboundAckId_o, inboundAckId_i=>inboundAckId_i,
|
397 |
|
|
outstandingAckId_i=>outstandingAckId_i, outboundAckId_i=>outboundAckId_i,
|
398 |
|
|
configStb_o=>configStb_o, configWe_o=>configWe_o, configAddr_o=>configAddr_o,
|
399 |
47 |
magro732 |
configData_o=>configData_o, configData_i=>configData_i, configAck_i=>configAck_i);
|
400 |
2 |
magro732 |
|
401 |
|
|
end architecture;
|
402 |
|
|
|
403 |
|
|
|
404 |
|
|
|
405 |
|
|
-------------------------------------------------------------------------------
|
406 |
46 |
magro732 |
-- SwitchPort.
|
407 |
2 |
magro732 |
-------------------------------------------------------------------------------
|
408 |
|
|
library ieee;
|
409 |
|
|
use ieee.std_logic_1164.all;
|
410 |
|
|
use ieee.numeric_std.all;
|
411 |
|
|
use work.rio_common.all;
|
412 |
|
|
|
413 |
|
|
|
414 |
|
|
-------------------------------------------------------------------------------
|
415 |
|
|
-- Entity for SwitchPort.
|
416 |
|
|
-------------------------------------------------------------------------------
|
417 |
|
|
entity SwitchPort is
|
418 |
|
|
generic(
|
419 |
46 |
magro732 |
MAINTENANCE_LOOKUP : boolean;
|
420 |
2 |
magro732 |
PORT_INDEX : natural);
|
421 |
|
|
port(
|
422 |
|
|
clk : in std_logic;
|
423 |
|
|
areset_n : in std_logic;
|
424 |
|
|
|
425 |
|
|
-- Master port signals.
|
426 |
|
|
-- Write frames to other ports.
|
427 |
|
|
masterCyc_o : out std_logic;
|
428 |
|
|
masterStb_o : out std_logic;
|
429 |
|
|
masterWe_o : out std_logic;
|
430 |
|
|
masterAddr_o : out std_logic_vector(9 downto 0);
|
431 |
|
|
masterData_o : out std_logic_vector(31 downto 0);
|
432 |
|
|
masterData_i : in std_logic;
|
433 |
|
|
masterAck_i : in std_logic;
|
434 |
|
|
|
435 |
|
|
-- Slave port signals.
|
436 |
|
|
-- Receives frames from other ports.
|
437 |
|
|
slaveCyc_i : in std_logic;
|
438 |
|
|
slaveStb_i : in std_logic;
|
439 |
|
|
slaveWe_i : in std_logic;
|
440 |
|
|
slaveAddr_i : in std_logic_vector(9 downto 0);
|
441 |
|
|
slaveData_i : in std_logic_vector(31 downto 0);
|
442 |
|
|
slaveData_o : out std_logic;
|
443 |
|
|
slaveAck_o : out std_logic;
|
444 |
|
|
|
445 |
|
|
-- Address-lookup interface.
|
446 |
|
|
lookupStb_o : out std_logic;
|
447 |
|
|
lookupAddr_o : out std_logic_vector(15 downto 0);
|
448 |
|
|
lookupData_i : in std_logic_vector(7 downto 0);
|
449 |
|
|
lookupAck_i : in std_logic;
|
450 |
|
|
|
451 |
|
|
-- Physical port frame buffer interface.
|
452 |
|
|
readFrameEmpty_i : in std_logic;
|
453 |
|
|
readFrame_o : out std_logic;
|
454 |
|
|
readFrameRestart_o : out std_logic;
|
455 |
|
|
readFrameAborted_i : in std_logic;
|
456 |
|
|
readContentEmpty_i : in std_logic;
|
457 |
|
|
readContent_o : out std_logic;
|
458 |
|
|
readContentEnd_i : in std_logic;
|
459 |
|
|
readContentData_i : in std_logic_vector(31 downto 0);
|
460 |
46 |
magro732 |
writeFramePort_o : out std_logic_vector(7 downto 0);
|
461 |
2 |
magro732 |
writeFrameFull_i : in std_logic;
|
462 |
|
|
writeFrame_o : out std_logic;
|
463 |
|
|
writeFrameAbort_o : out std_logic;
|
464 |
|
|
writeContent_o : out std_logic;
|
465 |
|
|
writeContentData_o : out std_logic_vector(31 downto 0));
|
466 |
|
|
end entity;
|
467 |
|
|
|
468 |
|
|
|
469 |
|
|
-------------------------------------------------------------------------------
|
470 |
|
|
-- Architecture for SwitchPort.
|
471 |
|
|
-------------------------------------------------------------------------------
|
472 |
|
|
architecture SwitchPortImpl of SwitchPort is
|
473 |
|
|
|
474 |
|
|
type MasterStateType is (STATE_IDLE,
|
475 |
|
|
STATE_WAIT_HEADER_0, STATE_READ_HEADER_0,
|
476 |
|
|
STATE_READ_PORT_LOOKUP,
|
477 |
|
|
STATE_READ_TARGET_PORT,
|
478 |
|
|
STATE_WAIT_TARGET_PORT,
|
479 |
|
|
STATE_WAIT_TARGET_WRITE,
|
480 |
|
|
STATE_WAIT_COMPLETE);
|
481 |
|
|
signal masterState : MasterStateType;
|
482 |
46 |
magro732 |
alias ftype : std_logic_vector(3 downto 0) is readContentData_i(19 downto 16);
|
483 |
|
|
alias tt : std_logic_vector(1 downto 0) is readContentData_i(21 downto 20);
|
484 |
|
|
|
485 |
2 |
magro732 |
type SlaveStateType is (STATE_IDLE, STATE_SEND_ACK);
|
486 |
|
|
signal slaveState : SlaveStateType;
|
487 |
|
|
|
488 |
|
|
begin
|
489 |
|
|
|
490 |
|
|
-----------------------------------------------------------------------------
|
491 |
|
|
-- Master interface process.
|
492 |
|
|
-----------------------------------------------------------------------------
|
493 |
|
|
Master: process(clk, areset_n)
|
494 |
|
|
begin
|
495 |
|
|
if (areset_n = '0') then
|
496 |
|
|
masterState <= STATE_IDLE;
|
497 |
|
|
|
498 |
|
|
lookupStb_o <= '0';
|
499 |
|
|
lookupAddr_o <= (others => '0');
|
500 |
|
|
|
501 |
|
|
masterCyc_o <= '0';
|
502 |
|
|
masterStb_o <= '0';
|
503 |
|
|
masterWe_o <= '0';
|
504 |
|
|
masterAddr_o <= (others => '0');
|
505 |
|
|
masterData_o <= (others => '0');
|
506 |
|
|
|
507 |
|
|
readContent_o <= '0';
|
508 |
|
|
readFrame_o <= '0';
|
509 |
|
|
readFrameRestart_o <= '0';
|
510 |
|
|
elsif (clk'event and clk = '1') then
|
511 |
|
|
readContent_o <= '0';
|
512 |
|
|
readFrame_o <= '0';
|
513 |
|
|
readFrameRestart_o <= '0';
|
514 |
|
|
|
515 |
|
|
-- REMARK: Add support for aborted frames...
|
516 |
|
|
case masterState is
|
517 |
|
|
|
518 |
|
|
when STATE_IDLE =>
|
519 |
|
|
---------------------------------------------------------------------
|
520 |
|
|
-- Wait for a new packet or content of a new packet.
|
521 |
|
|
---------------------------------------------------------------------
|
522 |
|
|
|
523 |
|
|
-- Reset bus signals.
|
524 |
|
|
masterCyc_o <= '0';
|
525 |
|
|
masterStb_o <= '0';
|
526 |
|
|
|
527 |
|
|
-- Wait for frame content to be available.
|
528 |
|
|
-- Use different signals to trigger the forwarding of packets depending
|
529 |
|
|
-- on the switch philosofy.
|
530 |
|
|
if (readFrameEmpty_i = '0') then
|
531 |
|
|
readContent_o <= '1';
|
532 |
|
|
masterState <= STATE_WAIT_HEADER_0;
|
533 |
|
|
end if;
|
534 |
|
|
|
535 |
|
|
when STATE_WAIT_HEADER_0 =>
|
536 |
|
|
---------------------------------------------------------------------
|
537 |
|
|
-- Wait for the frame buffer output to be updated.
|
538 |
|
|
---------------------------------------------------------------------
|
539 |
|
|
|
540 |
|
|
-- Wait for frame buffer output to be updated.
|
541 |
|
|
masterState <= STATE_READ_HEADER_0;
|
542 |
|
|
|
543 |
|
|
when STATE_READ_HEADER_0 =>
|
544 |
|
|
---------------------------------------------------------------------
|
545 |
|
|
-- Check the FTYPE and forward it to the maintenance port if it is a
|
546 |
|
|
-- maintenance packet. Otherwise, initiate an address lookup and wait
|
547 |
|
|
-- for the result.
|
548 |
|
|
---------------------------------------------------------------------
|
549 |
|
|
|
550 |
|
|
-- Check if the frame has ended.
|
551 |
|
|
if (readContentEnd_i = '0') then
|
552 |
|
|
-- The frame has not ended.
|
553 |
|
|
-- This word contains the header and the source id.
|
554 |
|
|
|
555 |
|
|
-- Read the tt-field to check the source and destination id size.
|
556 |
|
|
if (tt = "01") then
|
557 |
|
|
-- This frame contains 16-bit addresses.
|
558 |
|
|
|
559 |
|
|
-- Read the new content.
|
560 |
|
|
readContent_o <= '1';
|
561 |
|
|
|
562 |
|
|
-- Save the content of the header and destination.
|
563 |
|
|
masterData_o <= readContentData_i;
|
564 |
|
|
|
565 |
|
|
-- Check if this is a maintenance frame.
|
566 |
46 |
magro732 |
if ((not MAINTENANCE_LOOKUP) and (ftype = FTYPE_MAINTENANCE_CLASS)) then
|
567 |
2 |
magro732 |
-- This is a maintenance frame.
|
568 |
|
|
|
569 |
|
|
-- Always route these frames to the maintenance module in the
|
570 |
|
|
-- switch by setting the MSB bit of the port address.
|
571 |
|
|
masterAddr_o <= '1' & std_logic_vector(to_unsigned(PORT_INDEX, 8)) & '0';
|
572 |
|
|
|
573 |
|
|
-- Start an access to the maintenance port.
|
574 |
|
|
masterState <= STATE_READ_TARGET_PORT;
|
575 |
|
|
else
|
576 |
|
|
-- This is not a maintenance frame.
|
577 |
|
|
|
578 |
|
|
-- Lookup the destination address and proceed to wait for the
|
579 |
|
|
-- result.
|
580 |
|
|
lookupStb_o <= '1';
|
581 |
|
|
lookupAddr_o <= readContentData_i(15 downto 0);
|
582 |
|
|
|
583 |
|
|
-- Wait for the port lookup to return a result.
|
584 |
|
|
masterState <= STATE_READ_PORT_LOOKUP;
|
585 |
|
|
end if;
|
586 |
|
|
else
|
587 |
|
|
-- Unsupported tt-value, discard the frame.
|
588 |
|
|
readFrame_o <= '1';
|
589 |
|
|
masterState <= STATE_IDLE;
|
590 |
|
|
end if;
|
591 |
|
|
else
|
592 |
|
|
-- End of frame.
|
593 |
|
|
-- The frame is too short to contain a valid frame. Discard it.
|
594 |
|
|
readFrame_o <= '1';
|
595 |
|
|
masterState <= STATE_IDLE;
|
596 |
|
|
end if;
|
597 |
|
|
|
598 |
|
|
when STATE_READ_PORT_LOOKUP =>
|
599 |
|
|
---------------------------------------------------------------------
|
600 |
|
|
-- Wait for the address lookup to be complete.
|
601 |
|
|
---------------------------------------------------------------------
|
602 |
|
|
|
603 |
|
|
-- Wait for the routing table to complete the request.
|
604 |
|
|
if (lookupAck_i = '1') then
|
605 |
|
|
-- The address lookup is complete.
|
606 |
|
|
|
607 |
|
|
-- Terminate the lookup cycle.
|
608 |
|
|
lookupStb_o <= '0';
|
609 |
|
|
|
610 |
|
|
-- Proceed to read the target port.
|
611 |
|
|
masterAddr_o <= '0' & lookupData_i & '0';
|
612 |
|
|
masterState <= STATE_READ_TARGET_PORT;
|
613 |
|
|
else
|
614 |
|
|
-- Wait until the address lookup is complete.
|
615 |
|
|
-- REMARK: Timeout here???
|
616 |
|
|
end if;
|
617 |
|
|
|
618 |
|
|
when STATE_READ_TARGET_PORT =>
|
619 |
|
|
---------------------------------------------------------------------
|
620 |
|
|
-- Initiate an access to the target port.
|
621 |
|
|
---------------------------------------------------------------------
|
622 |
|
|
|
623 |
|
|
-- Read the status of the target port using the result from the
|
624 |
|
|
-- lookup in the routing table.
|
625 |
|
|
masterCyc_o <= '1';
|
626 |
|
|
masterStb_o <= '1';
|
627 |
|
|
masterWe_o <= '0';
|
628 |
|
|
masterState <= STATE_WAIT_TARGET_PORT;
|
629 |
|
|
|
630 |
|
|
when STATE_WAIT_TARGET_PORT =>
|
631 |
|
|
---------------------------------------------------------------------
|
632 |
|
|
-- Wait to get access to the target port. When the port is ready
|
633 |
|
|
-- check if it is ready to accept a new frame. If it cannot accept a
|
634 |
|
|
-- new frame, terminate the access and go back and start a new one.
|
635 |
|
|
-- This is to free the interconnect to let other ports access it if
|
636 |
|
|
-- it is a shared bus. If the port is ready, initiate a write access
|
637 |
|
|
-- to the selected port.
|
638 |
|
|
---------------------------------------------------------------------
|
639 |
|
|
|
640 |
|
|
-- Wait for the target port to complete the request.
|
641 |
|
|
if (masterAck_i = '1') then
|
642 |
|
|
-- Target port has completed the request.
|
643 |
|
|
|
644 |
|
|
-- Check the status of the target port.
|
645 |
|
|
if (masterData_i = '0') then
|
646 |
|
|
-- The target port has empty buffers to receive the frame.
|
647 |
|
|
|
648 |
|
|
-- Hold the bus with cyc until the cycle is complete.
|
649 |
|
|
-- Write the first word of the frame to the target port.
|
650 |
|
|
-- The masterData_o has already been assigned.
|
651 |
|
|
masterCyc_o <= '1';
|
652 |
|
|
masterStb_o <= '1';
|
653 |
|
|
masterWe_o <= '1';
|
654 |
|
|
masterAddr_o(0) <= '1';
|
655 |
|
|
|
656 |
|
|
-- Change state to transfer the frame.
|
657 |
|
|
masterState <= STATE_WAIT_TARGET_WRITE;
|
658 |
|
|
else
|
659 |
|
|
-- The target port has no empty buffer to receive the frame.
|
660 |
|
|
-- Terminate the cycle and retry later.
|
661 |
|
|
masterCyc_o <= '0';
|
662 |
|
|
masterStb_o <= '0';
|
663 |
|
|
masterState <= STATE_READ_TARGET_PORT;
|
664 |
|
|
end if;
|
665 |
|
|
else
|
666 |
|
|
-- Target port has not completed the request.
|
667 |
|
|
-- Dont to anything.
|
668 |
|
|
end if;
|
669 |
|
|
|
670 |
|
|
when STATE_WAIT_TARGET_WRITE =>
|
671 |
|
|
---------------------------------------------------------------------
|
672 |
|
|
-- Wait for the write access to complete. When complete, write the
|
673 |
|
|
-- next content and update the content to the next. If the frame does
|
674 |
|
|
-- not have any more data ready, terminate the access but keep the
|
675 |
|
|
-- cycle active and proceed to wait for new data.
|
676 |
|
|
---------------------------------------------------------------------
|
677 |
|
|
|
678 |
|
|
-- Wait for the target port to complete the request.
|
679 |
|
|
-- REMARK: Remove the ack-condition, we know that the write takes one
|
680 |
|
|
-- cycle...
|
681 |
|
|
if (masterAck_i = '1') then
|
682 |
|
|
-- The target port is ready.
|
683 |
|
|
|
684 |
|
|
-- Check if the frame has ended.
|
685 |
|
|
if (readContentEnd_i = '0') then
|
686 |
|
|
-- The frame has not ended.
|
687 |
|
|
|
688 |
|
|
-- There are more data to transfer.
|
689 |
|
|
masterData_o <= readContentData_i;
|
690 |
|
|
readContent_o <= '1';
|
691 |
|
|
else
|
692 |
|
|
-- There are no more data to transfer.
|
693 |
|
|
|
694 |
|
|
-- Update to the next frame.
|
695 |
|
|
readFrame_o <= '1';
|
696 |
|
|
|
697 |
|
|
-- Tell the target port that the frame is complete.
|
698 |
|
|
masterWe_o <= '1';
|
699 |
|
|
masterAddr_o(0) <= '0';
|
700 |
|
|
masterData_o <= x"00000001";
|
701 |
|
|
|
702 |
|
|
-- Change state to wait for the target port to finalize the write
|
703 |
|
|
-- of the full frame.
|
704 |
|
|
masterState <= STATE_WAIT_COMPLETE;
|
705 |
|
|
end if;
|
706 |
|
|
else
|
707 |
|
|
-- Wait for the target port to reply.
|
708 |
|
|
-- Dont do anything.
|
709 |
|
|
end if;
|
710 |
|
|
|
711 |
|
|
when STATE_WAIT_COMPLETE =>
|
712 |
|
|
---------------------------------------------------------------------
|
713 |
|
|
-- Wait for the target port to signal that the frame has been
|
714 |
|
|
-- completed.
|
715 |
|
|
---------------------------------------------------------------------
|
716 |
|
|
|
717 |
|
|
-- Wait for the target port to complete the final request.
|
718 |
|
|
if (masterAck_i = '1') then
|
719 |
|
|
-- The target port has finalized the write of the frame.
|
720 |
|
|
|
721 |
|
|
-- Reset master bus signals.
|
722 |
|
|
masterCyc_o <= '0';
|
723 |
|
|
masterStb_o <= '0';
|
724 |
|
|
masterState <= STATE_IDLE;
|
725 |
|
|
else
|
726 |
|
|
-- Wait for the target port to reply.
|
727 |
|
|
-- REMARK: Timeout here???
|
728 |
|
|
end if;
|
729 |
|
|
|
730 |
|
|
when others =>
|
731 |
|
|
---------------------------------------------------------------------
|
732 |
|
|
--
|
733 |
|
|
---------------------------------------------------------------------
|
734 |
|
|
end case;
|
735 |
|
|
end if;
|
736 |
|
|
end process;
|
737 |
|
|
|
738 |
|
|
-----------------------------------------------------------------------------
|
739 |
|
|
-- Slave interface process.
|
740 |
|
|
-- Addr | Read | Write
|
741 |
|
|
-- 0 | full | abort & complete
|
742 |
|
|
-- 1 | full | frameData
|
743 |
46 |
magro732 |
-----------------------------------------------------------------------------
|
744 |
2 |
magro732 |
writeContentData_o <= slaveData_i;
|
745 |
|
|
Slave: process(clk, areset_n)
|
746 |
|
|
begin
|
747 |
|
|
if (areset_n = '0') then
|
748 |
|
|
slaveState <= STATE_IDLE;
|
749 |
|
|
|
750 |
|
|
slaveData_o <= '0';
|
751 |
|
|
|
752 |
46 |
magro732 |
writeFramePort_o <= (others=>'0');
|
753 |
2 |
magro732 |
writeFrame_o <= '0';
|
754 |
|
|
writeFrameAbort_o <= '0';
|
755 |
|
|
writeContent_o <= '0';
|
756 |
|
|
elsif (clk'event and clk = '1') then
|
757 |
|
|
writeFrame_o <= '0';
|
758 |
|
|
writeFrameAbort_o <= '0';
|
759 |
|
|
writeContent_o <= '0';
|
760 |
|
|
|
761 |
|
|
case slaveState is
|
762 |
|
|
|
763 |
|
|
when STATE_IDLE =>
|
764 |
|
|
---------------------------------------------------------------------
|
765 |
|
|
-- Wait for an access from a master.
|
766 |
|
|
---------------------------------------------------------------------
|
767 |
|
|
|
768 |
|
|
-- Check if any cycle is active.
|
769 |
|
|
if ((slaveCyc_i = '1') and (slaveStb_i = '1')) then
|
770 |
|
|
-- Cycle is active.
|
771 |
|
|
|
772 |
|
|
-- Check if the cycle is accessing the status- or data address.
|
773 |
|
|
if (slaveAddr_i(0) = '0') then
|
774 |
|
|
-- Accessing port status address.
|
775 |
|
|
|
776 |
|
|
-- Check if writing.
|
777 |
|
|
if (slaveWe_i = '1') then
|
778 |
|
|
-- Writing the status address.
|
779 |
|
|
-- Update the buffering output signals according to the input
|
780 |
|
|
-- data.
|
781 |
46 |
magro732 |
writeFramePort_o <= slaveAddr_i(8 downto 1);
|
782 |
2 |
magro732 |
writeFrame_o <= slaveData_i(0);
|
783 |
|
|
writeFrameAbort_o <= slaveData_i(1);
|
784 |
|
|
else
|
785 |
|
|
-- Reading the status address.
|
786 |
|
|
slaveData_o <= writeFrameFull_i;
|
787 |
|
|
end if;
|
788 |
|
|
else
|
789 |
|
|
-- Accessing port data address.
|
790 |
|
|
|
791 |
|
|
-- Check if writing.
|
792 |
|
|
if (slaveWe_i = '1') then
|
793 |
|
|
-- Write frame content into the frame buffer.
|
794 |
|
|
writeContent_o <= '1';
|
795 |
|
|
else
|
796 |
|
|
slaveData_o <= writeFrameFull_i;
|
797 |
|
|
end if;
|
798 |
|
|
end if;
|
799 |
|
|
|
800 |
|
|
-- Change state to send an ack to the master.
|
801 |
|
|
slaveState <= STATE_SEND_ACK;
|
802 |
|
|
end if;
|
803 |
|
|
|
804 |
|
|
when STATE_SEND_ACK =>
|
805 |
|
|
---------------------------------------------------------------------
|
806 |
|
|
-- Wait for acknowledge to be received by the master.
|
807 |
|
|
---------------------------------------------------------------------
|
808 |
|
|
|
809 |
|
|
-- Go back to the idle state and wait for a new cycle.
|
810 |
|
|
slaveState <= STATE_IDLE;
|
811 |
|
|
|
812 |
|
|
when others =>
|
813 |
|
|
---------------------------------------------------------------------
|
814 |
|
|
--
|
815 |
|
|
---------------------------------------------------------------------
|
816 |
|
|
null;
|
817 |
|
|
|
818 |
|
|
end case;
|
819 |
|
|
end if;
|
820 |
|
|
end process;
|
821 |
|
|
|
822 |
|
|
-- Assign the acknowledge depending on the current slave state.
|
823 |
|
|
slaveAck_o <= '1' when (slaveState = STATE_SEND_ACK) else '0';
|
824 |
|
|
|
825 |
|
|
end architecture;
|
826 |
|
|
|
827 |
|
|
|
828 |
|
|
|
829 |
46 |
magro732 |
|
830 |
|
|
|
831 |
2 |
magro732 |
-------------------------------------------------------------------------------
|
832 |
|
|
-- SwitchPortMaintenance
|
833 |
|
|
-------------------------------------------------------------------------------
|
834 |
|
|
|
835 |
|
|
library ieee;
|
836 |
|
|
use ieee.std_logic_1164.all;
|
837 |
|
|
use ieee.numeric_std.all;
|
838 |
|
|
use work.rio_common.all;
|
839 |
|
|
|
840 |
|
|
|
841 |
|
|
-------------------------------------------------------------------------------
|
842 |
|
|
-- Entity for SwitchPortMaintenance.
|
843 |
|
|
-------------------------------------------------------------------------------
|
844 |
|
|
entity SwitchPortMaintenance is
|
845 |
|
|
generic(
|
846 |
|
|
SWITCH_PORTS : natural range 0 to 255;
|
847 |
|
|
DEVICE_IDENTITY : std_logic_vector(15 downto 0);
|
848 |
|
|
DEVICE_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
|
849 |
|
|
DEVICE_REV : std_logic_vector(31 downto 0);
|
850 |
|
|
ASSY_IDENTITY : std_logic_vector(15 downto 0);
|
851 |
|
|
ASSY_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
|
852 |
|
|
ASSY_REV : std_logic_vector(15 downto 0));
|
853 |
|
|
port(
|
854 |
|
|
clk : in std_logic;
|
855 |
|
|
areset_n : in std_logic;
|
856 |
|
|
|
857 |
|
|
-- Routing table port lookup signals.
|
858 |
|
|
lookupStb_i : in std_logic;
|
859 |
|
|
lookupAddr_i : in std_logic_vector(15 downto 0);
|
860 |
|
|
lookupData_o : out std_logic_vector(7 downto 0);
|
861 |
|
|
lookupAck_o : out std_logic;
|
862 |
|
|
|
863 |
|
|
-- Master port signals.
|
864 |
|
|
-- Write frames to other ports.
|
865 |
|
|
masterCyc_o : out std_logic;
|
866 |
|
|
masterStb_o : out std_logic;
|
867 |
|
|
masterWe_o : out std_logic;
|
868 |
|
|
masterAddr_o : out std_logic_vector(9 downto 0);
|
869 |
|
|
masterData_o : out std_logic_vector(31 downto 0);
|
870 |
|
|
masterData_i : in std_logic;
|
871 |
|
|
masterAck_i : in std_logic;
|
872 |
|
|
|
873 |
|
|
-- Slave port signals.
|
874 |
|
|
-- Receives frames from other ports.
|
875 |
|
|
slaveCyc_i : in std_logic;
|
876 |
|
|
slaveStb_i : in std_logic;
|
877 |
|
|
slaveWe_i : in std_logic;
|
878 |
|
|
slaveAddr_i : in std_logic_vector(9 downto 0);
|
879 |
|
|
slaveData_i : in std_logic_vector(31 downto 0);
|
880 |
|
|
slaveData_o : out std_logic;
|
881 |
|
|
slaveAck_o : out std_logic;
|
882 |
|
|
|
883 |
|
|
-- Address-lookup interface.
|
884 |
|
|
lookupStb_o : out std_logic;
|
885 |
|
|
lookupAddr_o : out std_logic_vector(15 downto 0);
|
886 |
|
|
lookupData_i : in std_logic_vector(7 downto 0);
|
887 |
|
|
lookupAck_i : in std_logic;
|
888 |
|
|
|
889 |
|
|
-- Port common access interface.
|
890 |
|
|
portLinkTimeout_o : out std_logic_vector(23 downto 0);
|
891 |
|
|
|
892 |
|
|
-- Port specific access interface.
|
893 |
|
|
linkInitialized_i : in Array1(SWITCH_PORTS-1 downto 0);
|
894 |
|
|
outputPortEnable_o : out Array1(SWITCH_PORTS-1 downto 0);
|
895 |
|
|
inputPortEnable_o : out Array1(SWITCH_PORTS-1 downto 0);
|
896 |
|
|
localAckIdWrite_o : out Array1(SWITCH_PORTS-1 downto 0);
|
897 |
|
|
clrOutstandingAckId_o : out Array1(SWITCH_PORTS-1 downto 0);
|
898 |
|
|
inboundAckId_o : out Array5(SWITCH_PORTS-1 downto 0);
|
899 |
|
|
outstandingAckId_o : out Array5(SWITCH_PORTS-1 downto 0);
|
900 |
|
|
outboundAckId_o : out Array5(SWITCH_PORTS-1 downto 0);
|
901 |
|
|
inboundAckId_i : in Array5(SWITCH_PORTS-1 downto 0);
|
902 |
|
|
outstandingAckId_i : in Array5(SWITCH_PORTS-1 downto 0);
|
903 |
|
|
outboundAckId_i : in Array5(SWITCH_PORTS-1 downto 0);
|
904 |
|
|
|
905 |
|
|
-- Configuration space for implementation-defined space.
|
906 |
|
|
configStb_o : out std_logic;
|
907 |
|
|
configWe_o : out std_logic;
|
908 |
|
|
configAddr_o : out std_logic_vector(23 downto 0);
|
909 |
|
|
configData_o : out std_logic_vector(31 downto 0);
|
910 |
47 |
magro732 |
configData_i : in std_logic_vector(31 downto 0);
|
911 |
|
|
configAck_i : in std_logic);
|
912 |
2 |
magro732 |
end entity;
|
913 |
|
|
|
914 |
|
|
|
915 |
|
|
-------------------------------------------------------------------------------
|
916 |
|
|
-- Architecture for SwitchPort.
|
917 |
|
|
-------------------------------------------------------------------------------
|
918 |
|
|
architecture SwitchPortMaintenanceImpl of SwitchPortMaintenance is
|
919 |
|
|
|
920 |
46 |
magro732 |
component SwitchPort is
|
921 |
2 |
magro732 |
generic(
|
922 |
46 |
magro732 |
MAINTENANCE_LOOKUP : boolean;
|
923 |
|
|
PORT_INDEX : natural);
|
924 |
2 |
magro732 |
port(
|
925 |
46 |
magro732 |
clk : in std_logic;
|
926 |
|
|
areset_n : in std_logic;
|
927 |
2 |
magro732 |
|
928 |
46 |
magro732 |
masterCyc_o : out std_logic;
|
929 |
|
|
masterStb_o : out std_logic;
|
930 |
|
|
masterWe_o : out std_logic;
|
931 |
|
|
masterAddr_o : out std_logic_vector(9 downto 0);
|
932 |
|
|
masterData_o : out std_logic_vector(31 downto 0);
|
933 |
|
|
masterData_i : in std_logic;
|
934 |
|
|
masterAck_i : in std_logic;
|
935 |
|
|
|
936 |
|
|
slaveCyc_i : in std_logic;
|
937 |
|
|
slaveStb_i : in std_logic;
|
938 |
|
|
slaveWe_i : in std_logic;
|
939 |
|
|
slaveAddr_i : in std_logic_vector(9 downto 0);
|
940 |
|
|
slaveData_i : in std_logic_vector(31 downto 0);
|
941 |
|
|
slaveData_o : out std_logic;
|
942 |
|
|
slaveAck_o : out std_logic;
|
943 |
|
|
|
944 |
|
|
lookupStb_o : out std_logic;
|
945 |
|
|
lookupAddr_o : out std_logic_vector(15 downto 0);
|
946 |
|
|
lookupData_i : in std_logic_vector(7 downto 0);
|
947 |
|
|
lookupAck_i : in std_logic;
|
948 |
|
|
|
949 |
|
|
readFrameEmpty_i : in std_logic;
|
950 |
|
|
readFrame_o : out std_logic;
|
951 |
|
|
readFrameRestart_o : out std_logic;
|
952 |
|
|
readFrameAborted_i : in std_logic;
|
953 |
|
|
readContentEmpty_i : in std_logic;
|
954 |
|
|
readContent_o : out std_logic;
|
955 |
|
|
readContentEnd_i : in std_logic;
|
956 |
|
|
readContentData_i : in std_logic_vector(31 downto 0);
|
957 |
|
|
writeFramePort_o : out std_logic_vector(7 downto 0);
|
958 |
|
|
writeFrameFull_i : in std_logic;
|
959 |
|
|
writeFrame_o : out std_logic;
|
960 |
|
|
writeFrameAbort_o : out std_logic;
|
961 |
|
|
writeContent_o : out std_logic;
|
962 |
|
|
writeContentData_o : out std_logic_vector(31 downto 0));
|
963 |
2 |
magro732 |
end component;
|
964 |
46 |
magro732 |
|
965 |
|
|
-----------------------------------------------------------------------------
|
966 |
|
|
-- Signals between the port and the packet-queue.
|
967 |
|
|
-----------------------------------------------------------------------------
|
968 |
2 |
magro732 |
|
969 |
47 |
magro732 |
signal outboundFramePort, outboundFramePort0 : std_logic_vector(7 downto 0);
|
970 |
46 |
magro732 |
signal outboundReadFrameEmpty : std_logic;
|
971 |
|
|
signal outboundReadFrame : std_logic;
|
972 |
|
|
signal outboundReadContent : std_logic;
|
973 |
|
|
signal outboundReadContentEnd : std_logic;
|
974 |
|
|
signal outboundReadContentData : std_logic_vector(31 downto 0);
|
975 |
47 |
magro732 |
signal inboundFramePort, inboundFramePort0 : std_logic_vector(7 downto 0);
|
976 |
46 |
magro732 |
signal inboundWriteFrameFull : std_logic;
|
977 |
|
|
signal inboundWriteFrame : std_logic;
|
978 |
|
|
signal inboundWriteFrameAbort : std_logic;
|
979 |
|
|
signal inboundWriteContent : std_logic;
|
980 |
|
|
signal inboundWriteContentData : std_logic_vector(31 downto 0);
|
981 |
2 |
magro732 |
|
982 |
46 |
magro732 |
-----------------------------------------------------------------------------
|
983 |
|
|
-- Signals between the packet-queue and RioLogicalCommon.
|
984 |
|
|
-----------------------------------------------------------------------------
|
985 |
2 |
magro732 |
|
986 |
46 |
magro732 |
signal inboundReadFrameEmpty : std_logic;
|
987 |
|
|
signal inboundReadFrame : std_logic;
|
988 |
|
|
signal inboundReadContent : std_logic;
|
989 |
|
|
signal inboundReadContentEnd : std_logic;
|
990 |
|
|
signal inboundReadContentData : std_logic_vector(31 downto 0);
|
991 |
|
|
signal outboundWriteFrameFull : std_logic;
|
992 |
|
|
signal outboundWriteFrame : std_logic;
|
993 |
|
|
signal outboundWriteFrameAbort : std_logic;
|
994 |
|
|
signal outboundWriteContent : std_logic;
|
995 |
|
|
signal outboundWriteContentData : std_logic_vector(31 downto 0);
|
996 |
2 |
magro732 |
|
997 |
46 |
magro732 |
-----------------------------------------------------------------------------
|
998 |
|
|
-- Signals between RioLogicalCommon and PacketHandler.
|
999 |
|
|
-----------------------------------------------------------------------------
|
1000 |
2 |
magro732 |
|
1001 |
46 |
magro732 |
signal inboundCyc : std_logic;
|
1002 |
|
|
signal inboundStb : std_logic;
|
1003 |
|
|
signal inboundAdr : std_logic_vector(7 downto 0);
|
1004 |
|
|
signal inboundDat : std_logic_vector(31 downto 0);
|
1005 |
|
|
signal inboundAck : std_logic;
|
1006 |
|
|
signal outboundCyc : std_logic_vector(0 downto 0);
|
1007 |
|
|
signal outboundStb : std_logic_vector(0 downto 0);
|
1008 |
|
|
signal outboundDat : std_logic_vector(31 downto 0);
|
1009 |
|
|
signal outboundAck : std_logic_vector(0 downto 0);
|
1010 |
2 |
magro732 |
|
1011 |
46 |
magro732 |
-----------------------------------------------------------------------------
|
1012 |
|
|
-- Signals between PacketHandlers and maintenance controllers.
|
1013 |
|
|
-----------------------------------------------------------------------------
|
1014 |
2 |
magro732 |
|
1015 |
|
|
signal vc : std_logic;
|
1016 |
|
|
signal crf : std_logic;
|
1017 |
|
|
signal prio : std_logic_vector(1 downto 0);
|
1018 |
|
|
signal tt : std_logic_vector(1 downto 0);
|
1019 |
46 |
magro732 |
signal tid : std_logic_vector(7 downto 0);
|
1020 |
47 |
magro732 |
signal status : std_logic_vector(3 downto 0);
|
1021 |
2 |
magro732 |
|
1022 |
46 |
magro732 |
signal readRequestInbound : std_logic;
|
1023 |
|
|
signal writeRequestInbound : std_logic;
|
1024 |
|
|
signal readResponseInbound : std_logic;
|
1025 |
|
|
signal writeResponseInbound : std_logic;
|
1026 |
|
|
signal portWriteInbound : std_logic;
|
1027 |
|
|
signal dstIdInbound : std_logic_vector(31 downto 0);
|
1028 |
|
|
signal srcIdInbound : std_logic_vector(31 downto 0);
|
1029 |
47 |
magro732 |
signal sizeInbound : std_logic_vector(3 downto 0);
|
1030 |
|
|
signal statusInbound : std_logic_vector(3 downto 0);
|
1031 |
46 |
magro732 |
signal hopInbound : std_logic_vector(7 downto 0);
|
1032 |
|
|
signal offsetInbound : std_logic_vector(20 downto 0);
|
1033 |
|
|
signal wdptrInbound: std_logic;
|
1034 |
47 |
magro732 |
signal payloadLengthInbound : std_logic_vector(2 downto 0);
|
1035 |
|
|
signal payloadIndexInbound : std_logic_vector(2 downto 0);
|
1036 |
|
|
signal payloadInbound : std_logic_vector(63 downto 0);
|
1037 |
46 |
magro732 |
signal doneInbound : std_logic;
|
1038 |
|
|
|
1039 |
|
|
signal readRequestOutbound : std_logic;
|
1040 |
|
|
signal writeRequestOutbound : std_logic;
|
1041 |
|
|
signal readResponseOutbound : std_logic;
|
1042 |
|
|
signal writeResponseOutbound : std_logic;
|
1043 |
|
|
signal portWriteOutbound : std_logic;
|
1044 |
|
|
signal dstIdOutbound : std_logic_vector(31 downto 0);
|
1045 |
|
|
signal srcIdOutbound : std_logic_vector(31 downto 0);
|
1046 |
47 |
magro732 |
signal statusOutbound : std_logic_vector(3 downto 0);
|
1047 |
46 |
magro732 |
signal hopOutbound : std_logic_vector(7 downto 0);
|
1048 |
47 |
magro732 |
signal payloadLengthOutbound : std_logic_vector(2 downto 0);
|
1049 |
|
|
signal payloadIndexOutbound : std_logic_vector(2 downto 0);
|
1050 |
|
|
signal payloadOutbound : std_logic_vector(63 downto 0);
|
1051 |
46 |
magro732 |
signal doneOutbound : std_logic;
|
1052 |
|
|
|
1053 |
|
|
signal readRequestMaint : std_logic;
|
1054 |
|
|
signal writeRequestMaint : std_logic;
|
1055 |
|
|
signal readResponseMaint : std_logic;
|
1056 |
|
|
signal writeResponseMaint : std_logic;
|
1057 |
47 |
magro732 |
signal statusMaint : std_logic_vector(3 downto 0);
|
1058 |
|
|
signal payloadLengthMaint : std_logic_vector(2 downto 0);
|
1059 |
|
|
signal payloadIndexMaint : std_logic_vector(2 downto 0);
|
1060 |
|
|
signal payloadMaint : std_logic_vector(63 downto 0);
|
1061 |
46 |
magro732 |
signal doneMaint : std_logic;
|
1062 |
|
|
|
1063 |
2 |
magro732 |
-----------------------------------------------------------------------------
|
1064 |
46 |
magro732 |
--
|
1065 |
|
|
-----------------------------------------------------------------------------
|
1066 |
|
|
|
1067 |
|
|
signal sendPacket : std_logic;
|
1068 |
|
|
signal forwardPacket : std_logic;
|
1069 |
|
|
|
1070 |
|
|
-----------------------------------------------------------------------------
|
1071 |
2 |
magro732 |
-- Route table access signals.
|
1072 |
|
|
-----------------------------------------------------------------------------
|
1073 |
|
|
|
1074 |
|
|
signal lookupEnable : std_logic;
|
1075 |
|
|
signal lookupAddress : std_logic_vector(10 downto 0);
|
1076 |
|
|
signal lookupData : std_logic_vector(7 downto 0);
|
1077 |
|
|
signal lookupAck : std_logic;
|
1078 |
|
|
|
1079 |
|
|
signal routeTableEnable : std_logic;
|
1080 |
|
|
signal routeTableWrite : std_logic;
|
1081 |
|
|
signal routeTableAddress : std_logic_vector(10 downto 0);
|
1082 |
|
|
signal routeTablePortWrite : std_logic_vector(7 downto 0);
|
1083 |
|
|
signal routeTablePortRead : std_logic_vector(7 downto 0);
|
1084 |
|
|
|
1085 |
|
|
signal routeTablePortDefault : std_logic_vector(7 downto 0);
|
1086 |
|
|
|
1087 |
|
|
-----------------------------------------------------------------------------
|
1088 |
|
|
-- Configuration space signals.
|
1089 |
|
|
-----------------------------------------------------------------------------
|
1090 |
46 |
magro732 |
|
1091 |
47 |
magro732 |
signal configStb, configStbInternal : std_logic;
|
1092 |
46 |
magro732 |
signal configWe : std_logic;
|
1093 |
|
|
signal configAdr : std_logic_vector(23 downto 0);
|
1094 |
|
|
signal configDataWrite : std_logic_vector(31 downto 0);
|
1095 |
|
|
signal configDataRead, configDataReadInternal : std_logic_vector(31 downto 0);
|
1096 |
47 |
magro732 |
signal configAck, configAckInternal : std_logic;
|
1097 |
46 |
magro732 |
|
1098 |
|
|
-- REMARK: Make these variables instead...
|
1099 |
2 |
magro732 |
signal discovered : std_logic;
|
1100 |
|
|
signal hostBaseDeviceIdLocked : std_logic;
|
1101 |
|
|
signal hostBaseDeviceId : std_logic_vector(15 downto 0);
|
1102 |
|
|
signal componentTag : std_logic_vector(31 downto 0);
|
1103 |
|
|
signal portLinkTimeout : std_logic_vector(23 downto 0);
|
1104 |
|
|
signal outputPortEnable : Array1(SWITCH_PORTS-1 downto 0);
|
1105 |
|
|
signal inputPortEnable : Array1(SWITCH_PORTS-1 downto 0);
|
1106 |
|
|
|
1107 |
|
|
begin
|
1108 |
|
|
|
1109 |
|
|
-----------------------------------------------------------------------------
|
1110 |
46 |
magro732 |
-- Normal switch port instance interfacing the switch interconnect.
|
1111 |
2 |
magro732 |
-----------------------------------------------------------------------------
|
1112 |
46 |
magro732 |
-- REMARK: PORT_INDEX is not used in this instantiation.
|
1113 |
|
|
-- REMARK: Add generic to disable the maintenance routing to this port...
|
1114 |
|
|
PortInst: SwitchPort
|
1115 |
2 |
magro732 |
generic map(
|
1116 |
46 |
magro732 |
MAINTENANCE_LOOKUP=>true,
|
1117 |
|
|
PORT_INDEX=>0)
|
1118 |
2 |
magro732 |
port map(
|
1119 |
46 |
magro732 |
clk=>clk, areset_n=>areset_n,
|
1120 |
|
|
masterCyc_o=>masterCyc_o,
|
1121 |
|
|
masterStb_o=>masterStb_o,
|
1122 |
|
|
masterWe_o=>masterWe_o,
|
1123 |
|
|
masterAddr_o=>masterAddr_o,
|
1124 |
|
|
masterData_o=>masterData_o,
|
1125 |
|
|
masterData_i=>masterData_i,
|
1126 |
|
|
masterAck_i=>masterAck_i,
|
1127 |
|
|
slaveCyc_i=>slaveCyc_i,
|
1128 |
|
|
slaveStb_i=>slaveStb_i,
|
1129 |
|
|
slaveWe_i=>slaveWe_i,
|
1130 |
|
|
slaveAddr_i=>slaveAddr_i,
|
1131 |
|
|
slaveData_i=>slaveData_i,
|
1132 |
|
|
slaveData_o=>slaveData_o,
|
1133 |
|
|
slaveAck_o=>slaveAck_o,
|
1134 |
|
|
lookupStb_o=>open,
|
1135 |
|
|
lookupAddr_o=>open,
|
1136 |
47 |
magro732 |
lookupData_i=>outboundFramePort0,
|
1137 |
46 |
magro732 |
lookupAck_i=>'1',
|
1138 |
|
|
readFrameEmpty_i=>outboundReadFrameEmpty,
|
1139 |
|
|
readFrame_o=>outboundReadFrame,
|
1140 |
|
|
readFrameRestart_o=>open,
|
1141 |
|
|
readFrameAborted_i=>'0',
|
1142 |
|
|
readContentEmpty_i=>'0',
|
1143 |
|
|
readContent_o=>outboundReadContent,
|
1144 |
|
|
readContentEnd_i=>outboundReadContentEnd,
|
1145 |
|
|
readContentData_i=>outboundReadContentData,
|
1146 |
47 |
magro732 |
writeFramePort_o=>inboundFramePort0,
|
1147 |
46 |
magro732 |
writeFrameFull_i=>inboundWriteFrameFull,
|
1148 |
|
|
writeFrame_o=>inboundWriteFrame,
|
1149 |
|
|
writeFrameAbort_o=>inboundWriteFrameAbort,
|
1150 |
|
|
writeContent_o=>inboundWriteContent,
|
1151 |
|
|
writeContentData_o=>inboundWriteContentData);
|
1152 |
|
|
|
1153 |
47 |
magro732 |
process(clk)
|
1154 |
|
|
begin
|
1155 |
|
|
if (clk'event and clk = '1') then
|
1156 |
|
|
if (inboundReadFrame = '1') then
|
1157 |
|
|
inboundFramePort <= inboundFramePort0;
|
1158 |
|
|
end if;
|
1159 |
|
|
if (outboundWriteFrame = '1') then
|
1160 |
|
|
outboundFramePort0 <= outboundFramePort;
|
1161 |
|
|
end if;
|
1162 |
|
|
end if;
|
1163 |
|
|
end process;
|
1164 |
|
|
|
1165 |
46 |
magro732 |
-----------------------------------------------------------------------------
|
1166 |
|
|
-- Packet queue.
|
1167 |
|
|
-- This queue should only contain one packet.
|
1168 |
|
|
-----------------------------------------------------------------------------
|
1169 |
|
|
-- REMARK: Use a packet-buffer with a configurable maximum sized packet...
|
1170 |
47 |
magro732 |
-- the size of the memory is too large...
|
1171 |
46 |
magro732 |
PacketQueue: RioPacketBuffer
|
1172 |
|
|
generic map(SIZE_ADDRESS_WIDTH=>1, CONTENT_ADDRESS_WIDTH=>7)
|
1173 |
|
|
port map(
|
1174 |
|
|
clk=>clk, areset_n=>areset_n,
|
1175 |
|
|
inboundWriteFrameFull_o=>inboundWriteFrameFull,
|
1176 |
|
|
inboundWriteFrame_i=>inboundWriteFrame,
|
1177 |
|
|
inboundWriteFrameAbort_i=>inboundWriteFrameAbort,
|
1178 |
|
|
inboundWriteContent_i=>inboundWriteContent,
|
1179 |
|
|
inboundWriteContentData_i=>inboundWriteContentData,
|
1180 |
|
|
inboundReadFrameEmpty_o=>inboundReadFrameEmpty,
|
1181 |
|
|
inboundReadFrame_i=>inboundReadFrame,
|
1182 |
|
|
inboundReadFrameRestart_i=>'0',
|
1183 |
|
|
inboundReadFrameAborted_o=>open,
|
1184 |
|
|
inboundReadContentEmpty_o=>open,
|
1185 |
|
|
inboundReadContent_i=>inboundReadContent,
|
1186 |
|
|
inboundReadContentEnd_o=>inboundReadContentEnd,
|
1187 |
|
|
inboundReadContentData_o=>inboundReadContentData,
|
1188 |
|
|
outboundWriteFrameFull_o=>outboundWriteFrameFull,
|
1189 |
|
|
outboundWriteFrame_i=>outboundWriteFrame,
|
1190 |
|
|
outboundWriteFrameAbort_i=>outboundWriteFrameAbort,
|
1191 |
|
|
outboundWriteContent_i=>outboundWriteContent,
|
1192 |
|
|
outboundWriteContentData_i=>outboundWriteContentData,
|
1193 |
|
|
outboundReadFrameEmpty_o=>outboundReadFrameEmpty,
|
1194 |
|
|
outboundReadFrame_i=>outboundReadFrame,
|
1195 |
|
|
outboundReadFrameRestart_i=>'0',
|
1196 |
|
|
outboundReadFrameAborted_o=>open,
|
1197 |
|
|
outboundReadContentEmpty_o=>open,
|
1198 |
|
|
outboundReadContent_i=>outboundReadContent,
|
1199 |
|
|
outboundReadContentEnd_o=>outboundReadContentEnd,
|
1200 |
|
|
outboundReadContentData_o=>outboundReadContentData);
|
1201 |
2 |
magro732 |
|
1202 |
|
|
-----------------------------------------------------------------------------
|
1203 |
46 |
magro732 |
-- Logical common packet parser.
|
1204 |
|
|
-- This module removes CRC and unpack addresses in the inbound direction and
|
1205 |
|
|
-- adds CRC and packs addresses in the outbound direction.
|
1206 |
2 |
magro732 |
-----------------------------------------------------------------------------
|
1207 |
46 |
magro732 |
LogicalCommon: RioLogicalCommon
|
1208 |
|
|
generic map(PORTS=>1)
|
1209 |
|
|
port map(
|
1210 |
|
|
clk=>clk, areset_n=>areset_n, enable=>'1',
|
1211 |
|
|
readFrameEmpty_i=>inboundReadFrameEmpty,
|
1212 |
|
|
readFrame_o=>inboundReadFrame,
|
1213 |
|
|
readContent_o=>inboundReadContent,
|
1214 |
|
|
readContentEnd_i=>inboundReadContentEnd,
|
1215 |
|
|
readContentData_i=>inboundReadContentData,
|
1216 |
|
|
writeFrameFull_i=>outboundWriteFrameFull,
|
1217 |
|
|
writeFrame_o=>outboundWriteFrame,
|
1218 |
|
|
writeFrameAbort_o=>outboundWriteFrameAbort,
|
1219 |
|
|
writeContent_o=>outboundWriteContent,
|
1220 |
|
|
writeContentData_o=>outboundWriteContentData,
|
1221 |
|
|
inboundCyc_o=>inboundCyc,
|
1222 |
|
|
inboundStb_o=>inboundStb,
|
1223 |
|
|
inboundAdr_o=>inboundAdr,
|
1224 |
|
|
inboundDat_o=>inboundDat,
|
1225 |
|
|
inboundAck_i=>inboundAck,
|
1226 |
|
|
outboundCyc_i=>outboundCyc,
|
1227 |
|
|
outboundStb_i=>outboundStb,
|
1228 |
|
|
outboundDat_i=>outboundDat,
|
1229 |
|
|
outboundAck_o=>outboundAck);
|
1230 |
2 |
magro732 |
|
1231 |
46 |
magro732 |
-----------------------------------------------------------------------------
|
1232 |
|
|
-- Inbound maintenance packet parser.
|
1233 |
|
|
-- Unpack inbound maintenance packets.
|
1234 |
|
|
-----------------------------------------------------------------------------
|
1235 |
|
|
-- REMARK: add another receiver that discards all other packet types...
|
1236 |
|
|
-- REMARK: Connect enable to something...
|
1237 |
|
|
payloadIndexInbound <= payloadIndexOutbound when (forwardPacket = '1') else payloadIndexMaint;
|
1238 |
|
|
doneInbound <= doneOutbound when (forwardPacket = '1') else doneMaint;
|
1239 |
|
|
InboundPacket: MaintenanceInbound
|
1240 |
2 |
magro732 |
port map(
|
1241 |
46 |
magro732 |
clk=>clk, areset_n=>areset_n, enable=>'1',
|
1242 |
|
|
readRequestReady_o=>readRequestInbound,
|
1243 |
|
|
writeRequestReady_o=>writeRequestInbound,
|
1244 |
|
|
readResponseReady_o=>readResponseInbound,
|
1245 |
|
|
writeResponseReady_o=>writeResponseInbound,
|
1246 |
|
|
portWriteReady_o=>portWriteInbound,
|
1247 |
|
|
vc_o=>vc,
|
1248 |
|
|
crf_o=>crf,
|
1249 |
|
|
prio_o=>prio,
|
1250 |
|
|
tt_o=>tt,
|
1251 |
|
|
dstid_o=>dstIdInbound,
|
1252 |
|
|
srcid_o=>srcIdInbound,
|
1253 |
47 |
magro732 |
size_o=>sizeInbound,
|
1254 |
|
|
status_o=>statusInbound,
|
1255 |
46 |
magro732 |
tid_o=>tid,
|
1256 |
|
|
hop_o=>hopInbound,
|
1257 |
|
|
offset_o=>offsetInbound,
|
1258 |
|
|
wdptr_o=>wdptrInbound,
|
1259 |
|
|
payloadLength_o=>payloadLengthInbound,
|
1260 |
|
|
payloadIndex_i=>payloadIndexInbound,
|
1261 |
|
|
payload_o=>payloadInbound,
|
1262 |
|
|
done_i=>doneInbound,
|
1263 |
|
|
inboundCyc_i=>inboundCyc,
|
1264 |
|
|
inboundStb_i=>inboundStb,
|
1265 |
|
|
inboundAdr_i=>inboundAdr,
|
1266 |
|
|
inboundDat_i=>inboundDat,
|
1267 |
|
|
inboundAck_o=>inboundAck);
|
1268 |
|
|
|
1269 |
|
|
-----------------------------------------------------------------------------
|
1270 |
|
|
-- Outbound maintenance packet generator.
|
1271 |
|
|
-----------------------------------------------------------------------------
|
1272 |
|
|
readRequestOutbound <= (readRequestInbound and sendPacket) when (forwardPacket = '1') else '0';
|
1273 |
|
|
writeRequestOutbound <= (writeRequestInbound and sendPacket) when (forwardPacket = '1') else '0';
|
1274 |
|
|
readResponseOutbound <= (readResponseInbound and sendPacket) when (forwardPacket = '1') else readResponseMaint;
|
1275 |
|
|
writeResponseOutbound <= (writeResponseInbound and sendPacket) when (forwardPacket = '1') else writeResponseMaint;
|
1276 |
|
|
portWriteOutbound <= (portWriteInbound and sendPacket) when (forwardPacket = '1') else '0';
|
1277 |
|
|
srcIdOutbound <= srcIdInbound when (forwardPacket = '1') else dstIdInbound;
|
1278 |
|
|
dstIdOutbound <= dstIdInbound when (forwardPacket = '1') else srcIdInbound;
|
1279 |
47 |
magro732 |
statusOutbound <= statusInbound when (forwardPacket = '1') else statusMaint;
|
1280 |
46 |
magro732 |
hopOutbound <= std_logic_vector(unsigned(hopInbound)-1) when (forwardPacket = '1') else x"ff";
|
1281 |
|
|
payloadLengthOutbound <= payloadLengthInbound when (forwardPacket = '1') else payloadLengthMaint;
|
1282 |
|
|
payloadOutbound <= payloadInbound when (forwardPacket = '1') else payloadMaint;
|
1283 |
|
|
-- REMARK: Connect enable to something...
|
1284 |
|
|
OutboundPacket: MaintenanceOutbound
|
1285 |
2 |
magro732 |
port map(
|
1286 |
46 |
magro732 |
clk=>clk, areset_n=>areset_n, enable=>'1',
|
1287 |
|
|
readRequestReady_i=>readRequestOutbound,
|
1288 |
|
|
writeRequestReady_i=>writeRequestOutbound,
|
1289 |
|
|
readResponseReady_i=>readResponseOutbound,
|
1290 |
|
|
writeResponseReady_i=>writeResponseOutbound,
|
1291 |
|
|
portWriteReady_i=>portWriteOutbound,
|
1292 |
|
|
vc_i=>vc,
|
1293 |
|
|
crf_i=>crf,
|
1294 |
|
|
prio_i=>prio,
|
1295 |
|
|
tt_i=>tt,
|
1296 |
|
|
dstid_i=>dstIdOutbound,
|
1297 |
|
|
srcid_i=>srcIdOutbound,
|
1298 |
47 |
magro732 |
size_i=>sizeInbound,
|
1299 |
|
|
status_i=>statusOutbound,
|
1300 |
46 |
magro732 |
tid_i=>tid,
|
1301 |
|
|
hop_i=>hopOutbound,
|
1302 |
|
|
offset_i=>offsetInbound,
|
1303 |
47 |
magro732 |
wdptr_i=>wdptrInbound,
|
1304 |
46 |
magro732 |
payloadLength_i=>payloadLengthOutbound,
|
1305 |
|
|
payloadIndex_o=>payloadIndexOutbound,
|
1306 |
|
|
payload_i=>payloadOutbound,
|
1307 |
|
|
done_o=>doneOutbound,
|
1308 |
|
|
outboundCyc_o=>outboundCyc(0),
|
1309 |
|
|
outboundStb_o=>outboundStb(0),
|
1310 |
|
|
outboundDat_o=>outboundDat,
|
1311 |
|
|
outboundAck_i=>outboundAck(0));
|
1312 |
|
|
|
1313 |
2 |
magro732 |
-----------------------------------------------------------------------------
|
1314 |
46 |
magro732 |
-- Main switch maintenance controller.
|
1315 |
|
|
-- This controller decides when to forward packets and when to consume and
|
1316 |
|
|
-- produce responses instead.
|
1317 |
|
|
-- It also determines when portWrite-packets are allowed to be sent.
|
1318 |
2 |
magro732 |
-----------------------------------------------------------------------------
|
1319 |
46 |
magro732 |
RioSwitchMaintenance: process(clk, areset_n)
|
1320 |
|
|
type MasterStateType is (STATE_IDLE,
|
1321 |
|
|
STATE_START_PORT_LOOKUP,
|
1322 |
|
|
STATE_READ_PORT_LOOKUP,
|
1323 |
|
|
STATE_WAIT_COMPLETE);
|
1324 |
|
|
variable masterState : MasterStateType;
|
1325 |
2 |
magro732 |
begin
|
1326 |
|
|
if (areset_n = '0') then
|
1327 |
46 |
magro732 |
masterState := STATE_IDLE;
|
1328 |
2 |
magro732 |
|
1329 |
46 |
magro732 |
sendPacket <= '0';
|
1330 |
|
|
forwardPacket <= '0';
|
1331 |
|
|
outboundFramePort <= (others=>'0');
|
1332 |
|
|
|
1333 |
2 |
magro732 |
lookupStb_o <= '0';
|
1334 |
|
|
lookupAddr_o <= (others => '0');
|
1335 |
|
|
elsif (clk'event and clk = '1') then
|
1336 |
|
|
case masterState is
|
1337 |
|
|
|
1338 |
|
|
when STATE_IDLE =>
|
1339 |
|
|
---------------------------------------------------------------------
|
1340 |
|
|
--
|
1341 |
|
|
---------------------------------------------------------------------
|
1342 |
46 |
magro732 |
-- Wait for frame to be available.
|
1343 |
|
|
-- REMARK: Discard erronous frames.
|
1344 |
|
|
sendPacket <= '0';
|
1345 |
|
|
if (((readRequestInbound = '1') or (writeRequestInbound = '1')) and (hopInbound = x"00")) then
|
1346 |
|
|
masterState := STATE_WAIT_COMPLETE;
|
1347 |
|
|
forwardPacket <= '0';
|
1348 |
|
|
outboundFramePort <= inboundFramePort;
|
1349 |
|
|
elsif (((readResponseInbound = '1') or ((readRequestInbound = '1') and (hopInbound /= x"00"))) or
|
1350 |
|
|
((writeResponseInbound = '1') or ((writeRequestInbound = '1') and (hopInbound /= x"00"))) or
|
1351 |
|
|
(portWriteInbound = '1')) then
|
1352 |
|
|
masterState := STATE_START_PORT_LOOKUP;
|
1353 |
|
|
forwardPacket <= '1';
|
1354 |
2 |
magro732 |
end if;
|
1355 |
|
|
|
1356 |
|
|
when STATE_START_PORT_LOOKUP =>
|
1357 |
|
|
---------------------------------------------------------------------
|
1358 |
|
|
--
|
1359 |
|
|
---------------------------------------------------------------------
|
1360 |
|
|
|
1361 |
|
|
-- Initiate a port-lookup of the destination address.
|
1362 |
|
|
lookupStb_o <= '1';
|
1363 |
46 |
magro732 |
lookupAddr_o <= dstIdInbound(15 downto 0);
|
1364 |
|
|
masterState := STATE_READ_PORT_LOOKUP;
|
1365 |
2 |
magro732 |
|
1366 |
|
|
when STATE_READ_PORT_LOOKUP =>
|
1367 |
|
|
---------------------------------------------------------------------
|
1368 |
|
|
--
|
1369 |
|
|
---------------------------------------------------------------------
|
1370 |
|
|
|
1371 |
|
|
-- Wait for the routing table to complete the request.
|
1372 |
|
|
if (lookupAck_i = '1') then
|
1373 |
|
|
-- The address lookup is complete.
|
1374 |
|
|
|
1375 |
|
|
-- Terminate the lookup cycle.
|
1376 |
|
|
lookupStb_o <= '0';
|
1377 |
|
|
|
1378 |
|
|
-- Wait for the target port to reply.
|
1379 |
46 |
magro732 |
outboundFramePort <= lookupData_i;
|
1380 |
|
|
masterState := STATE_WAIT_COMPLETE;
|
1381 |
2 |
magro732 |
else
|
1382 |
|
|
-- Wait until the address lookup is complete.
|
1383 |
|
|
-- REMARK: Timeout here???
|
1384 |
|
|
end if;
|
1385 |
|
|
|
1386 |
|
|
when STATE_WAIT_COMPLETE =>
|
1387 |
|
|
---------------------------------------------------------------------
|
1388 |
|
|
--
|
1389 |
|
|
---------------------------------------------------------------------
|
1390 |
46 |
magro732 |
-- REMARK: Wait for the packet to be fully transmitted to the target
|
1391 |
|
|
-- port. Then reset everything for the reception of a new packet.
|
1392 |
|
|
sendPacket <= '1';
|
1393 |
47 |
magro732 |
if (doneInbound = '1') then
|
1394 |
46 |
magro732 |
masterState := STATE_IDLE;
|
1395 |
2 |
magro732 |
end if;
|
1396 |
|
|
|
1397 |
|
|
when others =>
|
1398 |
|
|
---------------------------------------------------------------------
|
1399 |
|
|
--
|
1400 |
|
|
---------------------------------------------------------------------
|
1401 |
|
|
end case;
|
1402 |
|
|
end if;
|
1403 |
|
|
end process;
|
1404 |
|
|
|
1405 |
|
|
-----------------------------------------------------------------------------
|
1406 |
46 |
magro732 |
-- Bridge between the inbound RapidIO maintenance packets to the internal
|
1407 |
|
|
-- config-space bus.
|
1408 |
2 |
magro732 |
-----------------------------------------------------------------------------
|
1409 |
46 |
magro732 |
-- REMARK: Connect enable...
|
1410 |
|
|
readRequestMaint <= (readRequestInbound and sendPacket) when (forwardPacket = '0') else '0';
|
1411 |
|
|
writeRequestMaint <= (writeRequestInbound and sendPacket) when (forwardPacket = '0') else '0';
|
1412 |
|
|
MaintenanceBridge: RioLogicalMaintenance
|
1413 |
2 |
magro732 |
port map(
|
1414 |
46 |
magro732 |
clk=>clk, areset_n=>areset_n, enable=>'1',
|
1415 |
|
|
readRequestReady_i=>readRequestMaint,
|
1416 |
47 |
magro732 |
writeRequestReady_i=>writeRequestMaint,
|
1417 |
|
|
size_i=>sizeInbound,
|
1418 |
46 |
magro732 |
offset_i=>offsetInbound,
|
1419 |
|
|
wdptr_i=>wdptrInbound,
|
1420 |
|
|
payloadLength_i=>payloadLengthInbound,
|
1421 |
|
|
payloadIndex_o=>payloadIndexMaint,
|
1422 |
|
|
payload_i=>payloadInbound,
|
1423 |
|
|
done_o=>doneMaint,
|
1424 |
|
|
readResponseReady_o=>readResponseMaint,
|
1425 |
47 |
magro732 |
writeResponseReady_o=>writeResponseMaint,
|
1426 |
|
|
status_o=>statusMaint,
|
1427 |
46 |
magro732 |
payloadLength_o=>payloadLengthMaint,
|
1428 |
|
|
payloadIndex_i=>payloadIndexOutbound,
|
1429 |
|
|
payload_o=>payloadMaint,
|
1430 |
|
|
done_i=>doneOutbound,
|
1431 |
|
|
configStb_o=>configStb,
|
1432 |
|
|
configWe_o=>configWe,
|
1433 |
|
|
configAdr_o=>configAdr(23 downto 2),
|
1434 |
|
|
configDat_o=>configDataWrite,
|
1435 |
|
|
configDat_i=>configDataRead,
|
1436 |
|
|
configAck_i=>configAck);
|
1437 |
|
|
configAdr(1 downto 0) <= "00";
|
1438 |
2 |
magro732 |
|
1439 |
|
|
-----------------------------------------------------------------------------
|
1440 |
46 |
magro732 |
-- Switch configuration memory.
|
1441 |
2 |
magro732 |
-----------------------------------------------------------------------------
|
1442 |
|
|
portLinkTimeout_o <= portLinkTimeout;
|
1443 |
|
|
outputPortEnable_o <= outputPortEnable;
|
1444 |
|
|
inputPortEnable_o <= inputPortEnable;
|
1445 |
46 |
magro732 |
|
1446 |
|
|
configStb_o <= '1' when ((configStb = '1') and (configAdr(23 downto 16) /= x"00")) else '0';
|
1447 |
47 |
magro732 |
configStbInternal <= '1' when ((configStb = '1') and (configAdr(23 downto 16) = x"00")) else '0';
|
1448 |
46 |
magro732 |
configWe_o <= configWe;
|
1449 |
|
|
configAddr_o <= configAdr;
|
1450 |
2 |
magro732 |
configData_o <= configDataWrite;
|
1451 |
47 |
magro732 |
configDataRead <= configData_i when (configStbInternal = '0') else configDataReadInternal;
|
1452 |
|
|
configAck <= configAck_i when (configStbInternal = '0') else configAckInternal;
|
1453 |
2 |
magro732 |
|
1454 |
|
|
ConfigMemory: process(areset_n, clk)
|
1455 |
|
|
begin
|
1456 |
|
|
if (areset_n = '0') then
|
1457 |
|
|
configDataReadInternal <= (others => '0');
|
1458 |
47 |
magro732 |
configAckInternal <= '0';
|
1459 |
2 |
magro732 |
|
1460 |
|
|
routeTableEnable <= '1';
|
1461 |
|
|
routeTableWrite <= '0';
|
1462 |
|
|
routeTableAddress <= (others => '0');
|
1463 |
|
|
routeTablePortWrite <= (others => '0');
|
1464 |
|
|
routeTablePortDefault <= (others => '0');
|
1465 |
|
|
|
1466 |
|
|
discovered <= '0';
|
1467 |
|
|
|
1468 |
|
|
hostBaseDeviceIdLocked <= '0';
|
1469 |
|
|
hostBaseDeviceId <= (others => '1');
|
1470 |
|
|
componentTag <= (others => '0');
|
1471 |
|
|
|
1472 |
|
|
portLinkTimeout <= (others => '1');
|
1473 |
|
|
|
1474 |
|
|
-- REMARK: These should be set to zero when a port gets initialized...
|
1475 |
|
|
outputPortEnable <= (others => '0');
|
1476 |
|
|
inputPortEnable <= (others => '0');
|
1477 |
|
|
|
1478 |
|
|
localAckIdWrite_o <= (others => '0');
|
1479 |
|
|
elsif (clk'event and clk = '1') then
|
1480 |
|
|
routeTableWrite <= '0';
|
1481 |
|
|
localAckIdWrite_o <= (others => '0');
|
1482 |
|
|
|
1483 |
47 |
magro732 |
if (configAckInternal = '0') then
|
1484 |
|
|
if (configStbInternal = '1') then
|
1485 |
|
|
configAckInternal <= '1';
|
1486 |
2 |
magro732 |
|
1487 |
46 |
magro732 |
-- Check if the access is into implementation defined space or if the
|
1488 |
|
|
-- access should be handled here.
|
1489 |
|
|
if (configAdr(23 downto 16) /= x"00") then
|
1490 |
|
|
-- Accessing implementation defined space.
|
1491 |
|
|
-- Make an external access and return the resonse.
|
1492 |
|
|
configDataReadInternal <= (others=>'0');
|
1493 |
|
|
else
|
1494 |
|
|
-- Access should be handled here.
|
1495 |
|
|
|
1496 |
|
|
case (configAdr) is
|
1497 |
|
|
when x"000000" =>
|
1498 |
|
|
-----------------------------------------------------------------
|
1499 |
|
|
-- Device Identity CAR. Read-only.
|
1500 |
|
|
-----------------------------------------------------------------
|
1501 |
2 |
magro732 |
|
1502 |
46 |
magro732 |
configDataReadInternal(31 downto 16) <= DEVICE_IDENTITY;
|
1503 |
|
|
configDataReadInternal(15 downto 0) <= DEVICE_VENDOR_IDENTITY;
|
1504 |
|
|
|
1505 |
|
|
when x"000004" =>
|
1506 |
|
|
-----------------------------------------------------------------
|
1507 |
|
|
-- Device Information CAR. Read-only.
|
1508 |
|
|
-----------------------------------------------------------------
|
1509 |
2 |
magro732 |
|
1510 |
46 |
magro732 |
configDataReadInternal(31 downto 0) <= DEVICE_REV;
|
1511 |
|
|
|
1512 |
|
|
when x"000008" =>
|
1513 |
|
|
-----------------------------------------------------------------
|
1514 |
|
|
-- Assembly Identity CAR. Read-only.
|
1515 |
|
|
-----------------------------------------------------------------
|
1516 |
2 |
magro732 |
|
1517 |
46 |
magro732 |
configDataReadInternal(31 downto 16) <= ASSY_IDENTITY;
|
1518 |
|
|
configDataReadInternal(15 downto 0) <= ASSY_VENDOR_IDENTITY;
|
1519 |
|
|
|
1520 |
|
|
when x"00000c" =>
|
1521 |
|
|
-----------------------------------------------------------------
|
1522 |
|
|
-- Assembly Informaiton CAR. Read-only.
|
1523 |
|
|
-----------------------------------------------------------------
|
1524 |
2 |
magro732 |
|
1525 |
46 |
magro732 |
configDataReadInternal(31 downto 16) <= ASSY_REV;
|
1526 |
|
|
configDataReadInternal(15 downto 0) <= x"0100";
|
1527 |
|
|
|
1528 |
|
|
when x"000010" =>
|
1529 |
|
|
-----------------------------------------------------------------
|
1530 |
|
|
-- Processing Element Features CAR. Read-only.
|
1531 |
|
|
-----------------------------------------------------------------
|
1532 |
|
|
|
1533 |
|
|
-- Bridge.
|
1534 |
|
|
configDataReadInternal(31) <= '0';
|
1535 |
|
|
|
1536 |
|
|
-- Memory.
|
1537 |
|
|
configDataReadInternal(30) <= '0';
|
1538 |
|
|
|
1539 |
|
|
-- Processor.
|
1540 |
|
|
configDataReadInternal(29) <= '0';
|
1541 |
|
|
|
1542 |
|
|
-- Switch.
|
1543 |
|
|
configDataReadInternal(28) <= '1';
|
1544 |
|
|
|
1545 |
|
|
-- Reserved.
|
1546 |
|
|
configDataReadInternal(27 downto 10) <= (others => '0');
|
1547 |
|
|
|
1548 |
|
|
-- Extended route table configuration support.
|
1549 |
|
|
configDataReadInternal(9) <= '0';
|
1550 |
|
|
|
1551 |
|
|
-- Standard route table configuration support.
|
1552 |
|
|
configDataReadInternal(8) <= '1';
|
1553 |
|
|
|
1554 |
|
|
-- Reserved.
|
1555 |
|
|
configDataReadInternal(7 downto 5) <= (others => '0');
|
1556 |
|
|
|
1557 |
|
|
-- Common transport large system support.
|
1558 |
|
|
configDataReadInternal(4) <= '1';
|
1559 |
|
|
|
1560 |
|
|
-- Extended features.
|
1561 |
|
|
configDataReadInternal(3) <= '1';
|
1562 |
|
|
|
1563 |
|
|
-- Extended addressing support.
|
1564 |
|
|
-- Not a processing element.
|
1565 |
|
|
configDataReadInternal(2 downto 0) <= "000";
|
1566 |
|
|
|
1567 |
|
|
when x"000014" =>
|
1568 |
|
|
-----------------------------------------------------------------
|
1569 |
|
|
-- Switch Port Information CAR. Read-only.
|
1570 |
|
|
-----------------------------------------------------------------
|
1571 |
2 |
magro732 |
|
1572 |
46 |
magro732 |
-- Reserved.
|
1573 |
|
|
configDataReadInternal(31 downto 16) <= (others => '0');
|
1574 |
2 |
magro732 |
|
1575 |
46 |
magro732 |
-- PortTotal.
|
1576 |
|
|
configDataReadInternal(15 downto 8) <=
|
1577 |
|
|
std_logic_vector(to_unsigned(SWITCH_PORTS, 8));
|
1578 |
2 |
magro732 |
|
1579 |
46 |
magro732 |
-- PortNumber.
|
1580 |
|
|
configDataReadInternal(7 downto 0) <= inboundFramePort;
|
1581 |
|
|
|
1582 |
|
|
when x"000034" =>
|
1583 |
|
|
-----------------------------------------------------------------
|
1584 |
|
|
-- Switch Route Table Destination ID Limit CAR.
|
1585 |
|
|
-----------------------------------------------------------------
|
1586 |
2 |
magro732 |
|
1587 |
46 |
magro732 |
-- Max_destId.
|
1588 |
|
|
-- Support 2048 addresses.
|
1589 |
|
|
configDataReadInternal(15 downto 0) <= x"0800";
|
1590 |
|
|
|
1591 |
|
|
when x"000068" =>
|
1592 |
|
|
-----------------------------------------------------------------
|
1593 |
|
|
-- Host Base Device ID Lock CSR.
|
1594 |
|
|
-----------------------------------------------------------------
|
1595 |
2 |
magro732 |
|
1596 |
46 |
magro732 |
if (configWe = '1') then
|
1597 |
|
|
-- Check if this field has been written before.
|
1598 |
|
|
if (hostBaseDeviceIdLocked = '0') then
|
1599 |
|
|
-- The field has not been written.
|
1600 |
|
|
-- Lock the field and set the host base device id.
|
1601 |
|
|
hostBaseDeviceIdLocked <= '1';
|
1602 |
|
|
hostBaseDeviceId <= configDataWrite(15 downto 0);
|
1603 |
2 |
magro732 |
else
|
1604 |
46 |
magro732 |
-- The field has been written.
|
1605 |
|
|
-- Check if the written data is the same as the stored.
|
1606 |
|
|
if (hostBaseDeviceId = configDataWrite(15 downto 0)) then
|
1607 |
|
|
-- Same as stored, reset the value to its initial value.
|
1608 |
|
|
hostBaseDeviceIdLocked <= '0';
|
1609 |
|
|
hostBaseDeviceId <= (others => '1');
|
1610 |
|
|
else
|
1611 |
|
|
-- Not writing the same as the stored value.
|
1612 |
|
|
-- Ignore the write.
|
1613 |
|
|
end if;
|
1614 |
2 |
magro732 |
end if;
|
1615 |
|
|
end if;
|
1616 |
46 |
magro732 |
|
1617 |
|
|
configDataReadInternal(31 downto 16) <= (others => '0');
|
1618 |
|
|
configDataReadInternal(15 downto 0) <= hostBaseDeviceId;
|
1619 |
|
|
|
1620 |
|
|
when x"00006c" =>
|
1621 |
|
|
-----------------------------------------------------------------
|
1622 |
|
|
-- Component TAG CSR.
|
1623 |
|
|
-----------------------------------------------------------------
|
1624 |
2 |
magro732 |
|
1625 |
46 |
magro732 |
if (configWe = '1') then
|
1626 |
|
|
componentTag <= configDataWrite;
|
1627 |
|
|
end if;
|
1628 |
|
|
|
1629 |
|
|
configDataReadInternal <= componentTag;
|
1630 |
|
|
|
1631 |
|
|
when x"000070" =>
|
1632 |
|
|
-----------------------------------------------------------------
|
1633 |
|
|
-- Standard Route Configuration Destination ID Select CSR.
|
1634 |
|
|
-----------------------------------------------------------------
|
1635 |
2 |
magro732 |
|
1636 |
46 |
magro732 |
if (configWe = '1') then
|
1637 |
|
|
-- Write the address to access the routing table.
|
1638 |
|
|
routeTableAddress <= configDataWrite(10 downto 0);
|
1639 |
|
|
end if;
|
1640 |
|
|
|
1641 |
|
|
configDataReadInternal(31 downto 11) <= (others => '0');
|
1642 |
|
|
configDataReadInternal(10 downto 0) <= routeTableAddress;
|
1643 |
|
|
|
1644 |
|
|
when x"000074" =>
|
1645 |
|
|
-----------------------------------------------------------------
|
1646 |
|
|
-- Standard Route Configuration Port Select CSR.
|
1647 |
|
|
-----------------------------------------------------------------
|
1648 |
2 |
magro732 |
|
1649 |
46 |
magro732 |
if (configWe = '1') then
|
1650 |
|
|
-- Write the port information for the address selected by the
|
1651 |
|
|
-- above register.
|
1652 |
|
|
routeTableWrite <= '1';
|
1653 |
|
|
routeTablePortWrite <= configDataWrite(7 downto 0);
|
1654 |
|
|
end if;
|
1655 |
2 |
magro732 |
|
1656 |
46 |
magro732 |
configDataReadInternal(31 downto 8) <= (others => '0');
|
1657 |
|
|
configDataReadInternal(7 downto 0) <= routeTablePortRead;
|
1658 |
|
|
|
1659 |
|
|
when x"000078" =>
|
1660 |
|
|
-----------------------------------------------------------------
|
1661 |
|
|
-- Standard Route Default Port CSR.
|
1662 |
|
|
-----------------------------------------------------------------
|
1663 |
2 |
magro732 |
|
1664 |
46 |
magro732 |
if (configWe = '1') then
|
1665 |
|
|
-- Write the default route device id.
|
1666 |
|
|
routeTablePortDefault <= configDataWrite(7 downto 0);
|
1667 |
|
|
end if;
|
1668 |
|
|
|
1669 |
|
|
configDataReadInternal(31 downto 8) <= (others => '0');
|
1670 |
|
|
configDataReadInternal(7 downto 0) <= routeTablePortDefault;
|
1671 |
|
|
|
1672 |
|
|
when x"000100" =>
|
1673 |
|
|
-----------------------------------------------------------------
|
1674 |
|
|
-- Extended features. LP-Serial Register Block Header.
|
1675 |
|
|
-----------------------------------------------------------------
|
1676 |
2 |
magro732 |
|
1677 |
46 |
magro732 |
-- One feature only, 0x0003=Generic End Point Free Device.
|
1678 |
|
|
configDataReadInternal(31 downto 16) <= x"0000";
|
1679 |
|
|
configDataReadInternal(15 downto 0) <= x"0003";
|
1680 |
|
|
|
1681 |
|
|
when x"000120" =>
|
1682 |
|
|
-----------------------------------------------------------------
|
1683 |
|
|
-- Port Link Timeout Control CSR.
|
1684 |
|
|
-----------------------------------------------------------------
|
1685 |
2 |
magro732 |
|
1686 |
46 |
magro732 |
if (configWe = '1') then
|
1687 |
|
|
portLinkTimeout <= configDataWrite(31 downto 8);
|
1688 |
|
|
end if;
|
1689 |
|
|
|
1690 |
|
|
configDataReadInternal(31 downto 8) <= portLinkTimeout;
|
1691 |
|
|
configDataReadInternal(7 downto 0) <= x"00";
|
1692 |
|
|
|
1693 |
|
|
when x"00013c" =>
|
1694 |
|
|
-----------------------------------------------------------------
|
1695 |
|
|
-- Port General Control CSR.
|
1696 |
|
|
-----------------------------------------------------------------
|
1697 |
2 |
magro732 |
|
1698 |
46 |
magro732 |
if (configWe = '1') then
|
1699 |
|
|
discovered <= configDataWrite(29);
|
1700 |
|
|
end if;
|
1701 |
|
|
|
1702 |
|
|
configDataReadInternal(31 downto 30) <= "00";
|
1703 |
|
|
configDataReadInternal(29) <= discovered;
|
1704 |
|
|
configDataReadInternal(28 downto 0) <= (others => '0');
|
1705 |
2 |
magro732 |
|
1706 |
46 |
magro732 |
when others =>
|
1707 |
|
|
-----------------------------------------------------------------
|
1708 |
|
|
-- Other port specific registers.
|
1709 |
|
|
-----------------------------------------------------------------
|
1710 |
|
|
|
1711 |
|
|
-- Make sure the output is always set to something.
|
1712 |
|
|
configDataReadInternal <= (others=>'0');
|
1713 |
2 |
magro732 |
|
1714 |
46 |
magro732 |
-- Iterate through all active ports.
|
1715 |
|
|
for portIndex in 0 to SWITCH_PORTS-1 loop
|
1716 |
2 |
magro732 |
|
1717 |
46 |
magro732 |
if(unsigned(configAdr) = (x"000148" + (x"000020"*portIndex))) then
|
1718 |
|
|
-----------------------------------------------------------------
|
1719 |
|
|
-- Port N Local ackID CSR.
|
1720 |
|
|
-----------------------------------------------------------------
|
1721 |
|
|
if (configWe = '1') then
|
1722 |
|
|
localAckIdWrite_o(portIndex) <= '1';
|
1723 |
|
|
clrOutstandingAckId_o(portIndex) <= configDataWrite(31);
|
1724 |
|
|
inboundAckId_o(portIndex) <= configDataWrite(28 downto 24);
|
1725 |
|
|
outstandingAckId_o(portIndex) <= configDataWrite(12 downto 8);
|
1726 |
|
|
outboundAckId_o(portIndex) <= configDataWrite(4 downto 0);
|
1727 |
|
|
end if;
|
1728 |
|
|
configDataReadInternal(31 downto 29) <= (others => '0');
|
1729 |
|
|
configDataReadInternal(28 downto 24) <= inboundAckId_i(portIndex);
|
1730 |
|
|
configDataReadInternal(23 downto 13) <= (others => '0');
|
1731 |
|
|
configDataReadInternal(12 downto 8) <= outstandingAckId_i(portIndex);
|
1732 |
|
|
configDataReadInternal(7 downto 5) <= (others => '0');
|
1733 |
|
|
configDataReadInternal(4 downto 0) <= outboundAckId_i(portIndex);
|
1734 |
|
|
|
1735 |
|
|
elsif(unsigned(configAdr) = (x"000154" + (x"000020"*portIndex))) then
|
1736 |
|
|
-----------------------------------------------------------------
|
1737 |
|
|
-- Port N Control 2 CSR.
|
1738 |
|
|
-----------------------------------------------------------------
|
1739 |
|
|
configDataReadInternal <= (others => '0');
|
1740 |
|
|
|
1741 |
|
|
elsif(unsigned(configAdr) = (x"000158" + (x"000020"*portIndex))) then
|
1742 |
|
|
-----------------------------------------------------------------
|
1743 |
|
|
-- Port N Error and Status CSR.
|
1744 |
|
|
-----------------------------------------------------------------
|
1745 |
|
|
-- Idle Sequence 2 Support.
|
1746 |
|
|
configDataReadInternal(31) <= '0';
|
1747 |
|
|
|
1748 |
|
|
-- Idle Sequence 2 Enable.
|
1749 |
|
|
configDataReadInternal(30) <= '0';
|
1750 |
|
|
|
1751 |
|
|
-- Idle Sequence.
|
1752 |
|
|
configDataReadInternal(29) <= '0';
|
1753 |
|
|
|
1754 |
|
|
-- Reserved.
|
1755 |
|
|
configDataReadInternal(28) <= '0';
|
1756 |
|
|
|
1757 |
|
|
-- Flow Control Mode.
|
1758 |
|
|
configDataReadInternal(27) <= '0';
|
1759 |
|
|
|
1760 |
|
|
-- Reserved.
|
1761 |
|
|
configDataReadInternal(26 downto 21) <= (others => '0');
|
1762 |
|
|
|
1763 |
|
|
-- Output retry-encountered.
|
1764 |
|
|
configDataReadInternal(20) <= '0';
|
1765 |
|
|
|
1766 |
|
|
-- Output retried.
|
1767 |
|
|
configDataReadInternal(19) <= '0';
|
1768 |
|
|
|
1769 |
|
|
-- Output retried-stopped.
|
1770 |
|
|
configDataReadInternal(18) <= '0';
|
1771 |
|
|
|
1772 |
|
|
-- Output error-encountered.
|
1773 |
|
|
configDataReadInternal(17) <= '0';
|
1774 |
|
|
|
1775 |
|
|
-- Output error-stopped.
|
1776 |
|
|
configDataReadInternal(16) <= '0';
|
1777 |
|
|
|
1778 |
|
|
-- Reserved.
|
1779 |
|
|
configDataReadInternal(15 downto 11) <= (others => '0');
|
1780 |
|
|
|
1781 |
|
|
-- Input retry-stopped.
|
1782 |
|
|
configDataReadInternal(10) <= '0';
|
1783 |
|
|
|
1784 |
|
|
-- Input error-encountered.
|
1785 |
|
|
configDataReadInternal(9) <= '0';
|
1786 |
|
|
|
1787 |
|
|
-- Input error-stopped.
|
1788 |
|
|
configDataReadInternal(8) <= '0';
|
1789 |
2 |
magro732 |
|
1790 |
46 |
magro732 |
-- Reserved.
|
1791 |
|
|
configDataReadInternal(7 downto 5) <= (others => '0');
|
1792 |
2 |
magro732 |
|
1793 |
46 |
magro732 |
-- Port-write pending.
|
1794 |
|
|
configDataReadInternal(4) <= '0';
|
1795 |
|
|
|
1796 |
|
|
-- Port unavailable.
|
1797 |
|
|
configDataReadInternal(3) <= '0';
|
1798 |
|
|
|
1799 |
|
|
-- Port error.
|
1800 |
|
|
configDataReadInternal(2) <= '0';
|
1801 |
|
|
|
1802 |
|
|
-- Port OK.
|
1803 |
|
|
configDataReadInternal(1) <= linkInitialized_i(portIndex);
|
1804 |
|
|
|
1805 |
|
|
-- Port uninitialized.
|
1806 |
|
|
configDataReadInternal(0) <= not linkInitialized_i(portIndex);
|
1807 |
|
|
|
1808 |
|
|
elsif(unsigned(configAdr) = (x"00015c" + (x"000020"*portIndex))) then
|
1809 |
|
|
-----------------------------------------------------------------
|
1810 |
|
|
-- Port N Control CSR.
|
1811 |
|
|
-----------------------------------------------------------------
|
1812 |
|
|
|
1813 |
|
|
-- Port Width Support.
|
1814 |
|
|
configDataReadInternal(31 downto 30) <= (others=>'0');
|
1815 |
2 |
magro732 |
|
1816 |
46 |
magro732 |
-- Initialized Port Width.
|
1817 |
|
|
configDataReadInternal(29 downto 27) <= (others=>'0');
|
1818 |
2 |
magro732 |
|
1819 |
46 |
magro732 |
-- Port Width Override.
|
1820 |
|
|
configDataReadInternal(26 downto 24) <= (others=>'0');
|
1821 |
2 |
magro732 |
|
1822 |
46 |
magro732 |
-- Port disable.
|
1823 |
|
|
configDataReadInternal(23) <= '0';
|
1824 |
|
|
|
1825 |
|
|
-- Output Port Enable.
|
1826 |
|
|
if (configWe = '1') then
|
1827 |
|
|
outputPortEnable(portIndex) <= configDataWrite(22);
|
1828 |
|
|
end if;
|
1829 |
|
|
configDataReadInternal(22) <= outputPortEnable(portIndex);
|
1830 |
|
|
|
1831 |
|
|
-- Input Port Enable.
|
1832 |
|
|
if (configWe = '1') then
|
1833 |
|
|
inputPortEnable(portIndex) <= configDataWrite(21);
|
1834 |
|
|
end if;
|
1835 |
|
|
configDataReadInternal(21) <= inputPortEnable(portIndex);
|
1836 |
2 |
magro732 |
|
1837 |
46 |
magro732 |
-- Error Checking Disabled.
|
1838 |
|
|
configDataReadInternal(20) <= '0';
|
1839 |
|
|
|
1840 |
|
|
-- Multicast-event Participant.
|
1841 |
|
|
configDataReadInternal(19) <= '0';
|
1842 |
|
|
|
1843 |
|
|
-- Reserved.
|
1844 |
|
|
configDataReadInternal(18) <= '0';
|
1845 |
|
|
|
1846 |
|
|
-- Enumeration Boundry.
|
1847 |
|
|
configDataReadInternal(17) <= '0';
|
1848 |
2 |
magro732 |
|
1849 |
46 |
magro732 |
-- Reserved.
|
1850 |
|
|
configDataReadInternal(16) <= '0';
|
1851 |
2 |
magro732 |
|
1852 |
46 |
magro732 |
-- Extended Port Width Override.
|
1853 |
|
|
configDataReadInternal(15 downto 14) <= (others=>'0');
|
1854 |
2 |
magro732 |
|
1855 |
46 |
magro732 |
-- Extended Port Width Support.
|
1856 |
|
|
configDataReadInternal(13 downto 12) <= (others=>'0');
|
1857 |
|
|
|
1858 |
|
|
-- Implementation defined.
|
1859 |
|
|
configDataReadInternal(11 downto 4) <= (others=>'0');
|
1860 |
2 |
magro732 |
|
1861 |
46 |
magro732 |
-- Reserved.
|
1862 |
|
|
configDataReadInternal(3 downto 1) <= (others=>'0');
|
1863 |
2 |
magro732 |
|
1864 |
46 |
magro732 |
-- Port Type.
|
1865 |
|
|
configDataReadInternal(0) <= '1';
|
1866 |
|
|
end if;
|
1867 |
|
|
end loop;
|
1868 |
2 |
magro732 |
|
1869 |
46 |
magro732 |
end case;
|
1870 |
|
|
end if;
|
1871 |
|
|
else
|
1872 |
|
|
-- Config memory not enabled.
|
1873 |
2 |
magro732 |
end if;
|
1874 |
|
|
else
|
1875 |
47 |
magro732 |
configAckInternal <= '0';
|
1876 |
2 |
magro732 |
end if;
|
1877 |
|
|
end if;
|
1878 |
|
|
end process;
|
1879 |
|
|
|
1880 |
46 |
magro732 |
-----------------------------------------------------------------------------
|
1881 |
|
|
-- Logic implementing the routing table access.
|
1882 |
|
|
-----------------------------------------------------------------------------
|
1883 |
|
|
|
1884 |
|
|
-- Lookup interface port memory signals.
|
1885 |
|
|
lookupEnable <= '1' when (lookupStb_i = '1') and (lookupAddr_i(15 downto 11) = "00000") else '0';
|
1886 |
|
|
lookupAddress <= lookupAddr_i(10 downto 0);
|
1887 |
|
|
lookupData_o <= lookupData when (lookupEnable = '1') else routeTablePortDefault;
|
1888 |
|
|
lookupAck_o <= lookupAck;
|
1889 |
|
|
LookupProcess: process(clk, areset_n)
|
1890 |
|
|
begin
|
1891 |
|
|
if (areset_n = '0') then
|
1892 |
|
|
lookupAck <= '0';
|
1893 |
|
|
elsif (clk'event and clk = '1') then
|
1894 |
|
|
if ((lookupStb_i = '1') and (lookupAck = '0')) then
|
1895 |
|
|
lookupAck <= '1';
|
1896 |
|
|
else
|
1897 |
|
|
lookupAck <= '0';
|
1898 |
|
|
end if;
|
1899 |
|
|
end if;
|
1900 |
|
|
end process;
|
1901 |
|
|
|
1902 |
|
|
-- Dual port memory containing the routing table.
|
1903 |
|
|
RoutingTable: MemoryDualPort
|
1904 |
|
|
generic map(
|
1905 |
|
|
ADDRESS_WIDTH=>11, DATA_WIDTH=>8)
|
1906 |
|
|
port map(
|
1907 |
|
|
clkA_i=>clk, enableA_i=>routeTableEnable, writeEnableA_i=>routeTableWrite,
|
1908 |
|
|
addressA_i=>routeTableAddress,
|
1909 |
|
|
dataA_i=>routeTablePortWrite, dataA_o=>routeTablePortRead,
|
1910 |
|
|
clkB_i=>clk, enableB_i=>lookupEnable,
|
1911 |
|
|
addressB_i=>lookupAddress, dataB_o=>lookupData);
|
1912 |
|
|
|
1913 |
2 |
magro732 |
end architecture;
|
1914 |
|
|
|
1915 |
|
|
|
1916 |
|
|
-------------------------------------------------------------------------------
|
1917 |
|
|
--
|
1918 |
|
|
-------------------------------------------------------------------------------
|
1919 |
|
|
|
1920 |
|
|
library ieee;
|
1921 |
|
|
use ieee.std_logic_1164.all;
|
1922 |
|
|
use ieee.numeric_std.all;
|
1923 |
|
|
use work.rio_common.all;
|
1924 |
|
|
|
1925 |
|
|
|
1926 |
|
|
-------------------------------------------------------------------------------
|
1927 |
|
|
--
|
1928 |
|
|
-------------------------------------------------------------------------------
|
1929 |
|
|
entity RouteTableInterconnect is
|
1930 |
|
|
generic(
|
1931 |
|
|
WIDTH : natural range 1 to 256 := 8);
|
1932 |
|
|
port(
|
1933 |
|
|
clk : in std_logic;
|
1934 |
|
|
areset_n : in std_logic;
|
1935 |
|
|
|
1936 |
|
|
stb_i : in Array1(WIDTH-1 downto 0);
|
1937 |
|
|
addr_i : in Array16(WIDTH-1 downto 0);
|
1938 |
|
|
dataM_o : out Array8(WIDTH-1 downto 0);
|
1939 |
|
|
ack_o : out Array1(WIDTH-1 downto 0);
|
1940 |
|
|
|
1941 |
|
|
stb_o : out std_logic;
|
1942 |
|
|
addr_o : out std_logic_vector(15 downto 0);
|
1943 |
|
|
dataS_i : in std_logic_vector(7 downto 0);
|
1944 |
|
|
ack_i : in std_logic);
|
1945 |
|
|
end entity;
|
1946 |
|
|
|
1947 |
|
|
|
1948 |
|
|
-------------------------------------------------------------------------------
|
1949 |
|
|
--
|
1950 |
|
|
-------------------------------------------------------------------------------
|
1951 |
|
|
architecture RouteTableInterconnectImpl of RouteTableInterconnect is
|
1952 |
|
|
signal activeCycle : std_logic;
|
1953 |
|
|
signal selectedMaster : natural range 0 to WIDTH-1;
|
1954 |
|
|
begin
|
1955 |
|
|
|
1956 |
|
|
-----------------------------------------------------------------------------
|
1957 |
|
|
-- Arbitration.
|
1958 |
|
|
-----------------------------------------------------------------------------
|
1959 |
|
|
Arbiter: process(areset_n, clk)
|
1960 |
|
|
begin
|
1961 |
|
|
if (areset_n = '0') then
|
1962 |
|
|
activeCycle <= '0';
|
1963 |
|
|
selectedMaster <= 0;
|
1964 |
|
|
elsif (clk'event and clk = '1') then
|
1965 |
|
|
if (activeCycle = '0') then
|
1966 |
|
|
for i in 0 to WIDTH-1 loop
|
1967 |
|
|
if (stb_i(i) = '1') then
|
1968 |
|
|
activeCycle <= '1';
|
1969 |
|
|
selectedMaster <= i;
|
1970 |
|
|
end if;
|
1971 |
|
|
end loop;
|
1972 |
|
|
else
|
1973 |
|
|
if (stb_i(selectedMaster) = '0') then
|
1974 |
|
|
activeCycle <= '0';
|
1975 |
|
|
end if;
|
1976 |
|
|
end if;
|
1977 |
|
|
end if;
|
1978 |
|
|
end process;
|
1979 |
|
|
|
1980 |
|
|
-----------------------------------------------------------------------------
|
1981 |
|
|
-- Interconnection.
|
1982 |
|
|
-----------------------------------------------------------------------------
|
1983 |
|
|
stb_o <= stb_i(selectedMaster);
|
1984 |
|
|
addr_o <= addr_i(selectedMaster);
|
1985 |
|
|
|
1986 |
|
|
Interconnect: for i in 0 to WIDTH-1 generate
|
1987 |
|
|
dataM_o(i) <= dataS_i;
|
1988 |
|
|
ack_o(i) <= ack_i when (selectedMaster = i) else '0';
|
1989 |
|
|
end generate;
|
1990 |
|
|
|
1991 |
|
|
end architecture;
|
1992 |
|
|
|
1993 |
|
|
|
1994 |
|
|
-------------------------------------------------------------------------------
|
1995 |
|
|
--
|
1996 |
|
|
-------------------------------------------------------------------------------
|
1997 |
|
|
|
1998 |
|
|
library ieee;
|
1999 |
|
|
use ieee.std_logic_1164.all;
|
2000 |
|
|
use ieee.numeric_std.all;
|
2001 |
|
|
use work.rio_common.all;
|
2002 |
|
|
|
2003 |
|
|
|
2004 |
|
|
-------------------------------------------------------------------------------
|
2005 |
|
|
--
|
2006 |
|
|
-------------------------------------------------------------------------------
|
2007 |
|
|
entity SwitchPortInterconnect is
|
2008 |
|
|
generic(
|
2009 |
|
|
WIDTH : natural range 1 to 256 := 8);
|
2010 |
|
|
port(
|
2011 |
|
|
clk : in std_logic;
|
2012 |
|
|
areset_n : in std_logic;
|
2013 |
|
|
|
2014 |
|
|
masterCyc_i : in Array1(WIDTH-1 downto 0);
|
2015 |
|
|
masterStb_i : in Array1(WIDTH-1 downto 0);
|
2016 |
|
|
masterWe_i : in Array1(WIDTH-1 downto 0);
|
2017 |
|
|
masterAddr_i : in Array10(WIDTH-1 downto 0);
|
2018 |
|
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masterData_i : in Array32(WIDTH-1 downto 0);
|
2019 |
|
|
masterData_o : out Array1(WIDTH-1 downto 0);
|
2020 |
|
|
masterAck_o : out Array1(WIDTH-1 downto 0);
|
2021 |
|
|
|
2022 |
|
|
slaveCyc_o : out Array1(WIDTH-1 downto 0);
|
2023 |
|
|
slaveStb_o : out Array1(WIDTH-1 downto 0);
|
2024 |
|
|
slaveWe_o : out Array1(WIDTH-1 downto 0);
|
2025 |
|
|
slaveAddr_o : out Array10(WIDTH-1 downto 0);
|
2026 |
|
|
slaveData_o : out Array32(WIDTH-1 downto 0);
|
2027 |
|
|
slaveData_i : in Array1(WIDTH-1 downto 0);
|
2028 |
|
|
slaveAck_i : in Array1(WIDTH-1 downto 0));
|
2029 |
|
|
end entity;
|
2030 |
|
|
|
2031 |
|
|
|
2032 |
|
|
-------------------------------------------------------------------------------
|
2033 |
|
|
--
|
2034 |
|
|
-------------------------------------------------------------------------------
|
2035 |
|
|
architecture SwitchPortInterconnectImpl of SwitchPortInterconnect is
|
2036 |
|
|
--component ChipscopeIcon1 is
|
2037 |
|
|
-- port (
|
2038 |
|
|
-- CONTROL0 : inout STD_LOGIC_VECTOR ( 35 downto 0 )
|
2039 |
|
|
-- );
|
2040 |
|
|
--end component;
|
2041 |
|
|
--component ChipscopeIlaWb is
|
2042 |
|
|
-- port (
|
2043 |
|
|
-- CLK : in STD_LOGIC := 'X';
|
2044 |
|
|
-- TRIG0 : in STD_LOGIC_VECTOR ( 46 downto 0);
|
2045 |
|
|
-- CONTROL : inout STD_LOGIC_VECTOR ( 35 downto 0 )
|
2046 |
|
|
-- );
|
2047 |
|
|
--end component;
|
2048 |
|
|
--signal control : std_logic_vector(35 downto 0);
|
2049 |
|
|
--signal trig : std_logic_vector(46 downto 0);
|
2050 |
|
|
|
2051 |
|
|
signal activeCycle : std_logic;
|
2052 |
|
|
signal selectedMaster : natural range 0 to WIDTH-1;
|
2053 |
|
|
signal selectedSlave : natural range 0 to WIDTH-1;
|
2054 |
|
|
|
2055 |
|
|
begin
|
2056 |
|
|
|
2057 |
|
|
-----------------------------------------------------------------------------
|
2058 |
|
|
-- Arbitration process.
|
2059 |
|
|
-----------------------------------------------------------------------------
|
2060 |
|
|
|
2061 |
|
|
RoundRobinArbiter: process(areset_n, clk)
|
2062 |
|
|
variable index : natural range 0 to WIDTH-1;
|
2063 |
|
|
begin
|
2064 |
|
|
if (areset_n = '0') then
|
2065 |
|
|
activeCycle <= '0';
|
2066 |
|
|
selectedMaster <= 0;
|
2067 |
|
|
elsif (clk'event and clk = '1') then
|
2068 |
|
|
-- Check if a cycle is ongoing.
|
2069 |
|
|
if (activeCycle = '0') then
|
2070 |
|
|
-- No ongoing cycles.
|
2071 |
|
|
|
2072 |
|
|
-- Iterate through all ports and check if any new cycle has started.
|
2073 |
|
|
for i in 0 to WIDTH-1 loop
|
2074 |
|
|
if ((selectedMaster+i) >= WIDTH) then
|
2075 |
|
|
index := (selectedMaster+i) - WIDTH;
|
2076 |
|
|
else
|
2077 |
|
|
index := (selectedMaster+i);
|
2078 |
|
|
end if;
|
2079 |
|
|
|
2080 |
|
|
if (masterCyc_i(index) = '1') then
|
2081 |
|
|
activeCycle <= '1';
|
2082 |
|
|
selectedMaster <= index;
|
2083 |
|
|
end if;
|
2084 |
|
|
end loop;
|
2085 |
|
|
else
|
2086 |
|
|
-- Ongoing cycle.
|
2087 |
|
|
|
2088 |
|
|
-- Check if the cycle has ended.
|
2089 |
|
|
if (masterCyc_i(selectedMaster) = '0') then
|
2090 |
|
|
-- Cycle has ended.
|
2091 |
|
|
activeCycle <= '0';
|
2092 |
|
|
|
2093 |
|
|
-- Check if a new cycle has started from another master.
|
2094 |
|
|
-- Start to check from the one that ended its cycle, this way, the
|
2095 |
|
|
-- ports will be scheduled like round-robin.
|
2096 |
|
|
for i in 0 to WIDTH-1 loop
|
2097 |
|
|
if ((selectedMaster+i) >= WIDTH) then
|
2098 |
|
|
index := (selectedMaster+i) - WIDTH;
|
2099 |
|
|
else
|
2100 |
|
|
index := (selectedMaster+i);
|
2101 |
|
|
end if;
|
2102 |
|
|
|
2103 |
|
|
if (masterCyc_i(index) = '1') then
|
2104 |
|
|
activeCycle <= '1';
|
2105 |
|
|
selectedMaster <= index;
|
2106 |
|
|
end if;
|
2107 |
|
|
end loop;
|
2108 |
|
|
end if;
|
2109 |
|
|
end if;
|
2110 |
|
|
end if;
|
2111 |
|
|
end process;
|
2112 |
|
|
|
2113 |
|
|
-----------------------------------------------------------------------------
|
2114 |
|
|
-- Address decoding.
|
2115 |
|
|
-----------------------------------------------------------------------------
|
2116 |
|
|
|
2117 |
|
|
-- Select the last port when the top bit is set.
|
2118 |
|
|
-- The last port must be the maintenance slave port.
|
2119 |
|
|
selectedSlave <= WIDTH-1 when masterAddr_i(selectedMaster)(9) = '1' else
|
2120 |
|
|
to_integer(unsigned(masterAddr_i(selectedMaster)(8 downto 1)));
|
2121 |
|
|
|
2122 |
|
|
-----------------------------------------------------------------------------
|
2123 |
|
|
-- Interconnection matrix.
|
2124 |
|
|
-----------------------------------------------------------------------------
|
2125 |
|
|
Interconnect: for i in 0 to WIDTH-1 generate
|
2126 |
|
|
slaveCyc_o(i) <= masterCyc_i(selectedMaster) when (selectedSlave = i) else '0';
|
2127 |
|
|
slaveStb_o(i) <= masterStb_i(selectedMaster) when (selectedSlave = i) else '0';
|
2128 |
|
|
slaveWe_o(i) <= masterWe_i(selectedMaster);
|
2129 |
|
|
slaveAddr_o(i) <= masterAddr_i(selectedMaster);
|
2130 |
|
|
slaveData_o(i) <= masterData_i(selectedMaster);
|
2131 |
|
|
masterData_o(i) <= slaveData_i(selectedSlave);
|
2132 |
|
|
masterAck_o(i) <= slaveAck_i(selectedSlave) when (selectedMaster = i) else '0';
|
2133 |
|
|
end generate;
|
2134 |
|
|
|
2135 |
|
|
-----------------------------------------------------------------------------
|
2136 |
|
|
-- Chipscope debugging probe.
|
2137 |
|
|
-----------------------------------------------------------------------------
|
2138 |
|
|
--trig <= masterCyc_i(selectedMaster) & masterStb_i(selectedMaster) &
|
2139 |
|
|
-- masterWe_i(selectedMaster) & masterAddr_i(selectedMaster) &
|
2140 |
|
|
-- masterData_i(selectedMaster) & slaveData_i(selectedSlave) &
|
2141 |
|
|
-- slaveAck_i(selectedSlave);
|
2142 |
|
|
--ChipscopeIconInst: ChipscopeIcon1
|
2143 |
|
|
-- port map(CONTROL0=>control);
|
2144 |
|
|
--ChipscopeIlaInst: ChipscopeIlaWb
|
2145 |
|
|
-- port map(CLK=>clk, TRIG0=>trig, CONTROL=>control);
|
2146 |
|
|
|
2147 |
|
|
end architecture;
|
2148 |
|
|
|
2149 |
|
|
|
2150 |
|
|
|