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[/] [rio/] [branches/] [2.0.0-development/] [rtl/] [vhdl/] [RioWbBridge.vhd] - Blame information for rev 47

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1 6 magro732 
-------------------------------------------------------------------------------
2 
--
3 
-- RapidIO IP Library Core
4 
--
5 
-- This file is part of the RapidIO IP library project
6 
-- http://www.opencores.org/cores/rio/
7 
--
8 
-- Description
9 
-- Containing a bridge between a RapidIO network and a Wishbone bus. Packets
10 39 magro732 
-- NWRITE, NWRITER and NREAD are currently supported.
11 6 magro732 
--
12 
-- To Do:
13 47 magro732 
-- - Move packet handlers to RioLogicalPackets and make them symetrical.
14 
-- - Add support for addressing to implementation defined config space by
15 
--   adding interface to top entity.
16 46 magro732 
-- - Set the stb_o to '0' in between read accesses to conform better to a
17 
--   block transfer in the Wishbone standard.
18 
-- - Clean up cyc-signals, only stb-signals are needed (between
19 
--   RioLogicalCommon and the packet handlers).
20 
-- - Add support for the lock_o to be sure to transfer all the packet
21 
--   content atomically?
22 
-- - Add support for EXTENDED_ADDRESS.
23 
-- - Use the baseDeviceId when sending packets? Currently, all responses
24 
--   are sent with destination<->source exchanged so the baseDeviceId is not
25 
--   needed.
26 
-- - Support inbound data with full bandwidth, not just half, applies to
27 
--   RioLogicalCommon and the packet handlers.
28 
-- - Move the packet handlers to seperate files.
29 
-- - Increase the priority of the response-packet when sent?
30 
-- - Implement error indications if erronous packets are received.
31 
-- - Implement error indications if err_i is received on the Wishbone bus.
32 
-- - Add support for extended features to dynamically configure the status
33 
--   from the port this block is connected to. Needed for the discovered- and
34 
--   masterEnable-bits.
35 
-- - Add support for outbound doorbells connected to interrupt input pins.
36 6 magro732 
--
37 
-- Author(s):
38 39 magro732 
-- - Magnus Rosenius, magro732@opencores.org
39 6 magro732 
--
40 
-------------------------------------------------------------------------------
41 
--
42 
-- Copyright (C) 2013 Authors and OPENCORES.ORG
43 
--
44 
-- This source file may be used and distributed without
45 
-- restriction provided that this copyright statement is not
46 
-- removed from the file and that any derivative work contains
47 
-- the original copyright notice and the associated disclaimer.
48 
--
49 
-- This source file is free software; you can redistribute it
50 
-- and/or modify it under the terms of the GNU Lesser General
51 
-- Public License as published by the Free Software Foundation;
52 
-- either version 2.1 of the License, or (at your option) any
53 
-- later version.
54 
--
55 
-- This source is distributed in the hope that it will be
56 
-- useful, but WITHOUT ANY WARRANTY; without even the implied
57 
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
58 
-- PURPOSE. See the GNU Lesser General Public License for more
59 
-- details.
60 
--
61 
-- You should have received a copy of the GNU Lesser General
62 
-- Public License along with this source; if not, download it
63 
-- from http://www.opencores.org/lgpl.shtml
64 
--
65 
-------------------------------------------------------------------------------
66 
 
67 45 magro732 
 
68 39 magro732 
-------------------------------------------------------------------------------
69 
-- RioWbBridge.
70 45 magro732 
-- This block acts as an RapidIO endpoint and converts packets into Wishbone
71 
-- accesses.
72 39 magro732 
-------------------------------------------------------------------------------
73 6 magro732 
library ieee;
74 
use ieee.std_logic_1164.all;
75 42 magro732 
use ieee.numeric_std.all;
76 6 magro732 
use work.rio_common.all;
77 
 
78 
-------------------------------------------------------------------------------
79 39 magro732 
-- Entity for RioWbBridge.
80 6 magro732 
-------------------------------------------------------------------------------
81 39 magro732 
entity RioWbBridge is
82 6 magro732 
  generic(
83 39 magro732 
    EXTENDED_ADDRESS : natural range 0 to 2 := 0;
84 6 magro732 
    DEVICE_IDENTITY : std_logic_vector(15 downto 0);
85 
    DEVICE_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
86 
    DEVICE_REV : std_logic_vector(31 downto 0);
87 
    ASSY_IDENTITY : std_logic_vector(15 downto 0);
88 
    ASSY_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
89 39 magro732 
    ASSY_REV : std_logic_vector(15 downto 0));
90 6 magro732 
  port(
91 39 magro732 
    clk : in std_logic;
92 
    areset_n : in std_logic;
93 44 magro732 
    enable : in std_logic;
94 6 magro732 
 
95 
    readFrameEmpty_i : in std_logic;
96 
    readFrame_o : out std_logic;
97 
    readContent_o : out std_logic;
98 
    readContentEnd_i : in std_logic;
99 
    readContentData_i : in std_logic_vector(31 downto 0);
100 
    writeFrameFull_i : in std_logic;
101 
    writeFrame_o : out std_logic;
102 
    writeFrameAbort_o : out std_logic;
103 
    writeContent_o : out std_logic;
104 
    writeContentData_o : out std_logic_vector(31 downto 0);
105 
 
106 39 magro732 
    cyc_o : out std_logic;
107 
    stb_o : out std_logic;
108 
    we_o : out std_logic;
109 
    adr_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
110 
    sel_o : out std_logic_vector(7 downto 0);
111 
    dat_o : out std_logic_vector(63 downto 0);
112 
    dat_i : in std_logic_vector(63 downto 0);
113 
    err_i : in std_logic;
114 
    ack_i : in std_logic);
115 
end entity;
116 6 magro732 
 
117 39 magro732 
 
118 6 magro732 
-------------------------------------------------------------------------------
119 
-- Architecture for RioWbBridge.
120 
-------------------------------------------------------------------------------
121 39 magro732 
architecture RioWbBridgeImpl of RioWbBridge is
122 6 magro732 
 
123 39 magro732 
  component RequestClassInbound is
124 
    generic(
125 
      EXTENDED_ADDRESS : natural range 0 to 2 := 0);
126 6 magro732 
    port(
127 39 magro732 
      clk : in std_logic;
128 
      areset_n : in std_logic;
129 
      enable : in std_logic;
130 
 
131 
      ready_o : out std_logic;
132 
      vc_o : out std_logic;
133 
      crf_o : out std_logic;
134 
      prio_o : out std_logic_vector(1 downto 0);
135 
      tt_o : out std_logic_vector(1 downto 0);
136 
      dstId_o : out std_logic_vector(31 downto 0);
137 
      srcId_o : out std_logic_vector(31 downto 0);
138 
      tid_o : out std_logic_vector(7 downto 0);
139 
      address_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
140 44 magro732 
      length_o : out std_logic_vector(4 downto 0);
141 39 magro732 
      select_o : out std_logic_vector(7 downto 0);
142 
      done_i : in std_logic;
143 
 
144 45 magro732 
      inboundCyc_i : in std_logic;
145 
      inboundStb_i : in std_logic;
146 
      inboundAdr_i : in std_logic_vector(7 downto 0);
147 
      inboundDat_i : in std_logic_vector(31 downto 0);
148 
      inboundAck_o : out std_logic);
149 6 magro732 
  end component;
150 
 
151 39 magro732 
  component WriteClassInbound is
152 
    generic(
153 
      EXTENDED_ADDRESS : natural range 0 to 2 := 0);
154 
    port(
155 
      clk : in std_logic;
156 
      areset_n : in std_logic;
157 
      enable : in std_logic;
158 6 magro732 
 
159 39 magro732 
      ready_o : out std_logic;
160 45 magro732 
      responseNeeded_o : out std_logic;
161 39 magro732 
      vc_o : out std_logic;
162 
      crf_o : out std_logic;
163 
      prio_o : out std_logic_vector(1 downto 0);
164 
      tt_o : out std_logic_vector(1 downto 0);
165 
      dstId_o : out std_logic_vector(31 downto 0);
166 
      srcId_o : out std_logic_vector(31 downto 0);
167 
      tid_o : out std_logic_vector(7 downto 0);
168 
      address_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
169 44 magro732 
      length_o : out std_logic_vector(4 downto 0);
170 39 magro732 
      select_o : out std_logic_vector(7 downto 0);
171 44 magro732 
      payloadRead_i : in std_logic;
172 
      payloadIndex_i : in std_logic_vector(4 downto 0);
173 
      payload_o : out std_logic_vector(63 downto 0);
174 39 magro732 
      done_i : in std_logic;
175 
 
176 45 magro732 
      inboundCyc_i : in std_logic;
177 
      inboundStb_i : in std_logic;
178 
      inboundAdr_i : in std_logic_vector(7 downto 0);
179 
      inboundDat_i : in std_logic_vector(31 downto 0);
180 
      inboundAck_o : out std_logic);
181 39 magro732 
  end component;
182 6 magro732 
 
183 39 magro732 
  component ResponseClassOutbound is
184 
    port(
185 
      clk : in std_logic;
186 
      areset_n : in std_logic;
187 
      enable : in std_logic;
188 6 magro732 
 
189 39 magro732 
      ready_i : in std_logic;
190 
      vc_i : in std_logic;
191 
      crf_i : in std_logic;
192 
      prio_i : in std_logic_vector(1 downto 0);
193 
      tt_i : in std_logic_vector(1 downto 0);
194 
      dstid_i : in std_logic_vector(31 downto 0);
195 
      srcid_i : in std_logic_vector(31 downto 0);
196 
      tid_i : in std_logic_vector(7 downto 0);
197 
      error_i : in std_logic;
198 
      payloadPresent_i :  in std_logic;
199 44 magro732 
      payloadLength_i : in std_logic_vector(4 downto 0);
200 39 magro732 
      payloadWrite_i : in std_logic;
201 44 magro732 
      payloadIndex_i : in std_logic_vector(4 downto 0);
202 
      payload_i : in std_logic_vector(63 downto 0);
203 39 magro732 
      done_o : out std_logic;
204 
 
205 45 magro732 
      outboundCyc_o : out std_logic;
206 
      outboundStb_o : out std_logic;
207 
      outboundDat_o : out std_logic_vector(31 downto 0);
208 
      outboundAck_i : in std_logic);
209 39 magro732 
  end component;
210 6 magro732 
 
211 45 magro732 
  constant PORTS : natural := 2;
212 
 
213 44 magro732 
  type StateType is (IDLE,
214 
                     REQUEST_CLASS, REQUEST_CLASS_RESPONSE,
215 45 magro732 
                     WRITE_CLASS, WRITE_CLASS_ACCESS, WRITE_CLASS_ACK, WRITE_CLASS_RESPONSE);
216 44 magro732 
  signal state : StateType;
217 
 
218 
  signal adr : std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
219 
  signal datOut : std_logic_vector(63 downto 0);
220 
 
221 
  signal payloadUpdate : std_logic;
222 
  signal payloadIndex : std_logic_vector(4 downto 0);
223 
 
224 
  signal requestReady : std_logic;
225 
  signal requestVc : std_logic;
226 
  signal requestCrf : std_logic;
227 
  signal requestPrio : std_logic_vector(1 downto 0);
228 
  signal requestTt : std_logic_vector(1 downto 0);
229 
  signal requestDstId : std_logic_vector(31 downto 0);
230 
  signal requestSrcId : std_logic_vector(31 downto 0);
231 
  signal requestTid : std_logic_vector(7 downto 0);
232 
  signal requestAddress : std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
233 
  signal requestLength : std_logic_vector(4 downto 0);
234 
  signal requestSelect : std_logic_vector(7 downto 0);
235 
  signal requestDone : std_logic;
236 
  signal requestAck : std_logic;
237 
 
238 
  signal writeReady : std_logic;
239 45 magro732 
  signal writeResponse : std_logic;
240 44 magro732 
  signal writeVc : std_logic;
241 
  signal writeCrf : std_logic;
242 
  signal writePrio : std_logic_vector(1 downto 0);
243 
  signal writeTt : std_logic_vector(1 downto 0);
244 
  signal writeDstId : std_logic_vector(31 downto 0);
245 
  signal writeSrcId : std_logic_vector(31 downto 0);
246 
  signal writeTid : std_logic_vector(7 downto 0);
247 
  signal writeAddress : std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
248 
  signal writeLength : std_logic_vector(4 downto 0);
249 
  signal writeSelect : std_logic_vector(7 downto 0);
250 
  signal writePayload : std_logic_vector(63 downto 0);
251 
  signal writeDone : std_logic;
252 
  signal writeAck : std_logic;
253 
 
254 
  signal responseReady : std_logic;
255 
  signal responseVc : std_logic;
256 
  signal responseCrf : std_logic;
257 
  signal responsePrio : std_logic_vector(1 downto 0);
258 
  signal responseTt : std_logic_vector(1 downto 0);
259 
  signal responseDstId : std_logic_vector(31 downto 0);
260 
  signal responseSrcId : std_logic_vector(31 downto 0);
261 
  signal responseTid : std_logic_vector(7 downto 0);
262 
  signal responseError : std_logic;
263 
  signal responsePayloadPresent : std_logic;
264 
  signal responsePayload : std_logic_vector(63 downto 0);
265 
  signal responseDone : std_logic;
266 
 
267 46 magro732 
  signal readRequestInbound : std_logic;
268 
  signal writeRequestInbound : std_logic;
269 
  signal vcInbound : std_logic;
270 
  signal crfInbound : std_logic;
271 
  signal prioInbound : std_logic_vector(1 downto 0);
272 
  signal ttInbound : std_logic_vector(1 downto 0);
273 
  signal dstIdInbound : std_logic_vector(31 downto 0);
274 
  signal srcIdInbound : std_logic_vector(31 downto 0);
275 47 magro732 
  signal sizeInbound : std_logic_vector(3 downto 0);
276 46 magro732 
  signal tidInbound : std_logic_vector(7 downto 0);
277 
  signal offsetInbound : std_logic_vector(20 downto 0);
278 
  signal wdptrInbound : std_logic;
279 47 magro732 
  signal payloadLengthInbound : std_logic_vector(2 downto 0);
280 
  signal payloadInbound : std_logic_vector(63 downto 0);
281 46 magro732 
 
282 
  signal readResponseMaint : std_logic;
283 
  signal writeResponseMaint : std_logic;
284 47 magro732 
  signal statusMaint : std_logic_vector(3 downto 0);
285 
  signal payloadLengthMaint : std_logic_vector(2 downto 0);
286 
  signal payloadIndexMaint : std_logic_vector(2 downto 0);
287 
  signal payloadMaint : std_logic_vector(63 downto 0);
288 46 magro732 
  signal doneMaint : std_logic;
289 
 
290 47 magro732 
  signal payloadIndexOutbound : std_logic_vector(2 downto 0);
291 46 magro732 
  signal doneOutbound : std_logic;
292 
 
293 45 magro732 
  signal configStb : std_logic;
294 
  signal configWe : std_logic;
295 
  signal configAdr : std_logic_vector(21 downto 0);
296 
  signal configAdrByte : std_logic_vector(23 downto 0);
297 
  signal configDatWrite : std_logic_vector(31 downto 0);
298 
  signal configDatRead : std_logic_vector(31 downto 0);
299 
  signal configAck : std_logic;
300 
  signal maintenanceAck : std_logic;
301 
 
302 44 magro732 
  signal inboundCyc : std_logic;
303 
  signal inboundStb : std_logic;
304 
  signal inboundAdr : std_logic_vector(7 downto 0);
305 
  signal inboundDat : std_logic_vector(31 downto 0);
306 
  signal inboundAck : std_logic;
307 
 
308 45 magro732 
  signal outboundCyc : std_logic_vector(PORTS-1 downto 0);
309 
  signal outboundStb : std_logic_vector(PORTS-1 downto 0);
310 
  signal outboundDat : std_logic_vector(32*PORTS-1 downto 0);
311 
  signal outboundAck : std_logic_vector(PORTS-1 downto 0);
312 39 magro732 
 
313 
begin
314 
 
315 44 magro732 
  responseVc <= requestVc when (responsePayloadPresent = '1') else writeVc;
316 
  responseCrf <= requestCrf when (responsePayloadPresent = '1') else writeCrf;
317 
  responsePrio <= requestPrio when (responsePayloadPresent = '1') else writePrio;
318 
  responseTt <= requestTt when (responsePayloadPresent = '1') else writeTt;
319 
  responseDstId <= requestSrcId when (responsePayloadPresent = '1') else writeSrcId;
320 
  responseSrcId <= requestDstId when (responsePayloadPresent = '1') else writeDstId;
321 
  responseTid <= requestTid when (responsePayloadPresent = '1') else writeTid;
322 
 
323 6 magro732 
  -----------------------------------------------------------------------------
324 39 magro732 
  --
325 6 magro732 
  -----------------------------------------------------------------------------
326 39 magro732 
  adr_o <= adr;
327 
  dat_o <= datOut;
328 
 
329 
  Bridge: process(clk, areset_n)
330 6 magro732 
  begin
331 39 magro732 
    if (areset_n = '0') then
332 
      cyc_o <= '0';
333 
      stb_o <= '0';
334 
      we_o <= '0';
335 
      adr <= (others=>'0');
336 
      datOut <= (others=>'0');
337 6 magro732 
 
338 44 magro732 
      payloadUpdate <= '0';
339 
      payloadIndex <= (others=>'0');
340 
 
341 39 magro732 
      requestDone <= '0';
342 
 
343 44 magro732 
      writeDone <= '0';
344 
 
345 
      responseReady <= '0';
346 
      responseError <= '0';
347 
      responsePayloadPresent <= '0';
348 
      responsePayload <= (others=>'0');
349 39 magro732 
    elsif (clk'event and clk = '1') then
350 44 magro732 
      if (enable = '1') then
351 
        requestDone <= '0';
352 
        writeDone <= '0';
353 
        responseReady <= '0';
354 
 
355 
        payloadUpdate <= '0';
356 
        if (payloadUpdate = '1') then
357 
          payloadIndex <= std_logic_vector(unsigned(payloadIndex) + 1);
358 
        end if;
359 
 
360 
        case state is
361 
          when IDLE =>
362 
            ---------------------------------------------------------------------
363 
            --
364 
            ---------------------------------------------------------------------
365 
            if (requestReady = '1') then
366 
              cyc_o <= '1';
367 
              stb_o <= '1';
368 
              we_o <= '0';
369 
              adr <= requestAddress;
370 
              sel_o <= requestSelect;
371 
 
372 
              payloadIndex <= (others=>'0');
373 
 
374 
              responsePayloadPresent <= '1';
375 
              state <= REQUEST_CLASS;
376 
            elsif (writeReady = '1') then
377 
              adr <= writeAddress;
378 39 magro732 
 
379 44 magro732 
              payloadUpdate <= '1';
380 
              payloadIndex <= (others=>'0');
381 
 
382 
              responsePayloadPresent <= '0';
383 
              state <= WRITE_CLASS;
384 
            end if;
385 39 magro732 
 
386 44 magro732 
          when REQUEST_CLASS =>
387 
            ---------------------------------------------------------------------
388 
            --
389 
            ---------------------------------------------------------------------
390 
            if (ack_i = '1') then
391 
              -- Note that responsePayloadIndex is updated after the write has been made.
392 
              payloadUpdate <= '1';
393 
              responsePayload <= dat_i;
394 
 
395 39 magro732 
              adr <= std_logic_vector(unsigned(adr) + 1);
396 44 magro732 
 
397 
              if (payloadIndex = requestLength) then
398 
                requestDone <= '1';
399 
                cyc_o <= '0';
400 
                stb_o <= '0';
401 
                state <= REQUEST_CLASS_RESPONSE;
402 
              end if;
403 39 magro732 
--          elsif(err_i = '1') then
404 
--            REMARK: Implement error indication from wb-bus...
405 44 magro732 
            end if;
406 39 magro732 
 
407 44 magro732 
          when REQUEST_CLASS_RESPONSE =>
408 
            ---------------------------------------------------------------------
409 
            --
410 
            ---------------------------------------------------------------------
411 
            if (responseDone = '1') then
412 
              responseReady <= '0';
413 
              state <= IDLE;
414 
            else
415 
              responseReady <= '1';
416 
            end if;
417 6 magro732 
 
418 44 magro732 
          when WRITE_CLASS =>
419 
            ---------------------------------------------------------------------
420 
            --
421 
            ---------------------------------------------------------------------
422 45 magro732 
            state <= WRITE_CLASS_ACCESS;
423 
 
424 
          when WRITE_CLASS_ACCESS =>
425 
            ---------------------------------------------------------------------
426 
            --
427 
            ---------------------------------------------------------------------
428 
            cyc_o <= '1';
429 
            stb_o <= '1';
430 
            we_o <= '1';
431 
            sel_o <= writeSelect;
432 
            datOut <= writePayload;
433 
            payloadUpdate <= '1';
434 
 
435 
            state <= WRITE_CLASS_ACK;
436 
 
437 
          when WRITE_CLASS_ACK =>
438 
            ---------------------------------------------------------------------
439 
            --
440 
            ---------------------------------------------------------------------
441 44 magro732 
            if (ack_i = '1') then
442 
              adr <= std_logic_vector(unsigned(adr) + 1);
443 
 
444 45 magro732 
              if (unsigned(payloadIndex) /= (unsigned(writeLength)+2)) then
445 
                stb_o <= '0';
446 
                state <= WRITE_CLASS_ACCESS;
447 44 magro732 
              else
448 
                writeDone <= '1';
449 
                cyc_o <= '0';
450 
                stb_o <= '0';
451 
                state <= WRITE_CLASS_RESPONSE;
452 
              end if;
453 
            end if;
454 
 
455 
          when WRITE_CLASS_RESPONSE =>
456 
            ---------------------------------------------------------------------
457 
            --
458 
            ---------------------------------------------------------------------
459 45 magro732 
            if (responseDone = '1') or (writeResponse = '0') then
460 44 magro732 
              responseReady <= '0';
461 
              state <= IDLE;
462 39 magro732 
            else
463 44 magro732 
              responseReady <= '1';
464 39 magro732 
            end if;
465 6 magro732 
 
466 44 magro732 
          when others =>
467 6 magro732 
 
468 44 magro732 
        end case;
469 
      end if;
470 39 magro732 
    end if;
471 
  end process;
472 
 
473 
  -----------------------------------------------------------------------------
474 45 magro732 
  -- Packet handlers.
475 39 magro732 
  -----------------------------------------------------------------------------
476 6 magro732 
 
477 39 magro732 
  RequestClassInboundInst: RequestClassInbound
478 
    generic map(
479 
      EXTENDED_ADDRESS=>EXTENDED_ADDRESS)
480 
    port map(
481 
      clk=>clk,
482 
      areset_n=>areset_n,
483 
      enable=>enable,
484 
      ready_o=>requestReady,
485 
      vc_o=>requestVc,
486 
      crf_o=>requestCrf,
487 
      prio_o=>requestPrio,
488 
      tt_o=>requestTt,
489 
      dstId_o=>requestDstId,
490 
      srcId_o=>requestSrcId,
491 
      tid_o=>requestTid,
492 
      address_o=>requestAddress,
493 44 magro732 
      length_o=>requestLength,
494 39 magro732 
      select_o=>requestSelect,
495 
      done_i=>requestDone,
496 45 magro732 
      inboundCyc_i=>inboundCyc,
497 
      inboundStb_i=>inboundStb,
498 
      inboundAdr_i=>inboundAdr,
499 
      inboundDat_i=>inboundDat,
500 
      inboundAck_o=>requestAck);
501 6 magro732 
 
502 39 magro732 
  WriteClassInboundInst: WriteClassInbound
503 
    generic map(
504 
      EXTENDED_ADDRESS=>EXTENDED_ADDRESS)
505 
    port map(
506 
      clk=>clk,
507 
      areset_n=>areset_n,
508 
      enable=>enable,
509 
      ready_o=>writeReady,
510 45 magro732 
      responseNeeded_o=>writeResponse,
511 39 magro732 
      vc_o=>writeVc,
512 
      crf_o=>writeCrf,
513 
      prio_o=>writePrio,
514 
      tt_o=>writeTt,
515 
      dstId_o=>writeDstId,
516 
      srcId_o=>writeSrcId,
517 
      tid_o=>writeTid,
518 
      address_o=>writeAddress,
519 
      length_o=>writeLength,
520 
      select_o=>writeSelect,
521 44 magro732 
      payloadRead_i=>payloadUpdate,
522 
      payloadIndex_i=>payloadIndex,
523 39 magro732 
      payload_o=>writePayload,
524 
      done_i=>writeDone,
525 45 magro732 
      inboundCyc_i=>inboundCyc,
526 
      inboundStb_i=>inboundStb,
527 
      inboundAdr_i=>inboundAdr,
528 
      inboundDat_i=>inboundDat,
529 
      inboundAck_o=>writeAck);
530 6 magro732 
 
531 39 magro732 
  ResponseClassOutboundInst: ResponseClassOutbound
532 
    port map(
533 
      clk=>clk,
534 
      areset_n=>areset_n,
535 
      enable=>enable,
536 
      ready_i=>responseReady,
537 44 magro732 
      vc_i=>responseVc,
538 
      crf_i=>responseCrf,
539 
      prio_i=>responsePrio,
540 
      tt_i=>responseTt,
541 
      dstid_i=>responseDstId,
542 
      srcid_i=>responseSrcId,
543 
      tid_i=>responseTid,
544 39 magro732 
      error_i=>responseError,
545 
      payloadPresent_i=>responsePayloadPresent,
546 44 magro732 
      payloadLength_i=>requestLength,
547 
      payloadWrite_i=>payloadUpdate,
548 
      payloadIndex_i=>payloadIndex,
549 39 magro732 
      payload_i=>responsePayload,
550 
      done_o=>responseDone,
551 45 magro732 
      outboundCyc_o=>outboundCyc(0),
552 
      outboundStb_o=>outboundStb(0),
553 
      outboundDat_o=>outboundDat(31 downto 0),
554 
      outboundAck_i=>outboundAck(0));
555 44 magro732 
 
556 46 magro732 
  -----------------------------------------------------------------------------
557 45 magro732 
  -- Maintenance packet processing.
558 46 magro732 
  -----------------------------------------------------------------------------
559 
  InboundMaintenance: MaintenanceInbound
560 45 magro732 
    port map(
561 46 magro732 
      clk=>clk, areset_n=>areset_n, enable=>enable,
562 
      readRequestReady_o=>readRequestInbound,
563 
      writeRequestReady_o=>writeRequestInbound,
564 
      readResponseReady_o=>open,
565 
      writeResponseReady_o=>open,
566 
      portWriteReady_o=>open,
567 
      vc_o=>vcInbound,
568 
      crf_o=>crfInbound,
569 
      prio_o=>prioInbound,
570 
      tt_o=>ttInbound,
571 
      dstid_o=>dstIdInbound,
572 47 magro732 
      srcid_o=>srcIdInbound,
573 
      size_o=>sizeInbound,
574 
      status_o=>open,
575 46 magro732 
      tid_o=>tidInbound,
576 
      hop_o=>open,
577 
      offset_o=>offsetInbound,
578 
      wdptr_o=>wdptrInbound,
579 
      payloadLength_o=>payloadLengthInbound,
580 
      payloadIndex_i=>payloadIndexMaint,
581 
      payload_o=>payloadInbound,
582 
      done_i=>doneMaint,
583 
      inboundCyc_i=>inboundCyc,
584 
      inboundStb_i=>inboundStb,
585 
      inboundAdr_i=>inboundAdr,
586 
      inboundDat_i=>inboundDat,
587 
      inboundAck_o=>maintenanceAck);
588 
 
589 
  OutboundMaintenance: MaintenanceOutbound
590 
    port map(
591 
      clk=>clk, areset_n=>areset_n, enable=>enable,
592 
      readRequestReady_i=>'0',
593 
      writeRequestReady_i=>'0',
594 
      readResponseReady_i=>readResponseMaint,
595 
      writeResponseReady_i=>writeResponseMaint,
596 
      portWriteReady_i=>'0',
597 
      vc_i=>vcInbound,
598 
      crf_i=>crfInbound,
599 
      prio_i=>prioInbound,
600 
      tt_i=>ttInbound,
601 
      dstid_i=>srcIdInbound,
602 
      srcid_i=>dstIdInbound,
603 47 magro732 
      size_i=>(others=>'0'),
604 
      status_i=>statusMaint,
605 46 magro732 
      tid_i=>tidInbound,
606 
      hop_i=>x"ff",
607 
      offset_i=>(others=>'0'),
608 47 magro732 
      wdptr_i=>'0',
609 46 magro732 
      payloadLength_i=>payloadLengthMaint,
610 
      payloadIndex_o=>payloadIndexOutbound,
611 
      payload_i=>payloadMaint,
612 
      done_o=>doneOutbound,
613 
      outboundCyc_o=>outboundCyc(1),
614 
      outboundStb_o=>outboundStb(1),
615 
      outboundDat_o=>outboundDat(63 downto 32),
616 45 magro732 
      outboundAck_i=>outboundAck(1));
617 
 
618 46 magro732 
  MaintenanceBridge: RioLogicalMaintenance
619 
    port map(
620 
      clk=>clk, areset_n=>areset_n, enable=>enable,
621 
      readRequestReady_i=>readRequestInbound,
622 47 magro732 
      writeRequestReady_i=>writeRequestInbound,
623 
      size_i=>sizeInbound,
624 46 magro732 
      offset_i=>offsetInbound,
625 
      wdptr_i=>wdptrInbound,
626 
      payloadLength_i=>payloadLengthInbound,
627 
      payloadIndex_o=>payloadIndexMaint,
628 
      payload_i=>payloadInbound,
629 
      done_o=>doneMaint,
630 
      readResponseReady_o=>readResponseMaint,
631 
      writeResponseReady_o=>writeResponseMaint,
632 47 magro732 
      status_o=>statusMaint,
633 46 magro732 
      payloadLength_o=>payloadLengthMaint,
634 
      payloadIndex_i=>payloadIndexOutbound,
635 
      payload_o=>payloadMaint,
636 
      done_i=>doneOutbound,
637 
      configStb_o=>configStb,
638 
      configWe_o=>configWe,
639 
      configAdr_o=>configAdr,
640 
      configDat_o=>configDatWrite,
641 
      configDat_i=>configDatRead,
642 
      configAck_i=>configAck);
643 
 
644 45 magro732 
  -----------------------------------------------------------------------------
645 
  -- Common interface toward the packet queues.
646 
  -----------------------------------------------------------------------------
647 
 
648 
  inboundAck <= requestAck or writeAck or maintenanceAck;
649 39 magro732 
  RioLogicalCommonInst: RioLogicalCommon
650 45 magro732 
    generic map(PORTS=>PORTS)
651 39 magro732 
    port map(
652 
      clk=>clk,
653 
      areset_n=>areset_n,
654 
      enable=>enable,
655 
      readFrameEmpty_i=>readFrameEmpty_i,
656 
      readFrame_o=>readFrame_o,
657 
      readContent_o=>readContent_o,
658 
      readContentEnd_i=>readContentEnd_i,
659 
      readContentData_i=>readContentData_i,
660 
      writeFrameFull_i=>writeFrameFull_i,
661 
      writeFrame_o=>writeFrame_o,
662 
      writeFrameAbort_o=>writeFrameAbort_o,
663 
      writeContent_o=>writeContent_o,
664 
      writeContentData_o=>writeContentData_o,
665 45 magro732 
      inboundCyc_o=>inboundCyc,
666 
      inboundStb_o=>inboundStb,
667 
      inboundAdr_o=>inboundAdr,
668 
      inboundDat_o=>inboundDat,
669 
      inboundAck_i=>inboundAck,
670 
      outboundCyc_i=>outboundCyc,
671 
      outboundStb_i=>outboundStb,
672 
      outboundDat_i=>outboundDat,
673 
      outboundAck_o=>outboundAck);
674 6 magro732 
 
675 39 magro732 
  -----------------------------------------------------------------------------
676 
  -- Configuration memory.
677 
  -----------------------------------------------------------------------------
678 45 magro732 
  configAdrByte <= configAdr & "00";
679 
  memoryConfig : process(clk, areset_n)
680 
    variable componentTag : std_logic_vector(31 downto 0);
681 
    variable hostBaseDeviceIdLocked : std_logic;
682 
    variable hostBaseDeviceId : std_logic_vector(15 downto 0);
683 
  begin
684 
    if (areset_n = '0') then
685 
      componentTag := (others => '0');
686 
      hostBaseDeviceIdLocked := '0';
687 
      hostBaseDeviceId := (others => '1');
688 6 magro732 
 
689 45 magro732 
      configDatRead <= (others => '0');
690 
      configAck <= '0';
691 
    elsif (clk'event and clk = '1') then
692 
      if (configAck = '0') then
693 
        if (configStb = '1') then
694 
          configAck <= '1';
695 
          configDatRead <= (others=>'0');
696 
 
697 
          -- Check the address the access is for.
698 
          case (configAdrByte) is
699 
            when x"000000" =>
700 
              -----------------------------------------------------------------
701 
              -- Device Identity CAR. Read-only.
702 
              -----------------------------------------------------------------
703 
              configDatRead(31 downto 16) <= DEVICE_IDENTITY;
704 
              configDatRead(15 downto 0) <= DEVICE_VENDOR_IDENTITY;
705 
 
706 
            when x"000004" =>
707 
              -----------------------------------------------------------------
708 
              -- Device Information CAR. Read-only.
709 
              -----------------------------------------------------------------
710 
              configDatRead(31 downto 0) <= DEVICE_REV;
711 
 
712 
            when x"000008" =>
713 
              -----------------------------------------------------------------
714 
              -- Assembly Identity CAR. Read-only.
715 
              -----------------------------------------------------------------
716 
              configDatRead(31 downto 16) <= ASSY_IDENTITY;
717 
              configDatRead(15 downto 0) <= ASSY_VENDOR_IDENTITY;
718 
 
719 
            when x"00000c" =>
720 
              -----------------------------------------------------------------
721 
              -- Assembly Information CAR. Read-only.
722 
              -----------------------------------------------------------------
723 
              configDatRead(31 downto 16) <= ASSY_REV;
724 
 
725 
            when x"000010" =>
726 
              -----------------------------------------------------------------
727 
              -- Processing Element Features CAR. Read-only.
728 
              -----------------------------------------------------------------
729 
              -- Bridge.
730 
              configDatRead(31) <= '1';
731 
              -- Extended addressing support, 34-bit addresses.
732 
              configDatRead(2 downto 0) <= "001";
733 
 
734 
            when x"000018" =>
735 
              -----------------------------------------------------------------
736 
              -- Source Operations CAR. Read-only.
737 
              -----------------------------------------------------------------
738 
              -- Cannot act as a source of any packets.
739 
 
740 
            when x"00001c" =>
741 
              -----------------------------------------------------------------
742 
              -- Destination Operations CAR. Read-only.
743 
              -----------------------------------------------------------------
744 
              -- Read, supported.
745 
              configDatRead(15) <= '1';
746 
              -- Write, supported.
747 
              configDatRead(14) <= '1';
748 
              -- Write-with-response, supported.
749 
              configDatRead(12) <= '1';
750 
 
751 
            when x"00004c" =>
752 
              -----------------------------------------------------------------
753 
              -- Processing Element Logical Layer Control CSR.
754 
              -----------------------------------------------------------------
755 
              -- Extended addressing control, PE supports 34 bits addresses.
756 
              configDatRead(2 downto 0) <= "001";
757 6 magro732 
 
758 45 magro732 
            when x"000060" =>
759 
              -----------------------------------------------------------------
760 
              -- Base Device ID CSR.
761 
              -----------------------------------------------------------------
762 
              -- This is not used since this endpoint only replies to packets
763 
              -- and it can then use the destination deviceId as a source.
764 
 
765 
            when x"000068" =>
766 
              -----------------------------------------------------------------
767 
              -- Host Base Device ID Lock CSR.
768 
              -----------------------------------------------------------------
769 6 magro732 
 
770 45 magro732 
              -- Check if writing.
771 
              if (configWe = '1') then
772 
                -- Write access.
773 
 
774 
                -- Check if this field has been written before.
775 
                if (hostBaseDeviceIdLocked = '0') then
776 
                  -- The field has not been written.
777 
                  -- Lock the field and set the host base device id.
778 
                  hostBaseDeviceIdLocked := '1';
779 
                  hostBaseDeviceId := configDatWrite(15 downto 0);
780 
                else
781 
                  -- The field has been written.
782 
                  -- Check if the written data is the same as the stored.
783 
                  if (hostBaseDeviceId = configDatWrite(15 downto 0)) then
784 
                    -- Same as stored, reset the value to its initial value.
785 
                    hostBaseDeviceIdLocked := '0';
786 
                    hostBaseDeviceId := (others => '1');
787 
                  else
788 
                    -- Not writing the same as the stored value.
789 
                    -- Ignore the write.
790 
                  end if;
791 
                end if;
792 
              end if;
793 
 
794 
              configDatRead(15 downto 0) <= hostBaseDeviceId;
795 
 
796 
            when x"00006C" =>
797 
              -----------------------------------------------------------------
798 
              -- Component TAG CSR.
799 
              -----------------------------------------------------------------
800 
              if (configWe = '1') then
801 
                componentTag := configDatWrite;
802 
              end if;
803 
 
804 
              configDatRead <= componentTag;
805 
 
806 
            when others =>
807 
              -----------------------------------------------------------------
808 
              -- Other access.
809 
              -----------------------------------------------------------------
810 
              -- Respond with all zeros.
811 
              configDatRead <= (others => '0');
812 
          end case;
813 
        end if;
814 
      else
815 
        configAck <= '0';
816 
      end if;
817 
    end if;
818 
  end process;
819 
 
820 39 magro732 
end architecture;
821 6 magro732 
 
822 
 
823 39 magro732 
-------------------------------------------------------------------------------
824 
--
825 
-------------------------------------------------------------------------------
826 
-- REMARK: Extended addresses are not supported yet...
827 
library ieee;
828 
use ieee.std_logic_1164.all;
829 
use ieee.numeric_std.all;
830 
use work.rio_common.all;
831 6 magro732 
 
832 
 
833 39 magro732 
-------------------------------------------------------------------------------
834 
--
835 
-------------------------------------------------------------------------------
836 
entity RequestClassInbound is
837 
  generic(
838 
    EXTENDED_ADDRESS : natural range 0 to 2 := 0);
839 
  port(
840 
    clk : in std_logic;
841 
    areset_n : in std_logic;
842 
    enable : in std_logic;
843 6 magro732 
 
844 39 magro732 
    ready_o : out std_logic;
845 
    vc_o : out std_logic;
846 
    crf_o : out std_logic;
847 
    prio_o : out std_logic_vector(1 downto 0);
848 
    tt_o : out std_logic_vector(1 downto 0);
849 
    dstId_o : out std_logic_vector(31 downto 0);
850 
    srcId_o : out std_logic_vector(31 downto 0);
851 
    tid_o : out std_logic_vector(7 downto 0);
852 
    address_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
853 44 magro732 
    length_o : out std_logic_vector(4 downto 0);
854 39 magro732 
    select_o : out std_logic_vector(7 downto 0);
855 
    done_i : in std_logic;
856 
 
857 45 magro732 
    inboundCyc_i : in std_logic;
858 
    inboundStb_i : in std_logic;
859 
    inboundAdr_i : in std_logic_vector(7 downto 0);
860 
    inboundDat_i : in std_logic_vector(31 downto 0);
861 
    inboundAck_o : out std_logic);
862 39 magro732 
end entity;
863 
 
864 
 
865 
-------------------------------------------------------------------------------
866 
--
867 
-------------------------------------------------------------------------------
868 
architecture RequestClassInbound of RequestClassInbound is
869 
  type StateType is (RECEIVE_PACKET, READY);
870 
  signal state : StateType;
871 
 
872 
  signal rdsize : std_logic_vector(3 downto 0);
873 
  signal wdptr : std_logic;
874 
 
875 45 magro732 
  signal inboundAck : std_logic;
876 39 magro732 
  signal complete : std_logic;
877 
 
878 45 magro732 
  signal packetIndex : natural range 0 to 69;
879 39 magro732 
 
880 
begin
881 
 
882 45 magro732 
  inboundAck_o <= inboundAck;
883 39 magro732 
 
884 
  ready_o <= complete when (state = READY) else '0';
885 
 
886 
  RequestClass: process(clk, areset_n)
887 
  begin
888 
    if (areset_n = '0') then
889 44 magro732 
      state <= RECEIVE_PACKET;
890 
 
891 
      rdsize <= (others=>'0');
892 
      wdptr <= '0';
893 
 
894 45 magro732 
      inboundAck <= '0';
895 39 magro732 
      complete <= '0';
896 
 
897 44 magro732 
      packetIndex <= 0;
898 
 
899 39 magro732 
      vc_o <= '0';
900 
      crf_o <= '0';
901 
      prio_o <= "00";
902 
      tt_o <= "00";
903 44 magro732 
      dstId_o <= (others=>'0');
904 
      srcId_o <= (others=>'0');
905 
      tid_o <= (others=>'0');
906 39 magro732 
      address_o <= (others=>'0');
907 
    elsif (clk'event and clk = '1') then
908 
      case state is
909 
        when RECEIVE_PACKET =>
910 
          ---------------------------------------------------------------------
911 
          -- This state waits for a new REQUEST class packet, receives it
912 
          -- and parses it.
913 
          ---------------------------------------------------------------------
914 45 magro732 
          if (inboundCyc_i = '1') then
915 
            if (inboundAck = '0') then
916 
              if (inboundStb_i = '1') then
917 
                if (inboundAdr_i = x"24") then
918 39 magro732 
                  -------------------------------------------------------------
919 
                  -- NREAD packet parser.
920 
                  -------------------------------------------------------------
921 
                  case (packetIndex) is
922 
                    when 0 =>
923 
                      -- x"0000" & ackid & vc & crf & prio & tt & ftype
924 45 magro732 
                      vc_o <= inboundDat_i(9);
925 
                      crf_o <= inboundDat_i(8);
926 
                      prio_o <= inboundDat_i(7 downto 6);
927 
                      tt_o <= inboundDat_i(5 downto 4);
928 39 magro732 
                      packetIndex <= packetIndex + 1;
929 
                    when 1 =>
930 
                      -- dstid
931 45 magro732 
                      dstId_o <= inboundDat_i;
932 39 magro732 
                      packetIndex <= packetIndex + 1;
933 
                    when 2 =>
934 
                      -- srcid
935 45 magro732 
                      srcId_o <= inboundDat_i;
936 39 magro732 
                      packetIndex <= packetIndex + 1;
937 
                    when 3 =>
938 
                      -- transaction(3:0) & rdsize(3:0) & srcTID(7:0) & address(28:13)
939 45 magro732 
                      rdsize <= inboundDat_i(27 downto 24);
940 
                      tid_o <= inboundDat_i(23 downto 16);
941 
                      address_o(28 downto 13) <= inboundDat_i(15 downto 0);
942 39 magro732 
                      packetIndex <= packetIndex + 1;
943 
                    when 4 =>
944 
                      -- address(12:0) & wdptr & xamsbs(1:0) & crc(15:0)
945 45 magro732 
                      address_o(12 downto 0) <= inboundDat_i(31 downto 19);
946 
                      wdptr <= inboundDat_i(18);
947 
                      address_o(30 downto 29) <= inboundDat_i(17 downto 16);
948 39 magro732 
                      packetIndex <= packetIndex + 1;
949 
                      complete <= '1';
950 
                    when others =>
951 
                      -- There should be no more content in an NREAD.
952 
                      -- Discard.
953 
                  end case;
954 45 magro732 
                  inboundAck <= '1';
955 6 magro732 
                end if;
956 
              end if;
957 
            else
958 45 magro732 
              inboundAck <= '0';
959 6 magro732 
            end if;
960 
          else
961 39 magro732 
            if (complete = '1') then
962 
              state <= READY;
963 6 magro732 
            end if;
964 39 magro732 
            packetIndex <= 0;
965 6 magro732 
          end if;
966 
 
967 39 magro732 
        when READY =>
968 
          ---------------------------------------------------------------------
969 
          -- Wait for the handler of the packet to signal that it has been
970 
          -- processed.
971 
          ---------------------------------------------------------------------
972 
          if (done_i = '1') then
973 
            complete <= '0';
974 
            state <= RECEIVE_PACKET;
975 6 magro732 
          end if;
976 
 
977 39 magro732 
        when others =>
978 
          ---------------------------------------------------------------------
979 
          --
980 
          ---------------------------------------------------------------------
981 6 magro732 
 
982 39 magro732 
      end case;
983 
    end if;
984 
  end process;
985 
 
986 
  -----------------------------------------------------------------------------
987 
  -- Transformation of rdsize and wdptr into length of access and byte lanes.
988 
  -----------------------------------------------------------------------------
989 
 
990 
  process(clk, areset_n)
991 
  begin
992 
    if (areset_n = '0') then
993 44 magro732 
      length_o <= "00000";
994 39 magro732 
      select_o <= (others=>'0');
995 
    elsif (clk'event and clk = '1') then
996 
      if (complete = '1') then
997 
        if (wdptr = '0') then
998 
          case rdsize is
999 
            when "0000" =>
1000 44 magro732 
              length_o <= "00000";
1001 39 magro732 
              select_o <= "10000000";
1002 
            when "0001" =>
1003 44 magro732 
              length_o <= "00000";
1004 39 magro732 
              select_o <= "01000000";
1005 
            when "0010" =>
1006 44 magro732 
              length_o <= "00000";
1007 39 magro732 
              select_o <= "00100000";
1008 
            when "0011" =>
1009 44 magro732 
              length_o <= "00000";
1010 39 magro732 
              select_o <= "00010000";
1011 
            when "0100" =>
1012 44 magro732 
              length_o <= "00000";
1013 39 magro732 
              select_o <= "11000000";
1014 
            when "0101" =>
1015 44 magro732 
              length_o <= "00000";
1016 39 magro732 
              select_o <= "11100000";
1017 
            when "0110" =>
1018 44 magro732 
              length_o <= "00000";
1019 39 magro732 
              select_o <= "00110000";
1020 
            when "0111" =>
1021 44 magro732 
              length_o <= "00000";
1022 39 magro732 
              select_o <= "11111000";
1023 
            when "1000" =>
1024 44 magro732 
              length_o <= "00000";
1025 39 magro732 
              select_o <= "11110000";
1026 
            when "1001" =>
1027 44 magro732 
              length_o <= "00000";
1028 39 magro732 
              select_o <= "11111100";
1029 
            when "1010" =>
1030 44 magro732 
              length_o <= "00000";
1031 39 magro732 
              select_o <= "11111110";
1032 
            when "1011" =>
1033 44 magro732 
              length_o <= "00000";
1034 39 magro732 
              select_o <= "11111111";
1035 
            when "1100" =>
1036 44 magro732 
              length_o <= "00011";
1037 39 magro732 
              select_o <= "11111111";
1038 
            when "1101" =>
1039 44 magro732 
              length_o <= "01011";
1040 39 magro732 
              select_o <= "11111111";
1041 
            when "1110" =>
1042 44 magro732 
              length_o <= "10011";
1043 39 magro732 
              select_o <= "11111111";
1044 
            when others =>
1045 44 magro732 
              length_o <= "11011";
1046 39 magro732 
              select_o <= "11111111";
1047 
          end case;
1048 
        else
1049 
          case rdsize is
1050 
            when "0000" =>
1051 44 magro732 
              length_o <= "00000";
1052 39 magro732 
              select_o <= "00001000";
1053 
            when "0001" =>
1054 44 magro732 
              length_o <= "00000";
1055 39 magro732 
              select_o <= "00000100";
1056 
            when "0010" =>
1057 44 magro732 
              length_o <= "00000";
1058 39 magro732 
              select_o <= "00000010";
1059 
            when "0011" =>
1060 44 magro732 
              length_o <= "00000";
1061 39 magro732 
              select_o <= "00000001";
1062 
            when "0100" =>
1063 44 magro732 
              length_o <= "00000";
1064 39 magro732 
              select_o <= "00001100";
1065 
            when "0101" =>
1066 44 magro732 
              length_o <= "00000";
1067 39 magro732 
              select_o <= "00000111";
1068 
            when "0110" =>
1069 44 magro732 
              length_o <= "00000";
1070 39 magro732 
              select_o <= "00000011";
1071 
            when "0111" =>
1072 44 magro732 
              length_o <= "00000";
1073 39 magro732 
              select_o <= "00011111";
1074 
            when "1000" =>
1075 44 magro732 
              length_o <= "00000";
1076 39 magro732 
              select_o <= "00001111";
1077 
            when "1001" =>
1078 44 magro732 
              length_o <= "00000";
1079 39 magro732 
              select_o <= "00111111";
1080 
            when "1010" =>
1081 44 magro732 
              length_o <= "00000";
1082 39 magro732 
              select_o <= "01111111";
1083 
            when "1011" =>
1084 44 magro732 
              length_o <= "00001";
1085 39 magro732 
              select_o <= "11111111";
1086 
            when "1100" =>
1087 44 magro732 
              length_o <= "00111";
1088 39 magro732 
              select_o <= "11111111";
1089 
            when "1101" =>
1090 44 magro732 
              length_o <= "01111";
1091 39 magro732 
              select_o <= "11111111";
1092 
            when "1110" =>
1093 44 magro732 
              length_o <= "10111";
1094 39 magro732 
              select_o <= "11111111";
1095 
            when others =>
1096 44 magro732 
              length_o <= "11111";
1097 39 magro732 
              select_o <= "11111111";
1098 
          end case;
1099 
        end if;
1100 
      end if;
1101 
    end if;
1102 
  end process;
1103 
 
1104 
end architecture;
1105 
 
1106 
 
1107 
-------------------------------------------------------------------------------
1108 
--
1109 
-------------------------------------------------------------------------------
1110 
library ieee;
1111 
use ieee.std_logic_1164.all;
1112 
use ieee.numeric_std.all;
1113 
use work.rio_common.all;
1114 
 
1115 
 
1116 
-------------------------------------------------------------------------------
1117 
--
1118 
-------------------------------------------------------------------------------
1119 
entity WriteClassInbound is
1120 
  generic(
1121 
    EXTENDED_ADDRESS : natural range 0 to 2 := 0);
1122 
  port(
1123 
    clk : in std_logic;
1124 
    areset_n : in std_logic;
1125 
    enable : in std_logic;
1126 
 
1127 
    ready_o : out std_logic;
1128 45 magro732 
    responseNeeded_o : out std_logic;
1129 39 magro732 
    vc_o : out std_logic;
1130 
    crf_o : out std_logic;
1131 
    prio_o : out std_logic_vector(1 downto 0);
1132 
    tt_o : out std_logic_vector(1 downto 0);
1133 
    dstId_o : out std_logic_vector(31 downto 0);
1134 
    srcId_o : out std_logic_vector(31 downto 0);
1135 
    tid_o : out std_logic_vector(7 downto 0);
1136 
    address_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
1137 44 magro732 
    length_o : out std_logic_vector(4 downto 0);
1138 39 magro732 
    select_o : out std_logic_vector(7 downto 0);
1139 44 magro732 
    payloadRead_i : in std_logic;
1140 
    payloadIndex_i : in std_logic_vector(4 downto 0);
1141 
    payload_o : out std_logic_vector(63 downto 0);
1142 39 magro732 
    done_i : in std_logic;
1143 
 
1144 45 magro732 
    inboundCyc_i : in std_logic;
1145 
    inboundStb_i : in std_logic;
1146 
    inboundAdr_i : in std_logic_vector(7 downto 0);
1147 
    inboundDat_i : in std_logic_vector(31 downto 0);
1148 
    inboundAck_o : out std_logic);
1149 39 magro732 
end entity;
1150 
 
1151 
 
1152 
-------------------------------------------------------------------------------
1153 
--
1154 
-------------------------------------------------------------------------------
1155 
architecture WriteClassInbound of WriteClassInbound is
1156 
  type StateType is (RECEIVE_PACKET, READY);
1157 
  signal state : StateType;
1158 
 
1159 
  signal wdptr : std_logic;
1160 
  signal wrsize : std_logic_vector(3 downto 0);
1161 
 
1162 45 magro732 
  signal inboundAck : std_logic;
1163 39 magro732 
  signal complete : std_logic;
1164 
 
1165 45 magro732 
  signal packetIndex : natural range 0 to 69;
1166 39 magro732 
 
1167 44 magro732 
  signal doubleWord : std_logic_vector(63 downto 16);
1168 
 
1169 39 magro732 
  signal memoryWrite : std_logic;
1170 
  signal memoryAddress : std_logic_vector(4 downto 0);
1171 
  signal memoryDataIn : std_logic_vector(63 downto 0);
1172 
 
1173 44 magro732 
 
1174 39 magro732 
begin
1175 
 
1176 45 magro732 
  inboundAck_o <= inboundAck;
1177 39 magro732 
 
1178 
  ready_o <= complete when (state = READY) else '0';
1179 
 
1180 
  WriteClass: process(clk, areset_n)
1181 
  begin
1182 
    if (areset_n = '0') then
1183 44 magro732 
      state <= RECEIVE_PACKET;
1184 
 
1185 
      wdptr <= '0';
1186 
      wrsize <= (others=>'0');
1187 
 
1188 45 magro732 
      inboundAck <= '0';
1189 39 magro732 
      complete <= '0';
1190 45 magro732 
      responseNeeded_o <= '0';
1191 39 magro732 
 
1192 44 magro732 
      packetIndex <= 0;
1193 
      doubleWord <= (others=>'0');
1194 
 
1195 
      memoryWrite <= '0';
1196 
      memoryAddress <= (others=>'0');
1197 
      memoryDataIn <= (others=>'0');
1198 
 
1199 39 magro732 
      vc_o <= '0';
1200 
      crf_o <= '0';
1201 
      prio_o <= "00";
1202 
      tt_o <= "00";
1203 44 magro732 
      dstId_o <= (others=>'0');
1204 
      srcId_o <= (others=>'0');
1205 39 magro732 
      tid_o <= (others=>'0');
1206 
      address_o <= (others=>'0');
1207 
    elsif (clk'event and clk = '1') then
1208 
      case state is
1209 
        when RECEIVE_PACKET =>
1210 45 magro732 
          if (inboundCyc_i = '1') then
1211 
            if (inboundAck = '0') then
1212 
              if (inboundStb_i = '1') then
1213 
                if ((inboundAdr_i = x"55") or (inboundAdr_i = x"54")) then
1214 39 magro732 
                  -------------------------------------------------------------
1215 45 magro732 
                  -- NWRITE/NWRITER packet parser.
1216 39 magro732 
                  -------------------------------------------------------------
1217 
                  case (packetIndex) is
1218 
                    when 0 =>
1219 
                      -- x"0000" & ackid & vc & crf & prio & tt & ftype
1220 45 magro732 
                      vc_o <= inboundDat_i(9);
1221 
                      crf_o <= inboundDat_i(8);
1222 
                      prio_o <= inboundDat_i(7 downto 6);
1223 
                      tt_o <= inboundDat_i(5 downto 4);
1224 39 magro732 
                      packetIndex <= packetIndex + 1;
1225 
                    when 1 =>
1226 
                      -- destId
1227 45 magro732 
                      dstId_o <= inboundDat_i;
1228 39 magro732 
                      packetIndex <= packetIndex + 1;
1229 
                    when 2 =>
1230 
                      -- srcId
1231 45 magro732 
                      srcId_o <= inboundDat_i;
1232 39 magro732 
                      packetIndex <= packetIndex + 1;
1233 
                    when 3 =>
1234 
                      -- transaction & wrsize & srcTID & address(28:13)
1235 
                      -- REMARK: Add support for extended addresses here...
1236 45 magro732 
                      if (inboundDat_i(31 downto 28) = "0101") then
1237 
                        responseNeeded_o <= '1';
1238 
                      else
1239 
                        responseNeeded_o <= '0';
1240 
                      end if;
1241 
                      wrsize <= inboundDat_i(27 downto 24);
1242 
                      tid_o <= inboundDat_i(23 downto 16);
1243 
                      address_o(28 downto 13) <= inboundDat_i(15 downto 0);
1244 39 magro732 
                      packetIndex <= packetIndex + 1;
1245 
                    when 4 =>
1246 
                      -- address(12:0) & wdptr & xamsbs(1:0) & double-word(63:48)
1247 45 magro732 
                      address_o(12 downto 0) <= inboundDat_i(31 downto 19);
1248 
                      wdptr <= inboundDat_i(18);
1249 
                      address_o(30 downto 29) <= inboundDat_i(17 downto 16);
1250 
                      doubleWord(63 downto 48) <= inboundDat_i(15 downto 0);
1251 39 magro732 
                      packetIndex <= packetIndex + 1;
1252 
                    when 5 | 7 | 9 | 11 | 13 | 15 | 17 | 19 | 21 | 23 | 25 | 27 | 29 | 31  | 33 | 35 |
1253 
                      37 | 39 | 41 | 43 | 45 | 47 | 49 | 51 | 53 | 55 | 57 | 59 | 61 | 63 | 65 | 67 =>
1254 
                      -- double-word(47:16)
1255 45 magro732 
                      doubleWord(47 downto 16) <= inboundDat_i;
1256 39 magro732 
                      packetIndex <= packetIndex + 1;
1257 
                    when 6 | 8 | 10 | 12 | 14 | 16 | 18 | 20 | 22 | 24 | 26 | 28 | 30 | 32  | 34 |
1258 45 magro732 
                      36 | 38 | 40 | 42 | 44 | 46 | 48 | 50 | 52 | 54 | 56 | 58 | 60 | 62 | 64 | 66 | 68 =>
1259 39 magro732 
                      -- double-word(15:0) & double-word(63:48)
1260 45 magro732 
                      doubleWord(63 downto 48) <= inboundDat_i(15 downto 0);
1261 39 magro732 
                      packetIndex <= packetIndex + 1;
1262 
 
1263 
                      memoryWrite <= '1';
1264 45 magro732 
                      memoryDataIn <= doubleWord(63 downto 16) & inboundDat_i(31 downto 16);
1265 39 magro732 
                    when others =>
1266 45 magro732 
                      -- There should be no more content in an NWRITE/NWRITER request.
1267 39 magro732 
                      -- Discard.
1268 
                  end case;
1269 45 magro732 
                  inboundAck <= '1';
1270 6 magro732 
                end if;
1271 
              end if;
1272 
            else
1273 39 magro732 
              if (memoryWrite = '1') then
1274 
                memoryAddress <= std_logic_vector(unsigned(memoryAddress) + 1);
1275 
              end if;
1276 
 
1277 
              memoryWrite <= '0';
1278 45 magro732 
              inboundAck <= '0';
1279 6 magro732 
            end if;
1280 
          else
1281 45 magro732 
            if (packetIndex >= 6) then
1282 
              complete <= '1';
1283 39 magro732 
              state <= READY;
1284 45 magro732 
            else
1285 
              packetIndex <= 0;
1286 
              memoryAddress <= (others=>'0');
1287 39 magro732 
            end if;
1288 6 magro732 
          end if;
1289 
 
1290 39 magro732 
        when READY =>
1291 
          ---------------------------------------------------------------------
1292 
          -- Wait for the handler of the packet to signal that it has been
1293 
          -- processed.
1294 
          ---------------------------------------------------------------------
1295 
          if (done_i = '1') then
1296 45 magro732 
            packetIndex <= 0;
1297 
            memoryAddress <= (others=>'0');
1298 39 magro732 
            complete <= '0';
1299 
            state <= RECEIVE_PACKET;
1300 6 magro732 
          end if;
1301 
 
1302 
        when others =>
1303 39 magro732 
          ---------------------------------------------------------------------
1304 
          --
1305 
          ---------------------------------------------------------------------
1306 6 magro732 
 
1307 
      end case;
1308 39 magro732 
    end if;
1309 
  end process;
1310 6 magro732 
 
1311 39 magro732 
  -----------------------------------------------------------------------------
1312 
  -- Transformation of wrsize and wdptr into length of access and byte lanes.
1313 
  -----------------------------------------------------------------------------
1314 
 
1315 
  process(clk, areset_n)
1316 
  begin
1317 
    if (areset_n = '0') then
1318 44 magro732 
      length_o <= "00000";
1319 39 magro732 
      select_o <= (others=>'0');
1320 
    elsif (clk'event and clk = '1') then
1321 
      if (complete = '1') then
1322 
        if (wdptr = '0') then
1323 
          case wrsize is
1324 
            when "0000" =>
1325 44 magro732 
              length_o <= "00000";
1326 39 magro732 
              select_o <= "10000000";
1327 
            when "0001" =>
1328 44 magro732 
              length_o <= "00000";
1329 39 magro732 
              select_o <= "01000000";
1330 
            when "0010" =>
1331 44 magro732 
              length_o <= "00000";
1332 39 magro732 
              select_o <= "00100000";
1333 
            when "0011" =>
1334 44 magro732 
              length_o <= "00000";
1335 39 magro732 
              select_o <= "00010000";
1336 
            when "0100" =>
1337 44 magro732 
              length_o <= "00000";
1338 39 magro732 
              select_o <= "11000000";
1339 
            when "0101" =>
1340 44 magro732 
              length_o <= "00000";
1341 39 magro732 
              select_o <= "11100000";
1342 
            when "0110" =>
1343 44 magro732 
              length_o <= "00000";
1344 39 magro732 
              select_o <= "00110000";
1345 
            when "0111" =>
1346 44 magro732 
              length_o <= "00000";
1347 39 magro732 
              select_o <= "11111000";
1348 
            when "1000" =>
1349 44 magro732 
              length_o <= "00000";
1350 39 magro732 
              select_o <= "11110000";
1351 
            when "1001" =>
1352 44 magro732 
              length_o <= "00000";
1353 39 magro732 
              select_o <= "11111100";
1354 
            when "1010" =>
1355 44 magro732 
              length_o <= "00000";
1356 39 magro732 
              select_o <= "11111110";
1357 
            when "1011" =>
1358 44 magro732 
              length_o <= "00000";
1359 39 magro732 
              select_o <= "11111111";
1360 
            when others =>
1361 45 magro732 
              length_o <= std_logic_vector(unsigned(memoryAddress)-1);
1362 39 magro732 
              select_o <= "11111111";
1363 
          end case;
1364 
        else
1365 
          case wrsize is
1366 
            when "0000" =>
1367 44 magro732 
              length_o <= "00000";
1368 39 magro732 
              select_o <= "00001000";
1369 
            when "0001" =>
1370 44 magro732 
              length_o <= "00000";
1371 39 magro732 
              select_o <= "00000100";
1372 
            when "0010" =>
1373 44 magro732 
              length_o <= "00000";
1374 39 magro732 
              select_o <= "00000010";
1375 
            when "0011" =>
1376 44 magro732 
              length_o <= "00000";
1377 39 magro732 
              select_o <= "00000001";
1378 
            when "0100" =>
1379 44 magro732 
              length_o <= "00000";
1380 39 magro732 
              select_o <= "00001100";
1381 
            when "0101" =>
1382 44 magro732 
              length_o <= "00000";
1383 39 magro732 
              select_o <= "00000111";
1384 
            when "0110" =>
1385 44 magro732 
              length_o <= "00000";
1386 39 magro732 
              select_o <= "00000011";
1387 
            when "0111" =>
1388 44 magro732 
              length_o <= "00000";
1389 39 magro732 
              select_o <= "00011111";
1390 
            when "1000" =>
1391 44 magro732 
              length_o <= "00000";
1392 39 magro732 
              select_o <= "00001111";
1393 
            when "1001" =>
1394 44 magro732 
              length_o <= "00000";
1395 39 magro732 
              select_o <= "00111111";
1396 
            when "1010" =>
1397 44 magro732 
              length_o <= "00000";
1398 39 magro732 
              select_o <= "01111111";
1399 
            when others =>
1400 45 magro732 
              length_o <= std_logic_vector(unsigned(memoryAddress)-1);
1401 39 magro732 
              select_o <= "11111111";
1402 
          end case;
1403 
        end if;
1404 
      end if;
1405 6 magro732 
    end if;
1406 39 magro732 
  end process;
1407 6 magro732 
 
1408 
  -----------------------------------------------------------------------------
1409 39 magro732 
  -- Payload content memory.
1410 6 magro732 
  -----------------------------------------------------------------------------
1411 44 magro732 
 
1412 39 magro732 
  PayloadMemory: MemorySimpleDualPort
1413 
    generic map(ADDRESS_WIDTH=>5, DATA_WIDTH=>64)
1414 
    port map(clkA_i=>clk,
1415 
             enableA_i=>memoryWrite,
1416 
             addressA_i=>memoryAddress,
1417 
             dataA_i=>memoryDataIn,
1418 
             clkB_i=>clk,
1419 44 magro732 
             enableB_i=>payloadRead_i,
1420 
             addressB_i=>payloadIndex_i,
1421 39 magro732 
             dataB_o=>payload_o);
1422 6 magro732 
 
1423 39 magro732 
end architecture;
1424 
 
1425 
 
1426 
 
1427 
-------------------------------------------------------------------------------
1428 
--
1429 
-------------------------------------------------------------------------------
1430 
library ieee;
1431 
use ieee.std_logic_1164.all;
1432 
use ieee.numeric_std.all;
1433 
use work.rio_common.all;
1434 
 
1435 
-------------------------------------------------------------------------------
1436 
--
1437 
-------------------------------------------------------------------------------
1438 
entity ResponseClassOutbound is
1439 
  port(
1440 
    clk : in std_logic;
1441 
    areset_n : in std_logic;
1442 
    enable : in std_logic;
1443 
 
1444 
    ready_i : in std_logic;
1445 
    vc_i : in std_logic;
1446 
    crf_i : in std_logic;
1447 
    prio_i : in std_logic_vector(1 downto 0);
1448 
    tt_i : in std_logic_vector(1 downto 0);
1449 
    dstid_i : in std_logic_vector(31 downto 0);
1450 
    srcid_i : in std_logic_vector(31 downto 0);
1451 
    tid_i : in std_logic_vector(7 downto 0);
1452 
    error_i : in std_logic;
1453 
    payloadPresent_i :  in std_logic;
1454 44 magro732 
    payloadLength_i : in std_logic_vector(4 downto 0);
1455 39 magro732 
    payloadWrite_i : in std_logic;
1456 44 magro732 
    payloadIndex_i : in std_logic_vector(4 downto 0);
1457 
    payload_i : in std_logic_vector(63 downto 0);
1458 39 magro732 
    done_o : out std_logic;
1459 
 
1460 45 magro732 
    outboundCyc_o : out std_logic;
1461 
    outboundStb_o : out std_logic;
1462 
    outboundDat_o : out std_logic_vector(31 downto 0);
1463 
    outboundAck_i : in std_logic);
1464 39 magro732 
end entity;
1465 
 
1466 
 
1467 
-------------------------------------------------------------------------------
1468 
--
1469 
-------------------------------------------------------------------------------
1470 
architecture ResponseClassOutbound of ResponseClassOutbound is
1471 44 magro732 
  signal header : std_logic_vector(31 downto 0);
1472 
 
1473 
  type StateType is (WAIT_PACKET, SEND_RESPONSE,
1474 39 magro732 
                     WAIT_COMPLETE, RESPONSE_DONE);
1475 
  signal state : StateType;
1476 
 
1477 44 magro732 
  signal packetIndex : natural range 0 to 68;
1478 
 
1479 
  signal responsePayloadIndex : std_logic_vector(4 downto 0);
1480 
  signal responsePayload : std_logic_vector(15 downto 0);
1481 39 magro732 
 
1482 
  signal memoryEnable : std_logic;
1483 
  signal memoryAddress : std_logic_vector(4 downto 0);
1484 
  signal memoryDataRead : std_logic_vector(63 downto 0);
1485 
 
1486 
begin
1487 
 
1488 
  header <= x"0000" & "000000" & vc_i & crf_i & prio_i & tt_i & x"d";
1489 
 
1490 
  Response: process(clk, areset_n)
1491 
  begin
1492 
    if (areset_n = '0') then
1493 44 magro732 
      state <= WAIT_PACKET;
1494 39 magro732 
 
1495 44 magro732 
      packetIndex <= 0;
1496 
 
1497 
      responsePayloadIndex <= (others=>'0');
1498 
      responsePayload <= (others=>'0');
1499 
 
1500 39 magro732 
      memoryEnable <= '0';
1501 
      memoryAddress <= (others=>'0');
1502 
 
1503 
      done_o <= '0';
1504 
 
1505 45 magro732 
      outboundCyc_o <= '0';
1506 
      outboundStb_o <= '0';
1507 
      outboundDat_o <= (others=>'0');
1508 39 magro732 
    elsif (clk'event and clk = '1') then
1509 
      if (enable = '1') then
1510 
        case state is
1511 
          when WAIT_PACKET =>
1512 
            -------------------------------------------------------------------
1513 
            --
1514 
            -------------------------------------------------------------------
1515 
            if (ready_i = '1') then
1516 45 magro732 
              outboundCyc_o <= '1';
1517 
              outboundStb_o <= '1';
1518 
              outboundDat_o <= header;
1519 39 magro732 
 
1520 
              packetIndex <= 1;
1521 44 magro732 
              responsePayloadIndex <= (others=>'0');
1522 39 magro732 
 
1523 
              memoryEnable <= '1';
1524 
              memoryAddress <= (others=>'0');
1525 
 
1526 
              state <= SEND_RESPONSE;
1527 6 magro732 
            end if;
1528 39 magro732 
 
1529 
          when SEND_RESPONSE =>
1530 
            ---------------------------------------------------------------------
1531 
            --
1532 
            ---------------------------------------------------------------------
1533 45 magro732 
            if (outboundAck_i = '1') then
1534 39 magro732 
              case (packetIndex) is
1535 
                when 1 =>
1536 
                  -- destination
1537 45 magro732 
                  outboundDat_o <= dstId_i;
1538 39 magro732 
                  packetIndex <= packetIndex + 1;
1539 
                when 2 =>
1540 
                  -- source
1541 45 magro732 
                  outboundDat_o <= srcId_i;
1542 39 magro732 
                  packetIndex <= packetIndex + 1;
1543 
                when 3 =>
1544 
                  -- transaction & status & targetTID & double-word0(63:48)
1545 
                  if (error_i = '0') then
1546 
                    if (payloadPresent_i = '0') then
1547 45 magro732 
                      outboundDat_o <= "0000" & "0000" & tid_i & x"0000";
1548 39 magro732 
                      state <= WAIT_COMPLETE;
1549 
                    else
1550 45 magro732 
                      outboundDat_o <= "1000" & "0000" & tid_i & memoryDataRead(63 downto 48);
1551 39 magro732 
                    end if;
1552 
                  else
1553 45 magro732 
                    outboundDat_o <= "0000" & "0111" & tid_i & x"0000";
1554 39 magro732 
                    state <= WAIT_COMPLETE;
1555 
                  end if;
1556 
                  packetIndex <= packetIndex + 1;
1557 
                when 4 | 6 | 8 | 10 | 12 | 14 | 16 | 18 | 20 | 22 | 24 | 26 | 28 | 30 | 32 | 34 |
1558 
                  36 | 38 | 40 | 42 | 44 | 46 | 48 | 50 | 52 | 54 | 56 | 58 | 60 | 62 | 64 | 66 =>
1559 
                  -- double-wordN(47:16)
1560 45 magro732 
                  outboundDat_o <= memoryDataRead(47 downto 16);
1561 39 magro732 
                  responsePayload <= memoryDataRead(15 downto 0);
1562 
                  memoryAddress <= std_logic_vector(unsigned(memoryAddress) + 1);
1563 
                  packetIndex <= packetIndex + 1;
1564 
                when 5 | 7 | 9 | 11 | 13 | 15 | 17 | 19 | 21 | 23 | 25 | 27 | 29 | 31 | 33 | 35 |
1565 
                  37 | 39 | 41 | 43 | 45 | 47 | 49 | 51 | 53 | 55 | 57 | 59 | 61 | 63 | 65 | 67 =>
1566 
                  -- double-wordN(15:0) & double-wordN(63:48)
1567 45 magro732 
                  outboundDat_o <= responsePayload & memoryDataRead(63 downto 48);
1568 39 magro732 
                  packetIndex <= packetIndex + 1;
1569 
 
1570 
                  responsePayloadIndex <=
1571 
                    std_logic_vector(unsigned(responsePayloadIndex) + 1);
1572 
 
1573 44 magro732 
                  if (responsePayloadIndex = payloadLength_i) then
1574 39 magro732 
                    state <= WAIT_COMPLETE;
1575 
                  else
1576 
                    packetIndex <= packetIndex + 1;
1577 
                  end if;
1578 
                when others =>
1579 
                  -- Unallowed response length.
1580 
                  -- Dont do anything.
1581 
              end case;
1582 6 magro732 
            end if;
1583 39 magro732 
 
1584 
          when WAIT_COMPLETE =>
1585 
            -------------------------------------------------------------------
1586 
            --
1587 
            -------------------------------------------------------------------
1588 45 magro732 
            if (outboundAck_i = '1') then
1589 
              outboundCyc_o <= '0';
1590 
              outboundStb_o <= '0';
1591 39 magro732 
              state <= RESPONSE_DONE;
1592 
            end if;
1593 
 
1594 
          when RESPONSE_DONE =>
1595 
            ---------------------------------------------------------------------
1596 
            --
1597 
            ---------------------------------------------------------------------
1598 
            memoryEnable <= '0';
1599 
            if (ready_i = '0') then
1600 
              state <= WAIT_PACKET;
1601 
              done_o <= '0';
1602 6 magro732 
            else
1603 39 magro732 
              done_o <= '1';
1604 6 magro732 
            end if;
1605 39 magro732 
 
1606 6 magro732 
          when others =>
1607 39 magro732 
            ---------------------------------------------------------------------
1608 
            --
1609 
            ---------------------------------------------------------------------
1610 
            state <= WAIT_PACKET;
1611 
 
1612 6 magro732 
        end case;
1613 
      end if;
1614 
    end if;
1615 
  end process;
1616 
 
1617 
  -----------------------------------------------------------------------------
1618 39 magro732 
  -- Payload content memory.
1619 6 magro732 
  -----------------------------------------------------------------------------
1620 39 magro732 
  PayloadMemory: MemorySimpleDualPort
1621 
    generic map(ADDRESS_WIDTH=>5, DATA_WIDTH=>64)
1622 
    port map(clkA_i=>clk,
1623 
             enableA_i=>payloadWrite_i,
1624 
             addressA_i=>payloadIndex_i,
1625 
             dataA_i=>payload_i,
1626 
             clkB_i=>clk,
1627 
             enableB_i=>memoryEnable,
1628 
             addressB_i=>memoryAddress,
1629 
             dataB_o=>memoryDataRead);
1630 6 magro732 
 
1631 
end architecture;

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