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borin |
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.riscompatible_package.all;
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entity GPIO is
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generic
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(
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NumBitsAddr : natural:=1;
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NumBitsInputPorts : natural:=2;
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NumBitsOutputPorts : natural:=2
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);
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port
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(
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Clk_I : in std_logic;
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Enable_I : in std_logic;
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Write_I : in std_logic;
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Address_I : in std_logic_vector(NumBitsAddr-1 downto 0);
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InputData_I : in std_logic_vector(C_NumBitsWord-1 downto 0);
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OutputData_O : out std_logic_vector(C_NumBitsWord-1 downto 0);
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OutputData_Vld_O : out std_logic;
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InputPorts_I : in std_logic_vector(NumBitsInputPorts-1 downto 0);
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OutputPorts_O : out std_logic_vector(NumBitsOutputPorts-1 downto 0)
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);
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end GPIO;
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architecture behavioral of GPIO is
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function num_bits(num_io : integer) return integer is
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begin
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case num_io is
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when 0|1|2 =>
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return (1);
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when 3|4 =>
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return (2);
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when 5|6|7|8 =>
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return (3);
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when 9|10|11|12|13|14|15|16 =>
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return (4);
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when 17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32 =>
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return (5);
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when others => return (-1);
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end case;
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end function num_bits;
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begin
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process (Clk_I,Address_I)
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begin
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if Clk_I'event and Clk_I = '1' then
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if (Enable_I = '1') then
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if (Write_I = '1') and Address_I(Address_I'high)='1' then
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if to_integer(unsigned(Address_I(Address_I'high-1 downto 0))) * C_NumBitsWord < NumBitsOutputPorts then
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for i in 0 to 31 loop
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if to_integer(unsigned(Address_I(Address_I'high-1 downto 0))) * C_NumBitsWord + i < NumBitsOutputPorts then
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OutputPorts_O(i) <= InputData_I(i);
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end if;
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end loop;
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end if;
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end if;
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end if;
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if Address_I(Address_I'high)='1' then
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OutputData_Vld_O <= '1';
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else
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OutputData_Vld_O <= '0';
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end if;
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for i in 0 to 31 loop
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if to_integer(unsigned(Address_I(Address_I'high-1 downto 0))) * C_NumBitsWord + i < NumBitsInputPorts then
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OutputData_O(i) <= InputPorts_I(i);
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else
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OutputData_O(i) <= '0';
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end if;
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end loop;
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end if;
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end process;
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end behavioral;
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