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[/] [riscompatible/] [trunk/] [rtl/] [riscompatible_package.vhd] - Blame information for rev 2

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1 2 borin 
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2 
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-------------------------------------------------------------------------------------------------------------------
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package riscompatible_package is
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    ---------------------------------------------
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    constant C_NumBitsWord    : integer:=32;
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    constant C_NumBitsRegBank : natural:=3;
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    subtype TRiscoWord is std_logic_vector(C_NumBitsWord-1 downto 0);
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    subtype TRiscoWordPlusCarry is std_logic_vector(C_NumBitsWord downto 0); -- Carry = bit 32
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    ---------------------------------------------
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    -- Flags
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    ---------------------------------------------
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    type TRiscoFlag is record
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        Clr_I  : std_logic;
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        Wen_I  : std_logic;
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        Data_I : std_logic;
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        Data_O : std_logic;
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    end record;
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    ---------------------------------------------
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    -- Registers
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    ---------------------------------------------
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    type TRiscoReg is record
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        Clr_I  : std_logic;
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        Wen_I  : std_logic;
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        Data_I : std_logic_vector(C_NumBitsWord-1 downto 0);
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        Data_O : std_logic_vector(C_NumBitsWord-1 downto 0);
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    end record;
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    ---------------------------------------------
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    -- Instruction Types
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    ---------------------------------------------
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    constant INST_ULA : std_logic_vector(1 downto 0):="00";
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    constant INST_MEM : std_logic_vector(1 downto 0):="10";
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    constant INST_JMP : std_logic_vector(1 downto 0):="01";
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    constant INST_SUB : std_logic_vector(1 downto 0):="11";
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    ---------------------------------------------
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    -- Arithmetic Logical Instructions
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    ---------------------------------------------
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    -- ALU
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    constant C_AND      : std_logic_vector(4 downto 0):="01111";
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    constant C_OR       : std_logic_vector(4 downto 0):="01110";
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    constant C_XOR      : std_logic_vector(4 downto 0):="01101";
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    constant C_SUBRC    : std_logic_vector(4 downto 0):="01011";
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    constant C_SUBRCNOT : std_logic_vector(4 downto 0):="01010";
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    constant C_SUBR     : std_logic_vector(4 downto 0):="01001";
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    constant C_SUBRNC   : std_logic_vector(4 downto 0):="01000";
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    constant C_SUBC     : std_logic_vector(4 downto 0):="00111";
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    constant C_SUBCNOT  : std_logic_vector(4 downto 0):="00110";
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    constant C_SUB      : std_logic_vector(4 downto 0):="00101";
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    constant C_SUBNC    : std_logic_vector(4 downto 0):="00100";
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    constant C_ADDCNOT  : std_logic_vector(4 downto 0):="00011";
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    constant C_ADDC     : std_logic_vector(4 downto 0):="00010";
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    constant C_ADD1     : std_logic_vector(4 downto 0):="00001";
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    constant C_ADD      : std_logic_vector(4 downto 0):="00000";
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    -- UD
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    constant C_RLL      : std_logic_vector(4 downto 0):="10000";
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    constant C_RLLC     : std_logic_vector(4 downto 0):="10001";
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    constant C_RLA      : std_logic_vector(4 downto 0):="10010";
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    constant C_RLAC     : std_logic_vector(4 downto 0):="10011";
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    constant C_RRL      : std_logic_vector(4 downto 0):="10100";
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    constant C_RRLC     : std_logic_vector(4 downto 0):="10101";
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    constant C_RRA      : std_logic_vector(4 downto 0):="10110";
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    constant C_RRAC     : std_logic_vector(4 downto 0):="10111";
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    constant C_SLL      : std_logic_vector(4 downto 0):="11000";
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    constant C_SLLC     : std_logic_vector(4 downto 0):="11001";
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    constant C_SLA      : std_logic_vector(4 downto 0):="11010";
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    constant C_SLAC     : std_logic_vector(4 downto 0):="11011";
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    constant C_SRL      : std_logic_vector(4 downto 0):="11100";
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    constant C_SRLC     : std_logic_vector(4 downto 0):="11101";
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    constant C_SRA      : std_logic_vector(4 downto 0):="11110";
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    constant C_SRAC     : std_logic_vector(4 downto 0):="11111";
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    -- NOT PRESENT (PG 101,PG 220,PG 234): C_ADD1, C_ADDCNOT, C_SUBCNOT, C_SUBNC, C_SUBRNC, C_SUBRCNOT
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    -- PRESENT ON PG 136
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    ---------------------------------------------
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    -- Memory Access Instructions
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    ---------------------------------------------
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    constant C_LD       : std_logic_vector(4 downto 0):="00000";
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    constant C_LDPRI    : std_logic_vector(4 downto 0):="00111";
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    constant C_LDPOI    : std_logic_vector(4 downto 0):="00101";
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    constant C_LDPOD    : std_logic_vector(4 downto 0):="00100";
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    constant C_ST       : std_logic_vector(4 downto 0):="10000";
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    constant C_STPRI    : std_logic_vector(4 downto 0):="10111";
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    constant C_STPOI    : std_logic_vector(4 downto 0):="10101";
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    constant C_STPOD    : std_logic_vector(4 downto 0):="10100";
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    ---------------------------------------------
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    -- Conditions
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    ---------------------------------------------
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    constant C_TR     : std_logic_vector(4 downto 0):="11111";
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    constant C_NS     : std_logic_vector(4 downto 0):="10001";
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    constant C_CS     : std_logic_vector(4 downto 0):="10010";
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    constant C_OS     : std_logic_vector(4 downto 0):="10100";
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    constant C_ZS     : std_logic_vector(4 downto 0):="11000";
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    constant C_GE     : std_logic_vector(4 downto 0):="10011";
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    constant C_GT     : std_logic_vector(4 downto 0):="10110";
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    constant C_EQ     : std_logic_vector(4 downto 0):="11100";
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    constant C_FL     : std_logic_vector(4 downto 0):="00000";
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    constant C_NN     : std_logic_vector(4 downto 0):="00001";
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    constant C_NC     : std_logic_vector(4 downto 0):="00010";
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    constant C_NO     : std_logic_vector(4 downto 0):="00100";
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    constant C_NZ     : std_logic_vector(4 downto 0):="01000";
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    constant C_LT     : std_logic_vector(4 downto 0):="00011";
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    constant C_LE     : std_logic_vector(4 downto 0):="00110";
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    constant C_NE     : std_logic_vector(4 downto 0):="01100";
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    ---------------------------------------------
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    -- Source Operands
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    ---------------------------------------------
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    -- FT1 - Register number of source 1
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    -- FT2 - Register number of source 2
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    -- SS2 - Bit used to define format
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    -- Kp  - Small constant, 11 bits, extends signal
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    -- Kgl - Large constant, 17 bits, extends signal
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    -- Kgh - Large constant, 16 bits, most significant part
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    constant FFS_DST_FT1_FT2  : std_logic_vector(2 downto 0):="000";
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    constant FFS_DST_FT1_Kp   : std_logic_vector(2 downto 0):="001";
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    constant FFS_DST_R00_Kgl  : std_logic_vector(2 downto 0):="010";--01X
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    constant FFS_DST_DST_Kgh  : std_logic_vector(2 downto 0):="100";--10X
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    constant FFS_DST_DST_Kgl  : std_logic_vector(2 downto 0):="110";--11X
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    ---------------------------------------------
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    -- Specific Functions
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    ---------------------------------------------
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    --- CONSTEXT calculation
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    function Kpe_F(Kp : std_logic_vector(10 downto 0)) return TRiscoWord;
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    function Kgl_F(Kg : std_logic_vector(16 downto 0)) return TRiscoWord;
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    function Kgh_F(Kg : std_logic_vector(16 downto 0)) return TRiscoWord;
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    ---
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    function IsZero_F(Source : std_logic_vector) return std_logic;
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    ---------------------------------------------
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    -- Components
140 
    ---------------------------------------------
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    component riscompatible_core is
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        generic
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        (
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            NumBitsProgramMemory : Natural:=5;
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            NumBitsDataMemory    : Natural:=5;
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            NumBitsRegBank       : natural:=5
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        );
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        port
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        (
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            Clk_I             : in std_logic;
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            Reset_I           : in std_logic;
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            PMem_Enable_O     : out std_logic;
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            PMem_Write_O      : out std_logic;
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            PMem_Address_O    : out std_logic_vector(NumBitsProgramMemory-1 downto 0);
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            PMem_InputData_O  : out TRiscoWord;
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            PMem_OutputData_I : in TRiscoWord;
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            DMem_Enable_O     : out std_logic;
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            DMem_Write_O      : out std_logic;
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            DMem_Address_O    : out std_logic_vector(NumBitsDataMemory-1 downto 0);
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            DMem_InputData_O  : out TRiscoWord;
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            DMem_OutputData_I : in TRiscoWord;
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            Int_I             : in std_logic;
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            IntAck_O          : out std_logic
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        );
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    end component;
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    component RegisterBank is
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        generic
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        (
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            NumBitsAddr : natural:=4;
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            DataWidth   : natural:=32
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        );
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        port
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        (
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            Clk_I           : in std_logic;
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            Enable_I        : in std_logic;
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            Write_I         : in std_logic;
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            RegisterW_I     : in std_logic_vector(NumBitsAddr-1 downto 0);
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            Register1_I     : in std_logic_vector(NumBitsAddr-1 downto 0);
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            Register2_I     : in std_logic_vector(NumBitsAddr-1 downto 0);
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            InputData_I     : in std_logic_vector(DataWidth-1 downto 0);
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            FT1OutputData_O : out std_logic_vector(DataWidth-1 downto 0);
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            FT2OutputData_O : out std_logic_vector(DataWidth-1 downto 0)
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        );
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    end component;
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    component Ula is
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        port
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        (
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            Cy_I       : in std_logic;
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            Source1_I  : in TRiscoWord;
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            Source2_I  : in TRiscoWord;
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            Function_I : in std_logic_vector(4 downto 0);
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            Output_O   : out TRiscoWord;
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            Cy_O       : out std_logic;
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            Ov_O       : out std_logic;
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            Zr_O       : out std_logic;
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            Ng_O       : out std_logic
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        );
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    end component;
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    component UD is
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        port
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        (
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            InputData_I   : in TRiscoWord;
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            ShiftAmount_I : in std_logic_vector(4 downto 0);
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            OutputData_o  : out TRiscoWord;
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            Function_I    : in std_logic_vector(4 downto 0);
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            Cy_I          : in std_logic;
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            Cy_O          : out std_logic
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        );
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    end component;
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    component select_and_control is
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        generic
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        (
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            NumBitsProgramMemory : Natural:=5;
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            NumBitsDataMemory    : Natural:=5;
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            NumBitsRegBank       : natural:=5
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        );
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        port
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        (
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            Clk_I                    : in std_logic;
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            Reset_I                  : in std_logic;
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            PMem_Enable_O            : out std_logic;
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            PMem_Address_O           : out std_logic_vector(NumBitsProgramMemory - 1 downto 0);
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            PMem_Write_O             : out std_logic;
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            PMem_OutputData_I        : in TRiscoWord;
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            DMem_Enable_O            : out std_logic;
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            DMem_Write_O             : out std_logic;
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            DMem_Address_O           : out std_logic_vector(NumBitsDataMemory - 1 downto 0);
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            DMem_InputData_O         : out TRiscoWord;
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            DMem_OutputData_I        : in TRiscoWord;
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            RegBnk_Register1_O       : out std_logic_vector(NumBitsRegBank - 1 downto 0);
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            RegBnk_Register2_O       : out std_logic_vector(NumBitsRegBank - 1 downto 0);
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            RegBnk_RegisterW_O       : out std_logic_vector(NumBitsRegBank - 1 downto 0);
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            RegBnk_Write_O           : out std_logic;
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            RegBnk_InputData_O       : out TRiscoWord;
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            RegBnk_FT1_OutputData_I  : in TRiscoWord;
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            RegBnk_FT2_OutputData_I  : in TRiscoWord;
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            ULA_Function_O           : out std_logic_vector(4 downto 0);
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            ULA_Output_I             : in TRiscoWord;
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            ULA_Ng_O_I               : in std_logic;
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            ULA_Cy_O_I               : in std_logic;
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            ULA_Ov_O_I               : in std_logic;
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            ULA_Zr_O_I               : in std_logic;
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            UD_Function_O            : out std_logic_vector(4 downto 0);
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            UD_OutputData_I          : in TRiscoWord;
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            UD_Cy_O_I                : in std_logic;
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            RUA_Clr_O                : out std_logic;
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            RUB_Clr_O                : out std_logic;
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            RDA_Clr_O                : out std_logic;
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            RDB_Clr_O                : out std_logic;
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            RUA_Wen_O                : out std_logic;
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            RUB_Wen_O                : out std_logic;
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            RDA_Wen_O                : out std_logic;
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            RDB_Wen_O                : out std_logic;
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            RUA_Data_O               : out std_logic_vector(C_NumBitsWord - 1 downto 0);
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            RUB_Data_O               : out std_logic_vector(C_NumBitsWord - 1 downto 0);
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            RDA_Data_O               : out std_logic_vector(C_NumBitsWord - 1 downto 0);
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            RDB_Data_O               : out std_logic_vector(C_NumBitsWord - 1 downto 0);
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            PC_Clr_O                 : out std_logic;
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            PC_Wen_O                 : out std_logic;
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            PC_Data_I                : in std_logic_vector(C_NumBitsWord - 1 downto 0);
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            PC_Data_O                : out std_logic_vector(C_NumBitsWord - 1 downto 0);
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            PSW_Clr_O                : out std_logic;
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            PSW_Wen_O                : out std_logic;
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            PSW_Data_I               : in std_logic_vector(C_NumBitsWord - 1 downto 0);
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            PSW_Data_O               : out std_logic_vector(C_NumBitsWord - 1 downto 0);
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            Int_I                    : in std_logic;
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            IntAck_O                 : out std_logic
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        );
269 
    end component;
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    component reg is
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        generic
272 
        (
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            NumBits : Natural:=5
274 
        );
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        port
276 
        (
277 
            Clk_I : in std_logic;
278 
            Clr_I : in std_logic;
279 
            Wen_I : in std_logic;
280 
            Data_I : in std_logic_vector (NumBits-1 downto 0);
281 
            Data_O : out std_logic_vector (NumBits-1 downto 0)
282 
        );
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    end component;
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end package;
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package body riscompatible_package is
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    ---------------------------------------------
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    -- Implementation  of functions
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    ---------------------------------------------
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    -- Extends signal of Kp
290 
    function Kpe_F(Kp : std_logic_vector(10 downto 0)) return TRiscoWord is
291 
        variable VKpe : TRiscoWord;
292 
    begin
293 
        VKpe(10 downto 0):=Kp;
294 
        VKpe(TRiscoWord'high downto 11):=(others=>Kp(10));
295 
        return VKpe;
296 
    end function Kpe_F;
297 
    ---------------------------------------------
298 
    -- Extends signal of Kg
299 
    function Kgl_F(Kg : std_logic_vector(16 downto 0)) return TRiscoWord is
300 
        variable VKgl : TRiscoWord;
301 
    begin
302 
        VKgl(16 downto 0):=Kg;
303 
        VKgl(TRiscoWord'high downto 17):=(others=>Kg(16));
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        return VKgl;
305 
    end function Kgl_F;
306 
    ---------------------------------------------
307 
    -- Kg go to high order bits; low order bits receive the signal extension of Kg
308 
    function Kgh_F(Kg : std_logic_vector(16 downto 0)) return TRiscoWord is
309 
        variable VKgh : TRiscoWord;
310 
    begin
311 
        VKgh(31 downto 16):=Kg(15 downto 0);
312 
        VKgh(15 downto 0):=(others=>Kg(16));
313 
        return VKgh;
314 
    end function Kgh_F;
315 
    ---------------------------------------------
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    -- Set if word is equal to zero
317 
    function IsZero_F(Source : std_logic_vector) return std_logic is
318 
        variable counter : integer range Source'range;
319 
        variable accumulator : std_logic:='0';
320 
    begin
321 
        for counter in 0 to Source'high loop
322 
            accumulator:=accumulator or Source(counter);
323 
        end loop;
324 
        return (not accumulator);
325 
    end function IsZero_F;
326 
end riscompatible_package;
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