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[/] [riscompatible/] [trunk/] [rtl/] [ula.vhd] - Blame information for rev 2

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1 2 borin
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.riscompatible_package.all;
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entity Ula is
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    port
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    (
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        Cy_I       : in std_logic;
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        Source1_I  : in TRiscoWord;
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        Source2_I  : in TRiscoWord;
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        Function_I : in std_logic_vector(4 downto 0);
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        Output_O   : out TRiscoWord;
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        Cy_O       : out std_logic;
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        Ov_O       : out std_logic;
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        Zr_O       : out std_logic;
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        Ng_O       : out std_logic
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    );
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end Ula;
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architecture behavioral of ula is
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    signal UlaTemp_W : std_logic_vector(32 downto 0);
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    signal Carry_W : TRiscoWord;
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begin
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    Carry_W(0) <= Cy_I;
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    Carry_W(TRiscoWord'high downto 1) <= (others => '0');
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    with Function_I select
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        -- Fig. 5.8 of [1]
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        -- Carry -> bit 32
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        UlaTemp_W <=
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                     ('0'&Source1_I) and ('0'&Source2_I)                                                                    when C_AND,
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                     ('0'&Source1_I) or  ('0'&Source2_I)                                                                    when C_OR,
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                     ('0'&Source1_I) xor ('0'&Source2_I)                                                                    when C_XOR,
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                     std_logic_vector(unsigned('0'&not(Source1_I)) + unsigned('0'&Source2_I)      + unsigned(not(Carry_W))) when C_SUBRC,
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                     std_logic_vector(unsigned('0'&not(Source1_I)) + unsigned('0'&Source2_I)      + unsigned(Carry_W)     ) when C_SUBRCNOT,
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                     std_logic_vector(unsigned('0'&not(Source1_I)) + unsigned('0'&Source2_I)      + 1                     ) when C_SUBR,
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                     std_logic_vector(unsigned('0'&not(Source1_I)) + unsigned('0'&Source2_I)      + 0                     ) when C_SUBRNC,
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                     std_logic_vector(unsigned('0'&Source1_I)      + unsigned('0'&not(Source2_I)) + unsigned(not(Carry_W))) when C_SUBC,
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                     std_logic_vector(unsigned('0'&Source1_I)      + unsigned('0'&not(Source2_I)) + unsigned(Carry_W)     ) when C_SUBCNOT,
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                     std_logic_vector(unsigned('0'&Source1_I)      + unsigned('0'&not(Source2_I)) + 1                     ) when C_SUB,
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                     std_logic_vector(unsigned('0'&Source1_I)      + unsigned('0'&not(Source2_I)) + 0                     ) when C_SUBNC,
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                     std_logic_vector(unsigned('0'&Source1_I)      + unsigned('0'&Source2_I)      + unsigned(not(Carry_W))) when C_ADDCNOT,
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                     std_logic_vector(unsigned('0'&Source1_I)      + unsigned('0'&Source2_I)      + unsigned(Carry_W)     ) when C_ADDC,
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                     std_logic_vector(unsigned('0'&Source1_I)      + unsigned('0'&Source2_I)      + 1                     ) when C_ADD1,
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                     std_logic_vector(unsigned('0'&Source1_I)      + unsigned('0'&Source2_I)      + 0                     ) when C_ADD,
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                     (others => '0')                                                                                        when others;
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    Output_O <= UlaTemp_W(Output_O'range);
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    Cy_O <= UlaTemp_W(32);
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    Ov_O <= UlaTemp_W(32);
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    Zr_O <= IsZero_F(UlaTemp_W);
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    Ng_O <= UlaTemp_W(31);
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end behavioral;
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