URL https://opencores.org/ocsvn/riscompatible/riscompatible/trunk

Subversion Repositories riscompatible

[/] [riscompatible/] [trunk/] [sim/] [modelsim/] [compila.do] - Blame information for rev 2

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vlib work
vcom -93 ../../rtl/riscompatible_package.vhd
vcom -93 ../../rtl/reg.vhd
vcom -93 ../../rtl/select_and_control.vhd
vcom -93 ../../rtl/ud_package.vhd
vcom -93 ../../rtl/ud.vhd
vcom -93 ../../rtl/ula.vhd
vcom -93 ../../rtl/memory.vhd
vcom -93 ../../rtl/gpio.vhd
vcom -93 ../../rtl/registerbank.vhd
vcom -93 ../../rtl/riscompatible_core.vhd
vcom -93 ../../rtl/riscompatible.vhd
vcom -93 ../../bench/riscompatible_tb.vhd
vsim riscompatible_tb
do wave_riscompatible.do
run 100 us
 

Line No.	Rev	Author	Line
1	2	borin	`vlib work`
2			`vcom -93 ../../rtl/riscompatible_package.vhd`
3			`vcom -93 ../../rtl/reg.vhd`
4			`vcom -93 ../../rtl/select_and_control.vhd`
5			`vcom -93 ../../rtl/ud_package.vhd`
6			`vcom -93 ../../rtl/ud.vhd`
7			`vcom -93 ../../rtl/ula.vhd`
8			`vcom -93 ../../rtl/memory.vhd`
9			`vcom -93 ../../rtl/gpio.vhd`
10			`vcom -93 ../../rtl/registerbank.vhd`
11			`vcom -93 ../../rtl/riscompatible_core.vhd`
12			`vcom -93 ../../rtl/riscompatible.vhd`
13			`vcom -93 ../../bench/riscompatible_tb.vhd`
14			`vsim riscompatible_tb`
15			`do wave_riscompatible.do`
16			`run 100 us`
17

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Subversion Repositories riscompatible

[/] [riscompatible/] [trunk/] [sim/] [modelsim/] [compila.do] - Blame information for rev 2