OpenCores
URL https://opencores.org/ocsvn/robust_axi2ahb/robust_axi2ahb/trunk

Subversion Repositories robust_axi2ahb

[/] [robust_axi2ahb/] [trunk/] [src/] [base/] [axi2ahb_wr_fifo.v] - Blame information for rev 10

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 10 eyalhoc
<##//////////////////////////////////////////////////////////////////
2 5 eyalhoc
////                                                             ////
3
////  Author: Eyal Hochberg                                      ////
4
////          eyal@provartec.com                                 ////
5
////                                                             ////
6
////  Downloaded from: http://www.opencores.org                  ////
7
/////////////////////////////////////////////////////////////////////
8
////                                                             ////
9
//// Copyright (C) 2010 Provartec LTD                            ////
10
//// www.provartec.com                                           ////
11
//// info@provartec.com                                          ////
12
////                                                             ////
13
//// This source file may be used and distributed without        ////
14
//// restriction provided that this copyright statement is not   ////
15
//// removed from the file and that any derivative work contains ////
16
//// the original copyright notice and the associated disclaimer.////
17
////                                                             ////
18
//// This source file is free software; you can redistribute it  ////
19
//// and/or modify it under the terms of the GNU Lesser General  ////
20
//// Public License as published by the Free Software Foundation.////
21
////                                                             ////
22
//// This source is distributed in the hope that it will be      ////
23
//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
24
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
25
//// PURPOSE.  See the GNU Lesser General Public License for more////
26
//// details. http://www.gnu.org/licenses/lgpl.html              ////
27
////                                                             ////
28 10 eyalhoc
//////////////////////////////////////////////////////////////////##>
29 2 eyalhoc
 
30
INCLUDE def_axi2ahb.txt
31 4 eyalhoc
OUTFILE PREFIX_wr_fifo.v
32 2 eyalhoc
 
33 4 eyalhoc
module  PREFIX_wr_fifo (PORTS);
34 2 eyalhoc
 
35
   parameter              FIFO_LINES = EXPR(2 * 16); //double buffer of max burst
36
   parameter              RESP_SLVERR = 2'b10;
37
 
38
   input                  clk;
39
   input                  reset;
40
 
41
   port                   WGROUP_AXI_W;
42
   port                   BGROUP_AXI_B;
43
   output [DATA_BITS-1:0] HWDATA;
44
   input                  HREADY;
45
   input [1:0]            HTRANS;
46
   input                  HRESP;
47
 
48
   input                  cmd_err;
49
   input                  wdata_phase;
50
   output                 wdata_ready;
51
   input                  data_last;
52
 
53
 
54
   wire                   data_push;
55
   wire                   data_pop;
56
   wire                   data_empty;
57
   wire                   data_full;
58
 
59
   wire                   resp_push;
60
   wire                   resp_pop;
61
   wire                   resp_empty;
62
   wire                   resp_full;
63
 
64
   reg [LOG2(CMD_DEPTH):0] burst_cnt;
65
   wire                    burst_full;
66
 
67
   wire                   axi_last;
68
   wire                   ahb_last;
69
   wire [1:0]             cmd_resp;
70
 
71
   assign                 cmd_resp = cmd_err | HRESP ? RESP_SLVERR : 2'b00;
72
 
73
   assign                 wdata_ready = burst_cnt > 'd0;
74
 
75
   assign                 WREADY = (~data_full) & (~burst_full);
76
 
77
 
78
   assign                 data_push = WVALID & WREADY;
79
   assign                 data_pop = wdata_phase & HREADY;
80
 
81
   assign                 axi_last = WVALID & WREADY & WLAST;
82
   assign                 ahb_last = wdata_phase & data_last;
83
 
84
   assign                 burst_full = burst_cnt == {EXPR(LOG2(CMD_DEPTH)+1){1'b1}};
85
 
86
   always @(posedge clk or posedge reset)
87
     if (reset)
88
       burst_cnt <= #FFD 'd0;
89
     else if (axi_last | ahb_last)
90
       burst_cnt <= #FFD burst_cnt + axi_last - ahb_last;
91
 
92
   prgen_fifo #(DATA_BITS, FIFO_LINES)
93
   data_fifo(
94
            .clk(clk),
95
            .reset(reset),
96
            .push(data_push),
97
            .pop(data_pop),
98
            .din({WDATA
99
                  }
100
                 ),
101
            .dout({HWDATA
102
                   }
103
                  ),
104
            .empty(data_empty),
105
            .full(data_full)
106
            );
107
 
108
 
109
   assign                 resp_push = ahb_last;
110
   assign                 resp_pop  = BVALID & BREADY;
111
 
112
   assign                 BVALID = (~resp_empty);
113
 
114
   prgen_fifo #(2+ID_BITS, CMD_DEPTH)
115
   resp_fifo(
116
            .clk(clk),
117
            .reset(reset),
118
            .push(resp_push),
119
            .pop(resp_pop),
120
            .din({cmd_resp,
121
                  WID
122
                  }
123
                 ),
124
            .dout({BRESP,
125
                   BID
126
                   }
127
                  ),
128
            .empty(resp_empty),
129
            .full(resp_full)
130
            );
131
 
132
 
133
 
134
endmodule
135
 
136
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.