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unicore |
---------------------------------------------------------------------
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---- ----
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---- Reed Solomon decoder/encoder IP core ----
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---- ----
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---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
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---- Company: Unicore Systems http://unicore.co.ua ----
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---- ----
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---- Downloaded from: http://www.opencores.org ----
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---- ----
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---------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2006-2010 Unicore Systems LTD ----
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---- www.unicore.co.ua ----
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---- o.uzenkov@unicore.co.ua ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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---- ----
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---- THIS SOFTWARE IS PROVIDED "AS IS" ----
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---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
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---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
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---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
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---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
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---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
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---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
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---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
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---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
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---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
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---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
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---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
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---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
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---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
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---- ----
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---------------------------------------------------------------------
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--{{ Section below this comment is automatically maintained
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-- and may be overwritten
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--{entity {reed_sol_mull_div} architecture {reed_sol_mull_div}}
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity reed_sol_mull_div is
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port(
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clk : in STD_LOGIC;
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rst : in STD_LOGIC;
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a : in STD_LOGIC_VECTOR(7 downto 0);
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b : in STD_LOGIC_VECTOR(7 downto 0);
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m_d : in STD_LOGIC; -- '0' - mull, '1' - div
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tabla0 : in STD_LOGIC_VECTOR(7 downto 0);
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tablb0 : in STD_LOGIC_VECTOR(7 downto 0);
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tabl1 : in STD_LOGIC_VECTOR(7 downto 0);
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addra : out STD_LOGIC_VECTOR(7 downto 0);
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addrb : out STD_LOGIC_VECTOR(7 downto 0);
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addr1 : out STD_LOGIC_VECTOR(7 downto 0);
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error : out STD_LOGIC;
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res : out STD_LOGIC_VECTOR(7 downto 0)
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);
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end reed_sol_mull_div;
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--}} End of automatically maintained section
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architecture reed_sol_mull_div of reed_sol_mull_div is
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signal sm,sm1 : STD_LOGIC_VECTOR(8 downto 0) := (others => '0');
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signal md1 : std_logic;
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signal z0,e0 :std_logic;
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begin
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addra <= a;
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addrb <= b;
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process(clk,rst)
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begin
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if rst = '1' then
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sm1 <= (others => '0');
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md1 <= '0';
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elsif clk = '1' and clk'event then
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if m_d = '0' then sm1 <= ext(tabla0,9) + ext(tablb0,9) + 1;
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else sm1 <= ext(tabla0,9) - ext(tablb0,9);
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end if;
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md1 <= m_d;
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if a = x"00" or b = "00" then z0 <= '1'; else z0 <= '0'; end if;
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if m_d = '1' and b = "00" then e0 <= '1'; else e0 <= '0'; end if;
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end if;
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end process;
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sm <= sm1 + 0 when (md1 = '0' and sm1(8) = '1')else
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sm1 - 1 when (md1 = '0' or (md1 = '1' and sm1(8) = '1')) else sm1 + 0;
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addr1 <= sm(7 downto 0);
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res <= x"00" when (z0 = '1') else tabl1;
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error <= e0;
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-- enter your statements here --
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end reed_sol_mull_div;
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