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/////////////////////////////////////////////////////////////////////
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//// ////
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//// High Speed Reed Solomon Encoder ////
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//// ////
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//// ////
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//// Author: Rajesh Pathak ////
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//// rajesh_99@opencores.org ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2003 Rajesh Pathak ////
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//// rajesh_99@netzero.net ////
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//// Exponentiation Technology ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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module teststim( );
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wire [7:0] q0, q1, q2, q3, q4, q5, q6, q7, q8, q9, q10, q11, q12, q13, q14,
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q15;
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reg clk, valid;
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reg [7:0] datain;
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wire[7:0] gin0, gin1, gin2, gin3, gin4, gin5, gin6, gin7, gin8, gin9, gin10,
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gin11, gin12, gin13, gin14, gin15;
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reg rst;
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reg [31:0] tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4;
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wire [7:0] fbck, in, m0, z0, gin, sdrome;
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integer seed;
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integer seed1;
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initial begin
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clk = 0;
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rst = 1'b1;
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datain = 8'h06;
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#2 rst = 1'b0;
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#1 rst = 1'b1;
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//Start feeding message data here one byte at every clock.
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#1 datain = 8'h06;
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valid = 1;
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$dumpfile ("xxx.dump");
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$dumpvars (2, teststim);
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#10 datain = 8'hF0;
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#10 datain = 8'h82;
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#10 datain = 8'hEE;
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#10 datain = 8'h71;
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#10 datain = 8'h04;
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#10 datain = 8'h24;
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#10 datain = 8'h9A;
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#10 datain = 8'hEA;
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#10 datain = 8'h6E;
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#10 datain = 8'hEF;
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#10 datain = 8'hDD;
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#10 datain = $random(seed1);
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#10 datain = $random(seed);
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#10 datain = $random(seed1);
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#10 datain = $random(seed);
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#10 datain = $random(seed1);
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#10 datain = $random(seed);
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#10 datain = $random(seed);
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#10 datain = 8'hF0;
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#10 datain = 8'hAC;
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#10 datain = 8'h1C;
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//Continue upto 239 bytes. Here only a partial list has been fed.
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//End feeding message data. The registers contain parity bytes now. The parity and
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//message bytes togather form code bytes.
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//From next clock cylcle on, the parity bytes generated is fed into the machine as if the
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//parity bytes are message bytes. In other words, the entire code polynomial is shifted
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// into the machine. This will result in zero register values at the end of shift
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//sequence. Reason: code polynomial divides generator polynomial so the remainder should be zero.
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//Feeding message polynomial followed by remainder polynomial implies code polynomial has been
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//fed to the machine. This implies the contents of registers q15, q14, ...........q1. q0 contains
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//the remainder of division between code polynomial and generator polynomial. The result should be
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//all zero bytes. Check to see contents of q15........q0 are 8'h00.
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#4 tmp_reg1 = {q3, q2, q1, q0};
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tmp_reg2 = {q7, q6, q5, q4};
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tmp_reg3 = {q11, q10, q9, q8};
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tmp_reg4 = {q15, q14, q13, q12};
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#6 datain = tmp_reg4[31:24];
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#10 datain = tmp_reg4[23:16];
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#10 datain = tmp_reg4[15:8];
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#10 datain = tmp_reg4[7:0];
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#10 datain = tmp_reg3[31:24];
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#10 datain = tmp_reg3[23:16];
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#10 datain = tmp_reg3[15:8];
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#10 datain = tmp_reg3[7:0];
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#10 datain = tmp_reg2[31:24];
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#10 datain = tmp_reg2[23:16];
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#10 datain = tmp_reg2[15:8];
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#10 datain = tmp_reg2[7:0];
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#10 datain = tmp_reg1[31:24];
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#10 datain = tmp_reg1[23:16];
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#10 datain = tmp_reg1[15:8];
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#10 datain = tmp_reg1[7:0];
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//Stop the state machine after the entire code polynomial is shifted, using valid signal. Pulling valid low will
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// freeze the machine with its register contents.
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#10 valid = 0;
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#30 $finish;
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end
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always #5 clk = ~clk;
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//assign generator polynomial co-efficients here. The generator polynomial is
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//of form X^16+g15X^15+g14X^14 + ..................+g1X+g0;
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//Each gi (i=0, 1, ...15) is an element of GF(2^8);
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//Here they have been randomly assigned. Assign actual values.
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assign gin0 = 8'b00010000;
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assign gin1 = 8'hAB;
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assign gin2 = 8'hCD;
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assign gin3 = 8'h8E;
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assign gin4 = 8'h93;
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assign gin5=8'hAB; assign gin6=8'h8E; assign gin7=8'hCD;
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assign gin8=8'hFA;
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assign gin9=8'hEE; assign gin10=8'hFF; assign gin11=8'h0C; assign gin12=8'hAB;
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assign gin13= 8'h26; assign gin14=8'h35; assign gin15=8'h89;
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rs_encode U1(datain, valid, gin0, gin1, gin2, gin3, gin4, gin5, gin6, gin7, gin8, gin9,
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gin10, gin11, gin12, gin13, gin14, gin15, q0, q1, q2, q3, q4, q5, q6, q7, q8,
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q9, q10, q11, q12, q13, q14, q15, rst, clk);
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endmodule
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