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// ============================================================================
//  ALU
//  - perform datapath operations
//
//
//  (C) 2009-2012  Robert Finch
//  robfinch[remove]@opencores.org
//
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
//
//  Verilog 
//
// ============================================================================
//
function carry;
        input op;
        input a;
        input b;
        input s;
 
        begin
                carry = op ? (~a&b)|(s&~a)|(s&b) : (a&b)|(a&~s)|(b&~s);
        end
 
endfunction
 
function overflow;
        input op;
        input a;
        input b;
        input s;
 
        begin
                overflow = (op ^ s ^ b) & (~op ^ a ^ b);
        end
 
endfunction
 
reg [15:0] alu_o;
reg [15:0] a;
reg [15:0] b;
wire amsb = w ? a[15] : a[7];
wire bmsb = w ? b[15] : b[7];
wire [15:0] as = {!a[15],a[14:0]};
wire [15:0] bs = {!b[15],b[14:0]};
wire signed [15:0] sa = a;
wire signed [15:0] sb = b;
wire signed [7:0] als = a[7:0];
wire signed [7:0] bls = b[7:0];
wire signed [15:0] p = als * bls;
wire signed [31:0] wp = sa * sb;
 
// Compute AL/10
// - multiply by 1/10 = 26/256
wire [15:0] al26 = {al,4'b0} + {al,3'b0} + {al,1'b0};    // * 26
wire [7:0] aldv10 = al26[15:8];  // 256
 
wire [15:0] cmp_o = a - b;
wire eq  = a == b;
wire ltu = a < b;
wire lt  = as < bs;
 
always @(ir or ir2 or a or b or cf or af or al or ah or aldv10 or TTT)
        begin
                casex(ir)
                `MOV_M2AL,`MOV_M2AX,`LDS,`LES:
                        alu_o <= a;
                `MOV_MR,`MOV_R2S,
                `MOV_RR8,`MOV_RR16,
                `MOV_I8M,`MOV_I16M,
                `MOV_I2AL,`MOV_I2DL,`MOV_I2CL,`MOV_I2BL,`MOV_I2AH,`MOV_I2DH,`MOV_I2CH,`MOV_I2BH,
                `MOV_I2AX,`MOV_I2DX,`MOV_I2CX,`MOV_I2BX,`MOV_I2SP,`MOV_I2BP,`MOV_I2SI,`MOV_I2DI:
                        alu_o <= b;
                `XCHG_MEM:
                        alu_o <= b;
                `ADD,`ADD_ALI8,`ADD_AXI16: alu_o <= a + b;
                `SUB,`SUB_ALI8,`SUB_AXI16: alu_o <= a - b;
                `ADC,`ADC_ALI8,`ADC_AXI16: alu_o <= a + b + cf;
                `SBB,`SBB_ALI8,`SBB_AXI16: alu_o <= a - b - cf;
                `AND,`AND_ALI8,`AND_AXI16: alu_o <= a & b;
                `OR, `OR_ALI8, `OR_AXI16:  alu_o <= a | b;
                `XOR,`XOR_ALI8,`XOR_AXI16: alu_o <= a ^ b;
                `CMP,`CMP_ALI8,`CMP_AXI16: alu_o <= a - b;
                `SCASB,`SCASW,`CMPSB,`CMPSW: alu_o <= a - b;
                `INC_REG: alu_o <= a + 16'd1;
                `DEC_REG: alu_o <= a - 16'd1;
                `IMUL: alu_o <= w ? p : wp[15:0];
                `ALU_I2R8:
                        case(TTT)
                        3'd0:   alu_o <= a + b;                 // ADD
                        3'd1:   alu_o <= a | b;                 // OR
                        3'd2:   alu_o <= a + b + cf;    // ADC
                        3'd3:   alu_o <= a - b - cf;    // SBB
                        3'd4:   alu_o <= a & b;                 // AND
                        3'd5:   alu_o <= a - b;                 // SUB
                        3'd6:   alu_o <= a ^ b;                 // XOR
                        default:        alu_o <= 16'h0000;
                        endcase
                // ToDo: fix sign extension / extra immediate byte ?
                `ALU_I2R16:
                        case(TTT)
                        3'd0:   alu_o <= a + b;                 // ADD
                        3'd1:   alu_o <= a | b;                 // OR
                        3'd2:   alu_o <= a + b + cf;    // ADC
                        3'd3:   alu_o <= a - b - cf;    // SBB
                        3'd4:   alu_o <= a & b;                 // AND
                        3'd5:   alu_o <= a - b;                 // SUB
                        3'd6:   alu_o <= a ^ b;                 // XOR
                        default:        alu_o <= 16'h0000;
                        endcase
                `AAA:
                        if (al[3:0]>4'h9 || af) begin
                                alu_o[3:0] <= al[3:0] + 4'd6;
                                alu_o[7:4] <= 4'h0;
                                alu_o[15:8] <= ah + 8'd1;
                        end
                        else
                                alu_o <= ax;
                `AAS:
                        if (al[3:0]>4'h9 || af) begin
                                alu_o[3:0] <= al[3:0] - 4'd6;
                                alu_o[7:4] <= 4'h0;
                                alu_o[15:8] <= ah - 8'd1;
                        end
                        else
                                alu_o <= ax;
// ToDo: fix +1 carry
                `DAA:
                        begin
                                alu_o <= 16'h0000;
                                if (al[3:0]>4'h9 || af) begin
                                        alu_o[3:0] <= al[3:0] + 4'd6;
                                end
                                if (al[7:4]>4'h9 || cf) begin
                                        alu_o[7:4] <= al[7:4] + 4'd6;
                                end
                        end
// ToDo: fix +1 carry
                `DAS:
                        begin
                                alu_o <= 16'h0000;
                                if (al[3:0]>4'h9 || af) begin
                                        alu_o[3:0] <= al[3:0] - 4'd6;
                                end
                                if (al[7:4]>4'h9 || cf) begin
                                        alu_o[7:4] <= al[7:4] - 4'd6;
                                end
                        end
 
                `MORE1:
                        casex(ir2)
                        `AAM:
                                begin
                                        alu_o[ 7:0] <= al - aldv10;
                                        alu_o[15:8] <= aldv10;
                                end
                        default:
                                alu_o <= 16'h0000;
                        endcase
                `MORE2:
                        casex(ir2)
                        `AAD:
                                begin
                                        alu_o[ 7:0] <= {ah,3'b0} + {ah,1'b0} + al;
                                        alu_o[15:8] <= 8'h00;
                                end
                        default:
                                alu_o <= 16'h0000;
                        endcase
                default: alu_o <= 16'h0000;
                endcase
        end
 
assign pres = ~^alu_o[7:0];
assign reszw = alu_o==16'h0000;
assign reszb = alu_o[7:0]==8'h00;
assign resnb = alu_o[7];
assign resnw = alu_o[15];
 
assign resz = w ? reszw : reszb;
assign resn = w ? resnw : resnb;
 

Line No.	Rev	Author	Line
1	2	robfinch	`// ============================================================================`
2			`// ALU`
3			`// - perform datapath operations`
4			`//`
5			`//`
6			`// (C) 2009-2012 Robert Finch`
7			`// robfinch[remove]@opencores.org`
8			`//`
9			`//`
10			`// This source file is free software: you can redistribute it and/or modify`
11			`// it under the terms of the GNU Lesser General Public License as published`
12			`// by the Free Software Foundation, either version 3 of the License, or`
13			`// (at your option) any later version.`
14			`//`
15			`// This source file is distributed in the hope that it will be useful,`
16			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
17			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
18			`// GNU General Public License for more details.`
19			`//`
20			`// You should have received a copy of the GNU General Public License`
21			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
22			`//`
23			`//`
24			`// Verilog`
25			`//`
26			`// ============================================================================`
27			`//`
28			`function carry;`
29			`input op;`
30			`input a;`
31			`input b;`
32			`input s;`
33
34			`begin`
35			`carry = op ? (~a&b)\|(s&~a)\|(s&b) : (a&b)\|(a&~s)\|(b&~s);`
36			`end`
37
38			`endfunction`
39
40			`function overflow;`
41			`input op;`
42			`input a;`
43			`input b;`
44			`input s;`
45
46			`begin`
47			`overflow = (op ^ s ^ b) & (~op ^ a ^ b);`
48			`end`
49
50			`endfunction`
51
52			`reg [15:0] alu_o;`
53			`reg [15:0] a;`
54			`reg [15:0] b;`
55			`wire amsb = w ? a[15] : a[7];`
56			`wire bmsb = w ? b[15] : b[7];`
57			`wire [15:0] as = {!a[15],a[14:0]};`
58			`wire [15:0] bs = {!b[15],b[14:0]};`
59			`wire signed [15:0] sa = a;`
60			`wire signed [15:0] sb = b;`
61			`wire signed [7:0] als = a[7:0];`
62			`wire signed [7:0] bls = b[7:0];`
63			`wire signed [15:0] p = als * bls;`
64			`wire signed [31:0] wp = sa * sb;`
65
66			`// Compute AL/10`
67			`// - multiply by 1/10 = 26/256`
68			`wire [15:0] al26 = {al,4'b0} + {al,3'b0} + {al,1'b0}; // * 26`
69			`wire [7:0] aldv10 = al26[15:8]; // 256`
70
71			`wire [15:0] cmp_o = a - b;`
72			`wire eq = a == b;`
73			`wire ltu = a < b;`
74			`wire lt = as < bs;`
75
76			`always @(ir or ir2 or a or b or cf or af or al or ah or aldv10 or TTT)`
77			`begin`
78			`casex(ir)`
79			`MOV_M2AL,`MOV_M2AX,`LDS,`LES:
80			`alu_o <= a;`
81			`MOV_MR,`MOV_R2S,
82			`MOV_RR8,`MOV_RR16,
83			`MOV_I8M,`MOV_I16M,
84			`MOV_I2AL,`MOV_I2DL,`MOV_I2CL,`MOV_I2BL,`MOV_I2AH,`MOV_I2DH,`MOV_I2CH,`MOV_I2BH,
85			`MOV_I2AX,`MOV_I2DX,`MOV_I2CX,`MOV_I2BX,`MOV_I2SP,`MOV_I2BP,`MOV_I2SI,`MOV_I2DI:
86			`alu_o <= b;`
87			`XCHG_MEM:
88			`alu_o <= b;`
89			`ADD,`ADD_ALI8,`ADD_AXI16: alu_o <= a + b;
90			`SUB,`SUB_ALI8,`SUB_AXI16: alu_o <= a - b;
91			`ADC,`ADC_ALI8,`ADC_AXI16: alu_o <= a + b + cf;
92			`SBB,`SBB_ALI8,`SBB_AXI16: alu_o <= a - b - cf;
93			`AND,`AND_ALI8,`AND_AXI16: alu_o <= a & b;
94			`OR, `OR_ALI8, `OR_AXI16: alu_o <= a \| b;
95			`XOR,`XOR_ALI8,`XOR_AXI16: alu_o <= a ^ b;
96			`CMP,`CMP_ALI8,`CMP_AXI16: alu_o <= a - b;
97			`SCASB,`SCASW,`CMPSB,`CMPSW: alu_o <= a - b;
98			`INC_REG: alu_o <= a + 16'd1;
99			`DEC_REG: alu_o <= a - 16'd1;
100			`IMUL: alu_o <= w ? p : wp[15:0];
101			`ALU_I2R8:
102			`case(TTT)`
103			`3'd0: alu_o <= a + b; // ADD`
104			`3'd1: alu_o <= a \| b; // OR`
105			`3'd2: alu_o <= a + b + cf; // ADC`
106			`3'd3: alu_o <= a - b - cf; // SBB`
107			`3'd4: alu_o <= a & b; // AND`
108			`3'd5: alu_o <= a - b; // SUB`
109			`3'd6: alu_o <= a ^ b; // XOR`
110			`default: alu_o <= 16'h0000;`
111			`endcase`
112			`// ToDo: fix sign extension / extra immediate byte ?`
113			`ALU_I2R16:
114			`case(TTT)`
115			`3'd0: alu_o <= a + b; // ADD`
116			`3'd1: alu_o <= a \| b; // OR`
117			`3'd2: alu_o <= a + b + cf; // ADC`
118			`3'd3: alu_o <= a - b - cf; // SBB`
119			`3'd4: alu_o <= a & b; // AND`
120			`3'd5: alu_o <= a - b; // SUB`
121			`3'd6: alu_o <= a ^ b; // XOR`
122			`default: alu_o <= 16'h0000;`
123			`endcase`
124			`AAA:
125			`if (al[3:0]>4'h9 \|\| af) begin`
126			`alu_o[3:0] <= al[3:0] + 4'd6;`
127			`alu_o[7:4] <= 4'h0;`
128			`alu_o[15:8] <= ah + 8'd1;`
129			`end`
130			`else`
131			`alu_o <= ax;`
132			`AAS:
133			`if (al[3:0]>4'h9 \|\| af) begin`
134			`alu_o[3:0] <= al[3:0] - 4'd6;`
135			`alu_o[7:4] <= 4'h0;`
136			`alu_o[15:8] <= ah - 8'd1;`
137			`end`
138			`else`
139			`alu_o <= ax;`
140			`// ToDo: fix +1 carry`
141			`DAA:
142			`begin`
143			`alu_o <= 16'h0000;`
144			`if (al[3:0]>4'h9 \|\| af) begin`
145			`alu_o[3:0] <= al[3:0] + 4'd6;`
146			`end`
147			`if (al[7:4]>4'h9 \|\| cf) begin`
148			`alu_o[7:4] <= al[7:4] + 4'd6;`
149			`end`
150			`end`
151			`// ToDo: fix +1 carry`
152			`DAS:
153			`begin`
154			`alu_o <= 16'h0000;`
155			`if (al[3:0]>4'h9 \|\| af) begin`
156			`alu_o[3:0] <= al[3:0] - 4'd6;`
157			`end`
158			`if (al[7:4]>4'h9 \|\| cf) begin`
159			`alu_o[7:4] <= al[7:4] - 4'd6;`
160			`end`
161			`end`
162
163			`MORE1:
164			`casex(ir2)`
165			`AAM:
166			`begin`
167			`alu_o[ 7:0] <= al - aldv10;`
168			`alu_o[15:8] <= aldv10;`
169			`end`
170			`default:`
171			`alu_o <= 16'h0000;`
172			`endcase`
173			`MORE2:
174			`casex(ir2)`
175			`AAD:
176			`begin`
177			`alu_o[ 7:0] <= {ah,3'b0} + {ah,1'b0} + al;`
178			`alu_o[15:8] <= 8'h00;`
179			`end`
180			`default:`
181			`alu_o <= 16'h0000;`
182			`endcase`
183			`default: alu_o <= 16'h0000;`
184			`endcase`
185			`end`
186
187			`assign pres = ~^alu_o[7:0];`
188			`assign reszw = alu_o==16'h0000;`
189			`assign reszb = alu_o[7:0]==8'h00;`
190			`assign resnb = alu_o[7];`
191			`assign resnw = alu_o[15];`
192
193			`assign resz = w ? reszw : reszb;`
194			`assign resn = w ? resnw : resnb;`
195

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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [ALU.v] - Blame information for rev 2