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// ============================================================================
//  ALU
//  - perform datapath operations
//
//
//  (C) 2009-2013  Robert Finch
//  robfinch[remove]@finitron.ca
//
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
//
//  Verilog 
//
// ============================================================================
//
function carry;
        input op;
        input a;
        input b;
        input s;
 
        begin
                carry = op ? (~a&b)|(s&~a)|(s&b) : (a&b)|(a&~s)|(b&~s);
        end
 
endfunction
 
function overflow;
        input op;
        input a;
        input b;
        input s;
 
        begin
                overflow = (op ^ s ^ b) & (~op ^ a ^ b);
        end
 
endfunction
 
reg [15:0] alu_o;
reg [15:0] a;
reg [15:0] b;
wire amsb = w ? a[15] : a[7];
wire bmsb = w ? b[15] : b[7];
wire [15:0] as = {!a[15],a[14:0]};
wire [15:0] bs = {!b[15],b[14:0]};
wire signed [15:0] sa = a;
wire signed [15:0] sb = b;
wire signed [7:0] als = a[7:0];
wire signed [7:0] bls = b[7:0];
wire signed [15:0] p = als * bls;
wire signed [31:0] wp = sa * sb;
wire [15:0] p16 = a[7:0] * b[7:0];
wire [31:0] p32 = a * b;
 
// Compute AL/10
// - multiply by 1/10 = 26/256
wire [15:0] al26 = {al,4'b0} + {al,3'b0} + {al,1'b0};    // * 26
wire [7:0] aldv10 = al26[15:8];  // 256
 
wire [15:0] cmp_o = a - b;
wire eq  = a == b;
wire ltu = a < b;
wire lt  = as < bs;
 
wire [31:0] shlo = {16'h0000,b} << shftamt;
wire [31:0] shruo = {b,16'h0000} >> shftamt;
wire [15:0] shro = ~(~b >> shftamt);
wire [32:0] shlco = {16'h0000,b,cf} << shftamt;
wire [32:0] shrcuo = {cf,b,16'h0000} >> shftamt;
 
wire [15:0] shlo8 = {8'h00,b[7:0]} << shftamt;
wire [15:0] shruo8 = {b[7:0],8'h00} >> shftamt;
wire [ 7:0] shro8 = ~(~b[7:0] >> shftamt);
wire [16:0] shlco8 = {8'h00,b,cf} << shftamt;
wire [16:0] shrcuo8 = {cf,b[7:0],8'h00} >> shftamt;
 
wire div16_done;
wire div32_done;
wire [15:0] q16;
wire [7:0] r16;
wire [31:0] q32;
wire [15:0] r32;
wire [31:0] negdxax = -{dx,ax};
 
divr2 #(16) udiv1
(
        .rst(rst_i),
        .clk(clk_i),
        .ce(1'b1),
        .ld(ld_div16),
        .su(TTT[0]),
        .ri(1'b0),
        .a(ax),
        .b(b[7:0]),
        .i(8'h00),
        .q(q16),
        .r(r16),
        .divByZero(),
        .done(div16_done)
);
 
 
divr2 #(32) udiv2
(
        .rst(rst_i),
        .clk(clk_i),
        .ce(1'b1),
        .ld(ld_div32),
        .su(TTT[0]),
        .ri(1'b0),
        .a({dx,ax}),
        .b(b),
        .i(16'h0000),
        .q(q32),
        .r(r32),
        .divByZero(),
        .done(div32_done)
);
 
 
always @*       //(ir or ir2 or a or b or cf or af or al or ah or aldv10 or TTT)
        begin
                casex(ir)
                `MOV_M2AL,`MOV_M2AX,`LDS,`LES:
                        alu_o <= a;
                `MOV_MR,`MOV_R2S,
                `MOV_RR8,`MOV_RR16,
                `MOV_I8M,`MOV_I16M,
                `MOV_I2AL,`MOV_I2DL,`MOV_I2CL,`MOV_I2BL,`MOV_I2AH,`MOV_I2DH,`MOV_I2CH,`MOV_I2BH,
                `MOV_I2AX,`MOV_I2DX,`MOV_I2CX,`MOV_I2BX,`MOV_I2SP,`MOV_I2BP,`MOV_I2SI,`MOV_I2DI:
                        alu_o <= b;
                `XCHG_MEM:
                        alu_o <= b;
                `ADD,`ADD_ALI8,`ADD_AXI16: alu_o <= a + b;
                `SUB,`SUB_ALI8,`SUB_AXI16: alu_o <= a - b;
                `ADC,`ADC_ALI8,`ADC_AXI16: alu_o <= a + b + cf;
                `SBB,`SBB_ALI8,`SBB_AXI16: alu_o <= a - b - cf;
                `AND,`AND_ALI8,`AND_AXI16: alu_o <= a & b;
                `TEST,`TEST_ALI8,`TEST_AXI16: alu_o <= a & b;
                `OR, `OR_ALI8, `OR_AXI16:  alu_o <= a | b;
                `XOR,`XOR_ALI8,`XOR_AXI16: alu_o <= a ^ b;
                `CMP,`CMP_ALI8,`CMP_AXI16: alu_o <= a - b;
                `SCASB,`SCASW,`CMPSB,`CMPSW: alu_o <= a - b;
                `INC_REG: alu_o <= a + 16'd1;
                `DEC_REG: alu_o <= a - 16'd1;
//              `IMUL: alu_o <= w ? p : wp[15:0];
                `ALU_I2R8:
                        case(TTT)
                        3'd0:   alu_o <= a + b;                 // ADD
                        3'd1:   alu_o <= a | b;                 // OR
                        3'd2:   alu_o <= a + b + cf;    // ADC
                        3'd3:   alu_o <= a - b - cf;    // SBB
                        3'd4:   alu_o <= a & b;                 // AND
                        3'd5:   alu_o <= a - b;                 // SUB
                        3'd6:   alu_o <= a ^ b;                 // XOR
                        default:        alu_o <= 16'h0000;
                        endcase
                // ToDo: fix sign extension / extra immediate byte ?
                `ALU_I2R16:
                        case(TTT)
                        3'd0:   alu_o <= a + b;                 // ADD
                        3'd1:   alu_o <= a | b;                 // OR
                        3'd2:   alu_o <= a + b + cf;    // ADC
                        3'd3:   alu_o <= a - b - cf;    // SBB
                        3'd4:   alu_o <= a & b;                 // AND
                        3'd5:   alu_o <= a - b;                 // SUB
                        3'd6:   alu_o <= a ^ b;                 // XOR
                        default:        alu_o <= 16'h0000;
                        endcase
                8'hF6,8'hF7:
                        begin
                        case(TTT)
                        3'd0:   alu_o <= a & b;                 // TEST
                        3'd2:   alu_o <= ~b;                    // NOT
                        3'd3:   alu_o <= -b;                    // NEG
                        3'd4:   alu_o <= w ? p32[15:0] : p16;            // MUL
                        3'd5:   alu_o <= w ? wp[15:0] : p[15:0];  // IMUL
                        3'd6:   alu_o <= 16'h0000;              // DIV
                        3'd7:   alu_o <= 16'h0000;              // IDIV
                        default:        alu_o <= 16'h0000;
                        endcase
                        end
                `AAA:
                        if (al[3:0]>4'h9 || af) begin
                                alu_o[3:0] <= al[3:0] + 4'd6;
                                alu_o[7:4] <= 4'h0;
                                alu_o[15:8] <= ah + 8'd1;
                        end
                        else
                                alu_o <= ax;
                `AAS:
                        if (al[3:0]>4'h9 || af) begin
                                alu_o[3:0] <= al[3:0] - 4'd6;
                                alu_o[7:4] <= 4'h0;
                                alu_o[15:8] <= ah - 8'd1;
                        end
                        else
                                alu_o <= ax;
// ToDo: fix +1 carry
                `DAA:
                        begin
                                alu_o <= 16'h0000;
                                if (al[3:0]>4'h9 || af) begin
                                        alu_o[3:0] <= al[3:0] + 4'd6;
                                end
                                if (al[7:4]>4'h9 || cf) begin
                                        alu_o[7:4] <= al[7:4] + 4'd6;
                                end
                        end
// ToDo: fix +1 carry
                `DAS:
                        begin
                                alu_o <= 16'h0000;
                                if (al[3:0]>4'h9 || af) begin
                                        alu_o[3:0] <= al[3:0] - 4'd6;
                                end
                                if (al[7:4]>4'h9 || cf) begin
                                        alu_o[7:4] <= al[7:4] - 4'd6;
                                end
                        end
 
                `MORE1:
                        casex(ir2)
                        `AAM:
                                begin
                                        alu_o[ 7:0] <= al - aldv10;
                                        alu_o[15:8] <= aldv10;
                                end
                        default:
                                alu_o <= 16'h0000;
                        endcase
                `MORE2:
                        casex(ir2)
                        `AAD:
                                begin
                                        alu_o[ 7:0] <= {ah,3'b0} + {ah,1'b0} + al;
                                        alu_o[15:8] <= 8'h00;
                                end
                        default:
                                alu_o <= 16'h0000;
                        endcase
                default: alu_o <= 16'h0000;
                endcase
        end
 
assign pres = ~^alu_o[7:0];
assign reszw = alu_o==16'h0000;
assign reszb = alu_o[7:0]==8'h00;
assign resnb = alu_o[7];
assign resnw = alu_o[15];
 
assign resz = w ? reszw : reszb;
assign resn = w ? resnw : resnb;
 

Line No.	Rev	Author	Line
1	2	robfinch	`// ============================================================================`
2			`// ALU`
3			`// - perform datapath operations`
4			`//`
5			`//`
6	8	robfinch	`// (C) 2009-2013 Robert Finch`
7			`// robfinch[remove]@finitron.ca`
8	2	robfinch	`//`
9			`//`
10			`// This source file is free software: you can redistribute it and/or modify`
11			`// it under the terms of the GNU Lesser General Public License as published`
12			`// by the Free Software Foundation, either version 3 of the License, or`
13			`// (at your option) any later version.`
14			`//`
15			`// This source file is distributed in the hope that it will be useful,`
16			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
17			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
18			`// GNU General Public License for more details.`
19			`//`
20			`// You should have received a copy of the GNU General Public License`
21			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
22			`//`
23			`//`
24			`// Verilog`
25			`//`
26			`// ============================================================================`
27			`//`
28			`function carry;`
29			`input op;`
30			`input a;`
31			`input b;`
32			`input s;`
33
34			`begin`
35			`carry = op ? (~a&b)\|(s&~a)\|(s&b) : (a&b)\|(a&~s)\|(b&~s);`
36			`end`
37
38			`endfunction`
39
40			`function overflow;`
41			`input op;`
42			`input a;`
43			`input b;`
44			`input s;`
45
46			`begin`
47			`overflow = (op ^ s ^ b) & (~op ^ a ^ b);`
48			`end`
49
50			`endfunction`
51
52			`reg [15:0] alu_o;`
53			`reg [15:0] a;`
54			`reg [15:0] b;`
55			`wire amsb = w ? a[15] : a[7];`
56			`wire bmsb = w ? b[15] : b[7];`
57			`wire [15:0] as = {!a[15],a[14:0]};`
58			`wire [15:0] bs = {!b[15],b[14:0]};`
59			`wire signed [15:0] sa = a;`
60			`wire signed [15:0] sb = b;`
61			`wire signed [7:0] als = a[7:0];`
62			`wire signed [7:0] bls = b[7:0];`
63			`wire signed [15:0] p = als * bls;`
64			`wire signed [31:0] wp = sa * sb;`
65	6	robfinch	`wire [15:0] p16 = a[7:0] * b[7:0];`
66			`wire [31:0] p32 = a * b;`
67	2	robfinch
68			`// Compute AL/10`
69			`// - multiply by 1/10 = 26/256`
70			`wire [15:0] al26 = {al,4'b0} + {al,3'b0} + {al,1'b0}; // * 26`
71			`wire [7:0] aldv10 = al26[15:8]; // 256`
72
73			`wire [15:0] cmp_o = a - b;`
74			`wire eq = a == b;`
75			`wire ltu = a < b;`
76			`wire lt = as < bs;`
77
78	4	robfinch	`wire [31:0] shlo = {16'h0000,b} << shftamt;`
79			`wire [31:0] shruo = {b,16'h0000} >> shftamt;`
80			`wire [15:0] shro = ~(~b >> shftamt);`
81			`wire [32:0] shlco = {16'h0000,b,cf} << shftamt;`
82			`wire [32:0] shrcuo = {cf,b,16'h0000} >> shftamt;`
83
84			`wire [15:0] shlo8 = {8'h00,b[7:0]} << shftamt;`
85			`wire [15:0] shruo8 = {b[7:0],8'h00} >> shftamt;`
86			`wire [ 7:0] shro8 = ~(~b[7:0] >> shftamt);`
87			`wire [16:0] shlco8 = {8'h00,b,cf} << shftamt;`
88			`wire [16:0] shrcuo8 = {cf,b[7:0],8'h00} >> shftamt;`
89
90	6	robfinch	`wire div16_done;`
91			`wire div32_done;`
92			`wire [15:0] q16;`
93			`wire [7:0] r16;`
94			`wire [31:0] q32;`
95			`wire [15:0] r32;`
96			`wire [31:0] negdxax = -{dx,ax};`
97	4	robfinch
98	6	robfinch	`divr2 #(16) udiv1`
99			`(`
100			`.rst(rst_i),`
101			`.clk(clk_i),`
102			`.ce(1'b1),`
103			`.ld(ld_div16),`
104			`.su(TTT[0]),`
105			`.ri(1'b0),`
106			`.a(ax),`
107			`.b(b[7:0]),`
108			`.i(8'h00),`
109			`.q(q16),`
110			`.r(r16),`
111			`.divByZero(),`
112			`.done(div16_done)`
113			`);`
114
115
116			`divr2 #(32) udiv2`
117			`(`
118			`.rst(rst_i),`
119			`.clk(clk_i),`
120			`.ce(1'b1),`
121			`.ld(ld_div32),`
122			`.su(TTT[0]),`
123			`.ri(1'b0),`
124			`.a({dx,ax}),`
125			`.b(b),`
126			`.i(16'h0000),`
127			`.q(q32),`
128			`.r(r32),`
129			`.divByZero(),`
130			`.done(div32_done)`
131			`);`
132
133
134	8	robfinch	`always @* //(ir or ir2 or a or b or cf or af or al or ah or aldv10 or TTT)`
135	2	robfinch	`begin`
136			`casex(ir)`
137			`MOV_M2AL,`MOV_M2AX,`LDS,`LES:
138			`alu_o <= a;`
139			`MOV_MR,`MOV_R2S,
140			`MOV_RR8,`MOV_RR16,
141			`MOV_I8M,`MOV_I16M,
142			`MOV_I2AL,`MOV_I2DL,`MOV_I2CL,`MOV_I2BL,`MOV_I2AH,`MOV_I2DH,`MOV_I2CH,`MOV_I2BH,
143			`MOV_I2AX,`MOV_I2DX,`MOV_I2CX,`MOV_I2BX,`MOV_I2SP,`MOV_I2BP,`MOV_I2SI,`MOV_I2DI:
144			`alu_o <= b;`
145			`XCHG_MEM:
146			`alu_o <= b;`
147			`ADD,`ADD_ALI8,`ADD_AXI16: alu_o <= a + b;
148			`SUB,`SUB_ALI8,`SUB_AXI16: alu_o <= a - b;
149			`ADC,`ADC_ALI8,`ADC_AXI16: alu_o <= a + b + cf;
150			`SBB,`SBB_ALI8,`SBB_AXI16: alu_o <= a - b - cf;
151			`AND,`AND_ALI8,`AND_AXI16: alu_o <= a & b;
152	6	robfinch	`TEST,`TEST_ALI8,`TEST_AXI16: alu_o <= a & b;
153	2	robfinch	`OR, `OR_ALI8, `OR_AXI16: alu_o <= a \| b;
154			`XOR,`XOR_ALI8,`XOR_AXI16: alu_o <= a ^ b;
155			`CMP,`CMP_ALI8,`CMP_AXI16: alu_o <= a - b;
156			`SCASB,`SCASW,`CMPSB,`CMPSW: alu_o <= a - b;
157			`INC_REG: alu_o <= a + 16'd1;
158			`DEC_REG: alu_o <= a - 16'd1;
159	8	robfinch	// `IMUL: alu_o <= w ? p : wp[15:0];
160	2	robfinch	`ALU_I2R8:
161			`case(TTT)`
162			`3'd0: alu_o <= a + b; // ADD`
163			`3'd1: alu_o <= a \| b; // OR`
164			`3'd2: alu_o <= a + b + cf; // ADC`
165			`3'd3: alu_o <= a - b - cf; // SBB`
166			`3'd4: alu_o <= a & b; // AND`
167			`3'd5: alu_o <= a - b; // SUB`
168			`3'd6: alu_o <= a ^ b; // XOR`
169			`default: alu_o <= 16'h0000;`
170			`endcase`
171			`// ToDo: fix sign extension / extra immediate byte ?`
172			`ALU_I2R16:
173			`case(TTT)`
174			`3'd0: alu_o <= a + b; // ADD`
175			`3'd1: alu_o <= a \| b; // OR`
176			`3'd2: alu_o <= a + b + cf; // ADC`
177			`3'd3: alu_o <= a - b - cf; // SBB`
178			`3'd4: alu_o <= a & b; // AND`
179			`3'd5: alu_o <= a - b; // SUB`
180			`3'd6: alu_o <= a ^ b; // XOR`
181			`default: alu_o <= 16'h0000;`
182			`endcase`
183	6	robfinch	`8'hF6,8'hF7:`
184	8	robfinch	`begin`
185	6	robfinch	`case(TTT)`
186			`3'd0: alu_o <= a & b; // TEST`
187			`3'd2: alu_o <= ~b; // NOT`
188			`3'd3: alu_o <= -b; // NEG`
189			`3'd4: alu_o <= w ? p32[15:0] : p16; // MUL`
190			`3'd5: alu_o <= w ? wp[15:0] : p[15:0]; // IMUL`
191			`3'd6: alu_o <= 16'h0000; // DIV`
192			`3'd7: alu_o <= 16'h0000; // IDIV`
193			`default: alu_o <= 16'h0000;`
194			`endcase`
195	8	robfinch	`end`
196	2	robfinch	`AAA:
197			`if (al[3:0]>4'h9 \|\| af) begin`
198			`alu_o[3:0] <= al[3:0] + 4'd6;`
199			`alu_o[7:4] <= 4'h0;`
200			`alu_o[15:8] <= ah + 8'd1;`
201			`end`
202			`else`
203			`alu_o <= ax;`
204			`AAS:
205			`if (al[3:0]>4'h9 \|\| af) begin`
206			`alu_o[3:0] <= al[3:0] - 4'd6;`
207			`alu_o[7:4] <= 4'h0;`
208			`alu_o[15:8] <= ah - 8'd1;`
209			`end`
210			`else`
211			`alu_o <= ax;`
212			`// ToDo: fix +1 carry`
213			`DAA:
214			`begin`
215			`alu_o <= 16'h0000;`
216			`if (al[3:0]>4'h9 \|\| af) begin`
217			`alu_o[3:0] <= al[3:0] + 4'd6;`
218			`end`
219			`if (al[7:4]>4'h9 \|\| cf) begin`
220			`alu_o[7:4] <= al[7:4] + 4'd6;`
221			`end`
222			`end`
223			`// ToDo: fix +1 carry`
224			`DAS:
225			`begin`
226			`alu_o <= 16'h0000;`
227			`if (al[3:0]>4'h9 \|\| af) begin`
228			`alu_o[3:0] <= al[3:0] - 4'd6;`
229			`end`
230			`if (al[7:4]>4'h9 \|\| cf) begin`
231			`alu_o[7:4] <= al[7:4] - 4'd6;`
232			`end`
233			`end`
234
235			`MORE1:
236			`casex(ir2)`
237			`AAM:
238			`begin`
239			`alu_o[ 7:0] <= al - aldv10;`
240			`alu_o[15:8] <= aldv10;`
241			`end`
242			`default:`
243			`alu_o <= 16'h0000;`
244			`endcase`
245			`MORE2:
246			`casex(ir2)`
247			`AAD:
248			`begin`
249			`alu_o[ 7:0] <= {ah,3'b0} + {ah,1'b0} + al;`
250			`alu_o[15:8] <= 8'h00;`
251			`end`
252			`default:`
253			`alu_o <= 16'h0000;`
254			`endcase`
255			`default: alu_o <= 16'h0000;`
256			`endcase`
257			`end`
258
259			`assign pres = ~^alu_o[7:0];`
260			`assign reszw = alu_o==16'h0000;`
261			`assign reszb = alu_o[7:0]==8'h00;`
262			`assign resnb = alu_o[7];`
263			`assign resnw = alu_o[15];`
264
265			`assign resz = w ? reszw : reszb;`
266			`assign resn = w ? resnw : resnb;`
267

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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [ALU.v] - Blame information for rev 8