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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [DECODE.v] - Blame information for rev 8

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// ============================================================================
//  DECODE
//  - decode / dispatch instruction
//
//
//  (C) 2009-2012  Robert Finch
//  Stratford
//  robfinch[remove]@opencores.org
//
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
//
//  Verilog 
//
// Decode / dispatch instruction
// ============================================================================
//
DECODE:
        casex(ir)
        `MORE1: state <= XI_FETCH;
        `MORE2: state <= XI_FETCH;
        `EXTOP: state <= XI_FETCH;
 
        `DEC_REG,`INC_REG:
                begin
                        w <= 1'b1;
                        rrr <= ir[2:0];
                        state <= REGFETCHA;
                end
 
        `LEA: state <= EXECUTE;
 
        //-----------------------------------------------------------------
        // Immediate Loads
        //-----------------------------------------------------------------
 
        `MOV_I2AL,`MOV_I2DL,`MOV_I2CL,`MOV_I2BL,`MOV_I2AH,`MOV_I2DH,`MOV_I2CH,`MOV_I2BH:
                begin
                        `INITIATE_CODE_READ
                        state <= MOV_I2BYTREG;
                end
 
        `MOV_I2AX,`MOV_I2DX,`MOV_I2CX,`MOV_I2BX,`MOV_I2SP,`MOV_I2BP,`MOV_I2SI,`MOV_I2DI:
                begin
                        w <= 1'b1;
                        rrr <= ir[2:0];
                        if (ip==16'hFFFF) begin
                                int_num <= 8'h0d;
                                state <= INT2;
                        end
                        else
                                state <= FETCH_IMM16;
                end
 
        `XLAT:
                if (!cyc_o) begin
                        cyc_type <= `CT_RDMEM;
                        cyc_o <= 1'b1;
                        stb_o <= 1'b1;
                        adr_o <= {seg_reg,`SEG_SHIFT} + bx + al;
                end
                else if (ack_i) begin
                        cyc_type <= `CT_PASSIVE;
                        cyc_o <= 1'b0;
                        stb_o <= 1'b0;
                        res <= dat_i;
                        wrregs <= 1'b1;
                        w <= 1'b0;
                        rrr <= 3'd0;
                        state <= IFETCH;
                end
 
        //-----------------------------------------------------------------
        // Arithmetic Operations
        //-----------------------------------------------------------------
        `AAA,`AAS:
                begin
                        state <= IFETCH;
                        wrregs <= 1'b1;
                        w <= 1'b1;
                        rrr <= 3'd0;
                        res <= alu_o;
                        af <= (al[3:0]>4'h9 || af);
                        cf <= (al[3:0]>4'h9 || af);
                end
        `ADD_ALI8,`ADC_ALI8,`SUB_ALI8,`SBB_ALI8,`AND_ALI8,`OR_ALI8,`XOR_ALI8,`CMP_ALI8,`TEST_ALI8:
                begin
                        w <= 1'b0;
                        a <= {{8{al[7]}},al};
                        rrr <= 3'd0;
                        state <= FETCH_IMM8;
                end
        `ADD_AXI16,`ADC_AXI16,`SUB_AXI16,`SBB_AXI16,`AND_AXI16,`OR_AXI16,`XOR_AXI16,`CMP_AXI16,`TEST_AXI16:
                begin
                        w <= 1'b1;
                        a <= ax;
                        rrr <= 3'd0;
                        if (ip==16'hFFFF) begin
                                int_num <= 8'h0d;
                                state <= INT2;
                        end
                        else
                                state <= FETCH_IMM16;
                end
        `ALU_I2R8:
                begin
                        state <= FETCH_IMM8;
                        a <= rrro;
                end
        `ALU_I2R16:
                begin
                        state <= FETCH_IMM16;
                        a <= rrro;
                end
        `XCHG_AXR:
                begin
                        state <= IFETCH;
                        wrregs <= 1'b1;
                        w <= 1'b1;
                        rrr <= ir[2:0];
                        res <= ax;
                        case(ir[2:0])
                        3'd0:   ax <= ax;
                        3'd1:   ax <= cx;
                        3'd2:   ax <= dx;
                        3'd3:   ax <= bx;
                        3'd4:   ax <= sp;
                        3'd5:   ax <= bp;
                        3'd6:   ax <= si;
                        3'd7:   ax <= di;
                        endcase
                end
        `CBW: begin ax[15:8] <= {8{ax[7]}}; state <= IFETCH; end
        `CWD:
                begin
                        state <= IFETCH;
                        wrregs <= 1'b1;
                        w <= 1'b1;
                        rrr <= 3'd2;
                        res <= {16{ax[15]}};
                end
 
        //-----------------------------------------------------------------
        // String Operations
        //-----------------------------------------------------------------
        `LODSB: state <= LODS;
        `LODSW: state <= LODS;
        `STOSB: state <= STOS;
        `STOSW: state <= STOS;
        `MOVSB: state <= MOVS;
        `MOVSW: state <= MOVS;
        `CMPSB: state <= CMPSB;
        `CMPSW: state <= CMPSW;
        `SCASB: state <= SCASB;
        `SCASW: state <= SCASW;
 
        //-----------------------------------------------------------------
        // Stack Operations
        //-----------------------------------------------------------------
        `PUSH_REG: begin sp <= sp_dec; state <= PUSH; end
        `PUSH_DS: begin sp <= sp_dec; state <= PUSH; end
        `PUSH_ES: begin sp <= sp_dec; state <= PUSH; end
        `PUSH_SS: begin sp <= sp_dec; state <= PUSH; end
        `PUSH_CS: begin sp <= sp_dec; state <= PUSH; end
        `PUSHF: begin sp <= sp_dec; state <= PUSH; end
        `POP_REG: state <= POP;
        `POP_DS: state <= POP;
        `POP_ES: state <= POP;
        `POP_SS: state <= POP;
        `POPF: state <= POP;
 
        //-----------------------------------------------------------------
        // Flow controls
        //-----------------------------------------------------------------
        `NOP: state <= IFETCH;
        `HLT: if (pe_nmi | (irq_i & ie)) state <= IFETCH;
        `WAI: if (!busy_i) state <= IFETCH;
        `LOOP: begin cx <= cx_dec; state <= BRANCH1; end
        `LOOPZ: begin cx <= cx_dec; state <= BRANCH1; end
        `LOOPNZ: begin cx <= cx_dec; state <= BRANCH1; end
        `Jcc: state <= BRANCH1;
        `JCXZ: state <= BRANCH1;
        `JMPS: state <= BRANCH1;
        `JMPF: state <= FETCH_OFFSET;
        `CALL: begin sp <= sp_dec; state <= FETCH_DISP16; end
        `CALLF: begin sp <= sp_dec; state <= FETCH_OFFSET; end
        `RET: state <= RETPOP;          // data16 is zero
        `RETPOP: state <= FETCH_STK_ADJ1;
        `RETF: state <= RETFPOP;        // data16 is zero
        `RETFPOP: state <= FETCH_STK_ADJ1;
        `IRET: state <= IRET1;
        `INT: state <= INT;
        `INT3: begin int_num <= 8'd3; state <= INT2; end
        `INTO:
                if (vf) begin
                        int_num <= 8'd4;
                        state <= INT2;
                end
                else
                        state <= IFETCH;
 
        //-----------------------------------------------------------------
        // Flag register operations
        //-----------------------------------------------------------------
        `STI: begin ie <= 1'b1; state <= IFETCH; end
        `CLI: begin ie <= 1'b0; state <= IFETCH; end
        `STD: begin df <= 1'b1; state <= IFETCH; end
        `CLD: begin df <= 1'b0; state <= IFETCH; end
        `STC: begin cf <= 1'b1; state <= IFETCH; end
        `CLC: begin cf <= 1'b0; state <= IFETCH; end
        `CMC: begin cf <=  !cf; state <= IFETCH; end
        `LAHF:
                begin
                        ax[15] <= sf;
                        ax[14] <= zf;
                        ax[12] <= af;
                        ax[10] <= pf;
                        ax[8] <= cf;
                        state <= IFETCH;
                end
        `SAHF:
                begin
                        sf <= ah[7];
                        zf <= ah[6];
                        af <= ah[4];
                        pf <= ah[2];
                        cf <= ah[0];
                        state <= IFETCH;
                end
 
        //-----------------------------------------------------------------
        // IO instructions
        // - fetch port number, then vector
        //-----------------------------------------------------------------
        `INB: state <= INB;
        `INW: state <= INW;
        `OUTB: state <= OUTB;
        `OUTW: state <= OUTW;
        `INB_DX: begin ea <= {`SEG_SHIFT,dx}; state <= INB1; end
        `INW_DX: begin ea <= {`SEG_SHIFT,dx}; state <= INW1; end
        `OUTB_DX: begin ea <= {`SEG_SHIFT,dx}; state <= OUTB1; end
        `OUTW_DX: begin ea <= {`SEG_SHIFT,dx}; state <= OUTW1; end
        `INSB: state <= INSB;
        `OUTSB: state <= OUTSB;
        `OUTSW: state <= OUTSW;
 
        //-----------------------------------------------------------------
        // Control Prefix
        //-----------------------------------------------------------------
        `LOCK: begin lock_insn <= ir; state <= IFETCH; end
        `REPZ,`REPNZ,`CS,`DS,`ES,`SS: state <= IFETCH;
 
        //-----------------------------------------------------------------
        // disp16 instructions
        //-----------------------------------------------------------------
        `MOV_M2AL,`MOV_M2AX,`MOV_AL2M,`MOV_AX2M,`CALL,`JMP:
                begin
                        code_read();
                        state <= FETCH_DISP16_ACK;
                end
 
        default:
                begin
                if (v) shftamt <= cl[3:0];
                else shftamt <= 4'd1;
                //-----------------------------------------------------------------
                // MOD/RM instructions
                //-----------------------------------------------------------------
                $display("Fetching mod/rm, w=",w);
                if (ir==`MOV_R2S || ir==`MOV_S2R)
                        w <= 1'b1;
                if (ir==`LDS || ir==`LES)
                        w <= 1'b1;
                if (fetch_modrm) begin
                        code_read();
                        state <= EACALC;
                end
                else
                        state <= IFETCH;
                end
        endcase

Line No.	Rev	Author	Line
1	2	robfinch	`// ============================================================================`
2			`// DECODE`
3			`// - decode / dispatch instruction`
4			`//`
5			`//`
6			`// (C) 2009-2012 Robert Finch`
7			`// Stratford`
8			`// robfinch[remove]@opencores.org`
9			`//`
10			`//`
11			`// This source file is free software: you can redistribute it and/or modify`
12			`// it under the terms of the GNU Lesser General Public License as published`
13			`// by the Free Software Foundation, either version 3 of the License, or`
14			`// (at your option) any later version.`
15			`//`
16			`// This source file is distributed in the hope that it will be useful,`
17			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
18			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
19			`// GNU General Public License for more details.`
20			`//`
21			`// You should have received a copy of the GNU General Public License`
22			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
23			`//`
24			`//`
25			`// Verilog`
26			`//`
27			`// Decode / dispatch instruction`
28			`// ============================================================================`
29			`//`
30			`DECODE:`
31			`casex(ir)`
32			`MORE1: state <= XI_FETCH;
33			`MORE2: state <= XI_FETCH;
34			`EXTOP: state <= XI_FETCH;
35
36			`DEC_REG,`INC_REG:
37			`begin`
38			`w <= 1'b1;`
39			`rrr <= ir[2:0];`
40	3	robfinch	`state <= REGFETCHA;`
41	2	robfinch	`end`
42
43			`LEA: state <= EXECUTE;
44
45			`//-----------------------------------------------------------------`
46			`// Immediate Loads`
47			`//-----------------------------------------------------------------`
48
49			`MOV_I2AL,`MOV_I2DL,`MOV_I2CL,`MOV_I2BL,`MOV_I2AH,`MOV_I2DH,`MOV_I2CH,`MOV_I2BH:
50			`begin`
51			`INITIATE_CODE_READ
52			`state <= MOV_I2BYTREG;`
53			`end`
54
55			`MOV_I2AX,`MOV_I2DX,`MOV_I2CX,`MOV_I2BX,`MOV_I2SP,`MOV_I2BP,`MOV_I2SI,`MOV_I2DI:
56			`begin`
57			`w <= 1'b1;`
58			`rrr <= ir[2:0];`
59			`if (ip==16'hFFFF) begin`
60			`int_num <= 8'h0d;`
61			`state <= INT2;`
62			`end`
63			`else`
64			`state <= FETCH_IMM16;`
65			`end`
66
67			`XLAT:
68			`if (!cyc_o) begin`
69			cyc_type <= `CT_RDMEM;
70			`cyc_o <= 1'b1;`
71			`stb_o <= 1'b1;`
72			adr_o <= {seg_reg,`SEG_SHIFT} + bx + al;
73			`end`
74			`else if (ack_i) begin`
75			cyc_type <= `CT_PASSIVE;
76			`cyc_o <= 1'b0;`
77			`stb_o <= 1'b0;`
78			`res <= dat_i;`
79			`wrregs <= 1'b1;`
80			`w <= 1'b0;`
81			`rrr <= 3'd0;`
82			`state <= IFETCH;`
83			`end`
84
85			`//-----------------------------------------------------------------`
86			`// Arithmetic Operations`
87			`//-----------------------------------------------------------------`
88			`AAA,`AAS:
89			`begin`
90			`state <= IFETCH;`
91			`wrregs <= 1'b1;`
92			`w <= 1'b1;`
93			`rrr <= 3'd0;`
94			`res <= alu_o;`
95			`af <= (al[3:0]>4'h9 \|\| af);`
96			`cf <= (al[3:0]>4'h9 \|\| af);`
97			`end`
98	6	robfinch	`ADD_ALI8,`ADC_ALI8,`SUB_ALI8,`SBB_ALI8,`AND_ALI8,`OR_ALI8,`XOR_ALI8,`CMP_ALI8,`TEST_ALI8:
99	2	robfinch	`begin`
100			`w <= 1'b0;`
101			`a <= {{8{al[7]}},al};`
102			`rrr <= 3'd0;`
103			`state <= FETCH_IMM8;`
104			`end`
105	6	robfinch	`ADD_AXI16,`ADC_AXI16,`SUB_AXI16,`SBB_AXI16,`AND_AXI16,`OR_AXI16,`XOR_AXI16,`CMP_AXI16,`TEST_AXI16:
106	2	robfinch	`begin`
107			`w <= 1'b1;`
108			`a <= ax;`
109			`rrr <= 3'd0;`
110			`if (ip==16'hFFFF) begin`
111			`int_num <= 8'h0d;`
112			`state <= INT2;`
113			`end`
114			`else`
115			`state <= FETCH_IMM16;`
116			`end`
117			`ALU_I2R8:
118			`begin`
119			`state <= FETCH_IMM8;`
120			`a <= rrro;`
121			`end`
122			`ALU_I2R16:
123			`begin`
124			`state <= FETCH_IMM16;`
125			`a <= rrro;`
126			`end`
127			`XCHG_AXR:
128			`begin`
129			`state <= IFETCH;`
130			`wrregs <= 1'b1;`
131			`w <= 1'b1;`
132			`rrr <= ir[2:0];`
133			`res <= ax;`
134			`case(ir[2:0])`
135			`3'd0: ax <= ax;`
136			`3'd1: ax <= cx;`
137			`3'd2: ax <= dx;`
138			`3'd3: ax <= bx;`
139			`3'd4: ax <= sp;`
140			`3'd5: ax <= bp;`
141			`3'd6: ax <= si;`
142			`3'd7: ax <= di;`
143			`endcase`
144			`end`
145			`CBW: begin ax[15:8] <= {8{ax[7]}}; state <= IFETCH; end
146			`CWD:
147			`begin`
148			`state <= IFETCH;`
149			`wrregs <= 1'b1;`
150			`w <= 1'b1;`
151			`rrr <= 3'd2;`
152			`res <= {16{ax[15]}};`
153			`end`
154
155			`//-----------------------------------------------------------------`
156			`// String Operations`
157			`//-----------------------------------------------------------------`
158			`LODSB: state <= LODS;
159			`LODSW: state <= LODS;
160			`STOSB: state <= STOS;
161			`STOSW: state <= STOS;
162			`MOVSB: state <= MOVS;
163			`MOVSW: state <= MOVS;
164			`CMPSB: state <= CMPSB;
165			`CMPSW: state <= CMPSW;
166			`SCASB: state <= SCASB;
167			`SCASW: state <= SCASW;
168
169			`//-----------------------------------------------------------------`
170			`// Stack Operations`
171			`//-----------------------------------------------------------------`
172			`PUSH_REG: begin sp <= sp_dec; state <= PUSH; end
173			`PUSH_DS: begin sp <= sp_dec; state <= PUSH; end
174			`PUSH_ES: begin sp <= sp_dec; state <= PUSH; end
175			`PUSH_SS: begin sp <= sp_dec; state <= PUSH; end
176			`PUSH_CS: begin sp <= sp_dec; state <= PUSH; end
177			`PUSHF: begin sp <= sp_dec; state <= PUSH; end
178			`POP_REG: state <= POP;
179			`POP_DS: state <= POP;
180			`POP_ES: state <= POP;
181			`POP_SS: state <= POP;
182			`POPF: state <= POP;
183
184			`//-----------------------------------------------------------------`
185			`// Flow controls`
186			`//-----------------------------------------------------------------`
187			`NOP: state <= IFETCH;
188			`HLT: if (pe_nmi \| (irq_i & ie)) state <= IFETCH;
189			`WAI: if (!busy_i) state <= IFETCH;
190			`LOOP: begin cx <= cx_dec; state <= BRANCH1; end
191			`LOOPZ: begin cx <= cx_dec; state <= BRANCH1; end
192			`LOOPNZ: begin cx <= cx_dec; state <= BRANCH1; end
193			`Jcc: state <= BRANCH1;
194			`JCXZ: state <= BRANCH1;
195			`JMPS: state <= BRANCH1;
196			`JMPF: state <= FETCH_OFFSET;
197			`CALL: begin sp <= sp_dec; state <= FETCH_DISP16; end
198			`CALLF: begin sp <= sp_dec; state <= FETCH_OFFSET; end
199			`RET: state <= RETPOP; // data16 is zero
200			`RETPOP: state <= FETCH_STK_ADJ1;
201			`RETF: state <= RETFPOP; // data16 is zero
202			`RETFPOP: state <= FETCH_STK_ADJ1;
203			`IRET: state <= IRET1;
204			`INT: state <= INT;
205			`INT3: begin int_num <= 8'd3; state <= INT2; end
206			`INTO:
207			`if (vf) begin`
208			`int_num <= 8'd4;`
209			`state <= INT2;`
210			`end`
211			`else`
212			`state <= IFETCH;`
213
214			`//-----------------------------------------------------------------`
215			`// Flag register operations`
216			`//-----------------------------------------------------------------`
217			`STI: begin ie <= 1'b1; state <= IFETCH; end
218			`CLI: begin ie <= 1'b0; state <= IFETCH; end
219			`STD: begin df <= 1'b1; state <= IFETCH; end
220			`CLD: begin df <= 1'b0; state <= IFETCH; end
221			`STC: begin cf <= 1'b1; state <= IFETCH; end
222			`CLC: begin cf <= 1'b0; state <= IFETCH; end
223			`CMC: begin cf <= !cf; state <= IFETCH; end
224			`LAHF:
225			`begin`
226			`ax[15] <= sf;`
227			`ax[14] <= zf;`
228			`ax[12] <= af;`
229			`ax[10] <= pf;`
230			`ax[8] <= cf;`
231			`state <= IFETCH;`
232			`end`
233			`SAHF:
234			`begin`
235			`sf <= ah[7];`
236			`zf <= ah[6];`
237			`af <= ah[4];`
238			`pf <= ah[2];`
239			`cf <= ah[0];`
240			`state <= IFETCH;`
241			`end`
242
243			`//-----------------------------------------------------------------`
244			`// IO instructions`
245			`// - fetch port number, then vector`
246			`//-----------------------------------------------------------------`
247			`INB: state <= INB;
248			`INW: state <= INW;
249			`OUTB: state <= OUTB;
250			`OUTW: state <= OUTW;
251			`INB_DX: begin ea <= {`SEG_SHIFT,dx}; state <= INB1; end
252			`INW_DX: begin ea <= {`SEG_SHIFT,dx}; state <= INW1; end
253			`OUTB_DX: begin ea <= {`SEG_SHIFT,dx}; state <= OUTB1; end
254			`OUTW_DX: begin ea <= {`SEG_SHIFT,dx}; state <= OUTW1; end
255			`INSB: state <= INSB;
256			`OUTSB: state <= OUTSB;
257			`OUTSW: state <= OUTSW;
258
259			`//-----------------------------------------------------------------`
260			`// Control Prefix`
261			`//-----------------------------------------------------------------`
262			`LOCK: begin lock_insn <= ir; state <= IFETCH; end
263			`REPZ,`REPNZ,`CS,`DS,`ES,`SS: state <= IFETCH;
264
265			`//-----------------------------------------------------------------`
266			`// disp16 instructions`
267			`//-----------------------------------------------------------------`
268			`MOV_M2AL,`MOV_M2AX,`MOV_AL2M,`MOV_AX2M,`CALL,`JMP:
269			`begin`
270	8	robfinch	`code_read();`
271	2	robfinch	`state <= FETCH_DISP16_ACK;`
272			`end`
273
274			`default:`
275			`begin`
276	4	robfinch	`if (v) shftamt <= cl[3:0];`
277			`else shftamt <= 4'd1;`
278	2	robfinch	`//-----------------------------------------------------------------`
279			`// MOD/RM instructions`
280			`//-----------------------------------------------------------------`
281	6	robfinch	`$display("Fetching mod/rm, w=",w);`
282	2	robfinch	if (ir==`MOV_R2S \|\| ir==`MOV_S2R)
283			`w <= 1'b1;`
284			if (ir==`LDS \|\| ir==`LES)
285			`w <= 1'b1;`
286			`if (fetch_modrm) begin`
287	8	robfinch	`code_read();`
288	2	robfinch	`state <= EACALC;`
289			`end`
290			`else`
291			`state <= IFETCH;`
292			`end`
293			`endcase`

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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [DECODE.v] - Blame information for rev 8