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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [EACALC.v] - Blame information for rev 6

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// ============================================================================
//  EACALC
//  - calculation of effective address
//
//
//  (C) 2009-2012  Robert Finch, Stratford
//  robfinch[remove]@opencores.org
//
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
//
//  Verilog 
//
// - the effective address calculation may need to fetch an additional
//   eight or sixteen bit displacement value in order to calculate the
//   effective address.
// - the EA calc only needs to be done once as there is only ever a 
//   single memory operand address. Once the EA is calculated it is
//   used for both the fetch and the store when memory is the target.
// ============================================================================
//
EACALC:
        // Terminate an outstanding MODRM fetch cycle
        if (cyc_o) begin
                if (ack_i) begin
                        `TERMINATE_CODE_READ
                        mod   <= dat_i[7:6];
                        rrr   <= dat_i[5:3];
                        sreg3 <= dat_i[5:3];
                        TTT   <= dat_i[5:3];
                        rm    <= dat_i[2:0];
                        $display("Mod/RM=%b_%b_%b", dat_i[7:6],dat_i[5:3],dat_i[2:0]);
                end
        end
        else begin
 
                disp16 <= 16'h0000;
 
                case(mod)
 
                2'b00:
                        begin
                                state <= EACALC1;
                                // ToDo: error on stack state
                                case(rm)
                                3'd0:   offset <= bx + si;
                                3'd1:   offset <= bx + di;
                                3'd2:   offset <= bp + si;
                                3'd3:   offset <= bp + di;
                                3'd4:   offset <= si;
                                3'd5:   offset <= di;
                                3'd6:   begin
                                                state <= EACALC_DISP16;
                                                offset <= 16'h0000;
                                                end
                                3'd7:   offset <= bx;
                                endcase
                        end
 
                2'b01:
                        begin
                                state <= EACALC_DISP8;
                                case(rm)
                                3'd0:   offset <= bx + si;
                                3'd1:   offset <= bx + di;
                                3'd2:   offset <= bp + si;
                                3'd3:   offset <= bp + di;
                                3'd4:   offset <= si;
                                3'd5:   offset <= di;
                                3'd6:   offset <= bp;
                                3'd7:   offset <= bx;
                                endcase
                        end
 
                2'b10:
                        begin
                                state <= EACALC_DISP16;
                                case(rm)
                                3'd0:   offset <= bx + si;
                                3'd1:   offset <= bx + di;
                                3'd2:   offset <= bp + si;
                                3'd3:   offset <= bp + di;
                                3'd4:   offset <= si;
                                3'd5:   offset <= di;
                                3'd6:   offset <= bp;
                                3'd7:   offset <= bx;
                                endcase
                        end
 
                2'b11:
                        begin
                                state <= EXECUTE;
                                case(ir)
                                `MOV_I8M:
                                        begin
                                                rrr <= rm;
                                                if (rrr==3'd0) state <= FETCH_IMM8;
                                        end
                                `MOV_I16M:
                                        begin
                                                rrr <= rm;
                                                if (rrr==3'd0) state <= FETCH_IMM16;
                                        end
                                `MOV_S2R:
                                        begin
                                                a <= rfso;
                                                b <= rfso;
                                        end
                                `MOV_R2S:
                                        begin
                                                a <= rmo;
                                                b <= rmo;
                                        end
                                `POP_MEM:
                                        begin
                                                ir <= 8'h58|rm;
                                                state <= POP;
                                        end
                                `XCHG_MEM:
                                        begin
                                                wrregs <= 1'b1;
                                                res <= rmo;
                                                b <= rrro;
                                        end
                                // shifts and rotates
                                8'hD0,8'hD1,8'hD2,8'hD3:
                                        begin
                                                b <= rmo;
                                        end
                                8'hF6,8'hF7:
                                        b <= rmo;
                                default:
                                    begin
                                                if (d) begin
                                                        a <= rmo;
                                                        b <= rrro;
                                                end
                                                else begin
                                                        a <= rrro;
                                                        b <= rmo;
                                                end
                                        end
                                endcase
                                hasFetchedData <= 1'b1;
                        end
                endcase
        end
 
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Fetch 16 bit displacement
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
//
EACALC_DISP16:
        begin
                lock_o <= 1'b1;
                `INITIATE_CODE_READ
                state <= EACALC_DISP16_ACK;
        end
EACALC_DISP16_ACK:
        if (ack_i) begin
                `TERMINATE_CODE_READ
                disp16[7:0] <= dat_i;
                state <= EACALC_DISP16a;
        end
EACALC_DISP16a:
        begin
                `INITIATE_CODE_READ
                state <= EACALC_DISP16a_ACK;
        end
EACALC_DISP16a_ACK:
        if (ack_i) begin
                `TERMINATE_CODE_READ
                lock_o <= bus_locked;
                disp16[15:8] <= dat_i;
                state <= EACALC1;
        end
 
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Fetch 8 bit displacement
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
//
EACALC_DISP8:
        begin
                `INITIATE_CODE_READ
                state <= EACALC_DISP8_ACK;
        end
EACALC_DISP8_ACK:
        if (ack_i) begin
                `TERMINATE_CODE_READ
                disp16 <= {{8{dat_i[7]}},dat_i};
                state <= EACALC1;
        end
 
 
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Add the displacement into the effective address
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
//
EACALC1:
        begin
                casex(ir)
                `EXTOP:
                        casex(ir2)
                        8'h00:
                                begin
                                        case(rrr)
                                        3'b010: state <= FETCH_DESC;    // LLDT
                                        3'b011: state <= FETCH_DATA;    // LTR
                                        default: state <= FETCH_DATA;
                                        endcase
                                        if (w && (offsdisp==16'hFFFF)) begin
                                                int_num <= 8'h0d;
                                                state <= INT;
                                        end
                                end
                        8'h01:
                                begin
                                        case(rrr)
                                        3'b010: state <= FETCH_DESC;
                                        3'b011: state <= FETCH_DESC;
                                        default: state <= FETCH_DATA;
                                        endcase
                                        if (w && (offsdisp==16'hFFFF)) begin
                                                int_num <= 8'h0d;
                                                state <= INT;
                                        end
                                end
                        8'h03:
                                if (w && (offsdisp==16'hFFFF)) begin
                                        int_num <= 8'h0d;
                                        state <= INT;
                                end
                                else
                                        state <= FETCH_DATA;
                        default:
                                if (w && (offsdisp==16'hFFFF)) begin
                                        int_num <= 8'h0d;
                                        state <= INT;
                                end
                                else
                                        state <= FETCH_DATA;
                        endcase
                `MOV_I8M: state <= FETCH_IMM8;
                `MOV_I16M:
                        if (ip==16'hFFFF) begin
                                int_num <= 8'h0d;
                                state <= INT;
                        end
                        else
                                state <= FETCH_IMM16;
                `POP_MEM:
                        begin
                                state <= POP;
                        end
                `XCHG_MEM:
                        begin
//                              bus_locked <= 1'b1;
                                state <= FETCH_DATA;
                        end
                default:
                        begin
                                if (w && (offsdisp==16'hFFFF)) begin
                                        int_num <= 8'h0d;
                                        state <= INT;
                                end
                                else
                                        state <= FETCH_DATA;
                                if (ir==8'hff) begin
                                        case(rrr)
                                        3'b011: state <= CALLF; // CAll FAR indirect
                                        3'b101: state <= JUMP_VECTOR1;  // JMP FAR indirect
                                        3'b110: begin d <= 1'b0; state <= FETCH_DATA; end// for a push
                                        default: ;
                                        endcase
                                end
                        end
                endcase
//              ea <= ea + disp16;
                ea <= {seg_reg,`SEG_SHIFT} + offsdisp;  // offsdisp = offset + disp16
        end

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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [EACALC.v] - Blame information for rev 6

Line No.	Rev	Author	Line
1	2	robfinch	`// ============================================================================`
2			`// EACALC`
3			`// - calculation of effective address`
4			`//`
5			`//`
6			`// (C) 2009-2012 Robert Finch, Stratford`
7			`// robfinch[remove]@opencores.org`
8			`//`
9			`//`
10			`// This source file is free software: you can redistribute it and/or modify`
11			`// it under the terms of the GNU Lesser General Public License as published`
12			`// by the Free Software Foundation, either version 3 of the License, or`
13			`// (at your option) any later version.`
14			`//`
15			`// This source file is distributed in the hope that it will be useful,`
16			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
17			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
18			`// GNU General Public License for more details.`
19			`//`
20			`// You should have received a copy of the GNU General Public License`
21			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
22			`//`
23			`//`
24			`// Verilog`
25			`//`
26			`// - the effective address calculation may need to fetch an additional`
27			`// eight or sixteen bit displacement value in order to calculate the`
28			`// effective address.`
29			`// - the EA calc only needs to be done once as there is only ever a`
30			`// single memory operand address. Once the EA is calculated it is`
31			`// used for both the fetch and the store when memory is the target.`
32			`// ============================================================================`
33			`//`
34			`EACALC:`
35			`// Terminate an outstanding MODRM fetch cycle`
36			`if (cyc_o) begin`
37			`if (ack_i) begin`
38			`TERMINATE_CODE_READ
39			`mod <= dat_i[7:6];`
40			`rrr <= dat_i[5:3];`
41			`sreg3 <= dat_i[5:3];`
42			`TTT <= dat_i[5:3];`
43			`rm <= dat_i[2:0];`
44			`$display("Mod/RM=%b_%b_%b", dat_i[7:6],dat_i[5:3],dat_i[2:0]);`
45			`end`
46			`end`
47			`else begin`
48
49			`disp16 <= 16'h0000;`
50
51			`case(mod)`
52
53			`2'b00:`
54			`begin`
55			`state <= EACALC1;`
56			`// ToDo: error on stack state`
57			`case(rm)`
58			`3'd0: offset <= bx + si;`
59			`3'd1: offset <= bx + di;`
60			`3'd2: offset <= bp + si;`
61			`3'd3: offset <= bp + di;`
62			`3'd4: offset <= si;`
63			`3'd5: offset <= di;`
64			`3'd6: begin`
65			`state <= EACALC_DISP16;`
66			`offset <= 16'h0000;`
67			`end`
68			`3'd7: offset <= bx;`
69			`endcase`
70			`end`
71
72			`2'b01:`
73			`begin`
74			`state <= EACALC_DISP8;`
75			`case(rm)`
76			`3'd0: offset <= bx + si;`
77			`3'd1: offset <= bx + di;`
78			`3'd2: offset <= bp + si;`
79			`3'd3: offset <= bp + di;`
80			`3'd4: offset <= si;`
81			`3'd5: offset <= di;`
82			`3'd6: offset <= bp;`
83			`3'd7: offset <= bx;`
84			`endcase`
85			`end`
86
87			`2'b10:`
88			`begin`
89			`state <= EACALC_DISP16;`
90			`case(rm)`
91			`3'd0: offset <= bx + si;`
92			`3'd1: offset <= bx + di;`
93			`3'd2: offset <= bp + si;`
94			`3'd3: offset <= bp + di;`
95			`3'd4: offset <= si;`
96			`3'd5: offset <= di;`
97			`3'd6: offset <= bp;`
98			`3'd7: offset <= bx;`
99			`endcase`
100			`end`
101
102			`2'b11:`
103			`begin`
104			`state <= EXECUTE;`
105			`case(ir)`
106			`MOV_I8M:
107			`begin`
108			`rrr <= rm;`
109			`if (rrr==3'd0) state <= FETCH_IMM8;`
110			`end`
111			`MOV_I16M:
112			`begin`
113			`rrr <= rm;`
114			`if (rrr==3'd0) state <= FETCH_IMM16;`
115			`end`
116			`MOV_S2R:
117			`begin`
118			`a <= rfso;`
119			`b <= rfso;`
120			`end`
121			`MOV_R2S:
122			`begin`
123			`a <= rmo;`
124			`b <= rmo;`
125			`end`
126			`POP_MEM:
127			`begin`
128			`ir <= 8'h58\|rm;`
129			`state <= POP;`
130			`end`
131			`XCHG_MEM:
132			`begin`
133			`wrregs <= 1'b1;`
134			`res <= rmo;`
135			`b <= rrro;`
136			`end`
137	4	robfinch	`// shifts and rotates`
138			`8'hD0,8'hD1,8'hD2,8'hD3:`
139			`begin`
140			`b <= rmo;`
141			`end`
142	6	robfinch	`8'hF6,8'hF7:`
143			`b <= rmo;`
144	2	robfinch	`default:`
145			`begin`
146			`if (d) begin`
147			`a <= rmo;`
148			`b <= rrro;`
149			`end`
150			`else begin`
151			`a <= rrro;`
152			`b <= rmo;`
153			`end`
154			`end`
155			`endcase`
156			`hasFetchedData <= 1'b1;`
157			`end`
158			`endcase`
159			`end`
160
161			`//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
162			`// Fetch 16 bit displacement`
163			`//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
164			`//`
165			`EACALC_DISP16:`
166			`begin`
167			`lock_o <= 1'b1;`
168			`INITIATE_CODE_READ
169			`state <= EACALC_DISP16_ACK;`
170			`end`
171			`EACALC_DISP16_ACK:`
172			`if (ack_i) begin`
173			`TERMINATE_CODE_READ
174			`disp16[7:0] <= dat_i;`
175			`state <= EACALC_DISP16a;`
176			`end`
177			`EACALC_DISP16a:`
178			`begin`
179			`INITIATE_CODE_READ
180			`state <= EACALC_DISP16a_ACK;`
181			`end`
182			`EACALC_DISP16a_ACK:`
183			`if (ack_i) begin`
184			`TERMINATE_CODE_READ
185			`lock_o <= bus_locked;`
186			`disp16[15:8] <= dat_i;`
187			`state <= EACALC1;`
188			`end`
189
190			`//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
191			`// Fetch 8 bit displacement`
192			`//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
193			`//`
194			`EACALC_DISP8:`
195			`begin`
196			`INITIATE_CODE_READ
197			`state <= EACALC_DISP8_ACK;`
198			`end`
199			`EACALC_DISP8_ACK:`
200			`if (ack_i) begin`
201			`TERMINATE_CODE_READ
202			`disp16 <= {{8{dat_i[7]}},dat_i};`
203			`state <= EACALC1;`
204			`end`
205
206
207			`//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
208			`// Add the displacement into the effective address`
209			`//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
210			`//`
211			`EACALC1:`
212			`begin`
213			`casex(ir)`
214			`EXTOP:
215			`casex(ir2)`
216			`8'h00:`
217			`begin`
218			`case(rrr)`
219			`3'b010: state <= FETCH_DESC; // LLDT`
220			`3'b011: state <= FETCH_DATA; // LTR`
221			`default: state <= FETCH_DATA;`
222			`endcase`
223			`if (w && (offsdisp==16'hFFFF)) begin`
224			`int_num <= 8'h0d;`
225			`state <= INT;`
226			`end`
227			`end`
228			`8'h01:`
229			`begin`
230			`case(rrr)`
231			`3'b010: state <= FETCH_DESC;`
232			`3'b011: state <= FETCH_DESC;`
233			`default: state <= FETCH_DATA;`
234			`endcase`
235			`if (w && (offsdisp==16'hFFFF)) begin`
236			`int_num <= 8'h0d;`
237			`state <= INT;`
238			`end`
239			`end`
240			`8'h03:`
241			`if (w && (offsdisp==16'hFFFF)) begin`
242			`int_num <= 8'h0d;`
243			`state <= INT;`
244			`end`
245			`else`
246			`state <= FETCH_DATA;`
247			`default:`
248			`if (w && (offsdisp==16'hFFFF)) begin`
249			`int_num <= 8'h0d;`
250			`state <= INT;`
251			`end`
252			`else`
253			`state <= FETCH_DATA;`
254			`endcase`
255			`MOV_I8M: state <= FETCH_IMM8;
256			`MOV_I16M:
257			`if (ip==16'hFFFF) begin`
258			`int_num <= 8'h0d;`
259			`state <= INT;`
260			`end`
261			`else`
262			`state <= FETCH_IMM16;`
263			`POP_MEM:
264			`begin`
265			`state <= POP;`
266			`end`
267			`XCHG_MEM:
268			`begin`
269			`// bus_locked <= 1'b1;`
270			`state <= FETCH_DATA;`
271			`end`
272			`default:`
273			`begin`
274			`if (w && (offsdisp==16'hFFFF)) begin`
275			`int_num <= 8'h0d;`
276			`state <= INT;`
277			`end`
278			`else`
279			`state <= FETCH_DATA;`
280			`if (ir==8'hff) begin`
281			`case(rrr)`
282			`3'b011: state <= CALLF; // CAll FAR indirect`
283			`3'b101: state <= JUMP_VECTOR1; // JMP FAR indirect`
284			`3'b110: begin d <= 1'b0; state <= FETCH_DATA; end// for a push`
285			`default: ;`
286			`endcase`
287			`end`
288			`end`
289			`endcase`
290			`// ea <= ea + disp16;`
291			ea <= {seg_reg,`SEG_SHIFT} + offsdisp; // offsdisp = offset + disp16
292			`end`