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// ============================================================================
//  (C) 2009,2010,2012  Robert Finch
//  robfinch<remove>@opencores.org
//
//  EXECUTE
//  - execute instruction
//
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
//
//  Verilog 
//
// ============================================================================
//
EXECUTE:
        begin
                casex(ir)
 
                `EXTOP:
                        casex(ir2)
                        `LxDT: state <= FETCH_DESC;
                        endcase
 
                `DAA:
                        begin
                                state <= IFETCH;
                        end
 
                `ALU_I2R8,`ALU_I2R16,`ADD,`ADD_ALI8,`ADD_AXI16,`ADC,`ADC_ALI8,`ADC_AXI16:
                        begin
                                state <= IFETCH;
                                wrregs <= 1'b1;
                                res <= alu_o;
                                pf <= pres;
                                af <= carry   (1'b0,a[3],b[3],alu_o[3]);
                                cf <= carry   (1'b0,amsb,bmsb,resn);
                                vf <= overflow(1'b0,amsb,bmsb,resn);
                                sf <= resn;
                                zf <= resz;
                        end
 
                `AND,`OR,`XOR,`AND_ALI8,`OR_ALI8,`XOR_ALI8,`AND_AXI16,`OR_AXI16,`XOR_AXI16:
                        begin
                                state <= IFETCH;
                                wrregs <= 1'b1;
                                res <= alu_o;
                                pf <= pres;
                                cf <= 1'b0;
                                vf <= 1'b0;
                                sf <= resn;
                                zf <= resz;
                        end
 
                `TEST:
                        begin
                                state <= IFETCH;
                                res <= alu_o;
                                pf <= pres;
                                cf <= 1'b0;
                                vf <= 1'b0;
                                sf <= resn;
                                zf <= resz;
                        end
 
                `CMP,`CMP_ALI8,`CMP_AXI16:
                        begin
                                state <= IFETCH;
                                pf <= pres;
                                af <= carry   (1'b1,a[3],b[3],alu_o[3]);
                                cf <= carry   (1'b1,amsb,bmsb,resn);
                                vf <= overflow(1'b1,amsb,bmsb,resn);
                                sf <= resn;
                                zf <= resz;
                        end
 
                `SBB,`SUB,`SBB_ALI8,`SUB_ALI8,`SBB_AXI16,`SUB_AXI16:
                        begin
                                wrregs <= 1'b1;
                                state <= IFETCH;
                                res <= alu_o;
                                pf <= pres;
                                af <= carry   (1'b1,a[3],b[3],alu_o[3]);
                                cf <= carry   (1'b1,amsb,bmsb,resn);
                                vf <= overflow(1'b1,amsb,bmsb,resn);
                                sf <= resn;
                                zf <= resz;
                        end
 
                8'hF6,8'hF7:
                        begin
                                wrregs <= 1'b1;
                                state <= IFETCH;
                                case(rrr)
                                3'd2: res <= ~b;        // NOT
                                3'd3: res <= -b;        // NEG
                                endcase
                        end
                `INC_REG:
                        begin
                                state <= IFETCH;
                                wrregs <= 1'b1;
                                w <= 1'b1;
                                res <= alu_o;
                                pf <= pres;
                                af <= carry   (1'b0,a[3],b[3],alu_o[3]);
                                vf <= overflow(1'b0,a[15],b[15],resnw);
                                sf <= resnw;
                                zf <= reszw;
                        end
                `DEC_REG:
                        begin
                                state <= IFETCH;
                                wrregs <= 1'b1;
                                w <= 1'b1;
                                res <= alu_o;
                                pf <= pres;
                                af <= carry   (1'b1,a[3],b[3],alu_o[3]);
                                vf <= overflow(1'b1,a[15],b[15],resnw);
                                sf <= resnw;
                                zf <= reszw;
                        end
                `IMUL:
                        begin
                                state <= IFETCH;
                                wrregs <= 1'b1;
                                w <= 1'b1;
                                rrr <= 3'd0;
                                res <= alu_o;
                                if (w) begin
                                        cf <= wp[31:16]!={16{resnw}};
                                        vf <= wp[31:16]!={16{resnw}};
                                        dx <= wp[31:16];
                                end
                                else begin
                                        cf <= ah!={8{resnb}};
                                        vf <= ah!={8{resnb}};
                                end
                        end
 
 
                //-----------------------------------------------------------------
                // Memory Operations
                //-----------------------------------------------------------------
 
                // registers not allowed on LEA
                // invalid opcode
                //
                `LEA:
                        begin
                                w <= 1'b1;
                                res <= ea;
                                if (mod==2'b11) begin
                                        int_num <= 8'h06;
                                        state <= INT;
                                end
                                else begin
                                        state <= IFETCH;
                                        wrregs <= 1'b1;
                                end
                        end
                `LDS:
                        begin
                                wrsregs <= 1'b1;
                                res <= alu_o;
                                rrr <= 3'd3;
                                state <= IFETCH;
                        end
                `LES:
                        begin
                                wrsregs <= 1'b1;
                                res <= alu_o;
                                rrr <= 3'd0;
                                state <= IFETCH;
                        end
 
                `MOV_RR8,`MOV_RR16,
                `MOV_MR,
                `MOV_M2AL,`MOV_M2AX,
                `MOV_I2AL,`MOV_I2DL,`MOV_I2CL,`MOV_I2BL,`MOV_I2AH,`MOV_I2DH,`MOV_I2CH,`MOV_I2BH,
                `MOV_I2AX,`MOV_I2DX,`MOV_I2CX,`MOV_I2BX,`MOV_I2SP,`MOV_I2BP,`MOV_I2SI,`MOV_I2DI:
                        begin
                                state <= IFETCH;
                                wrregs <= 1'b1;
                                res <= alu_o;
                        end
                `XCHG_MEM:
                        begin
                                wrregs <= 1'b1;
                                if (mod==2'b11) rrr <= rm;
                                res <= alu_o;
                                b <= rrro;
                                state <= mod==2'b11 ? IFETCH : XCHG_MEM;
                        end
                `MOV_I8M,`MOV_I16M:
                        begin
                                res <= alu_o;
                                state <= rrr==3'd0 ? STORE_DATA : INVALID_OPCODE;
                        end
 
                `MOV_S2R:
                        begin
                                w <= 1'b1;
                                rrr <= rm;
                                res <= b;
                                if (mod==2'b11) begin
                                        state <= IFETCH;
                                        wrregs <= 1'b1;
                                end
                                else
                                        state <= STORE_DATA;
                        end
                `MOV_R2S:
                        begin
                                wrsregs <= 1'b1;
                                res <= alu_o;
                                state <= IFETCH;
                        end
 
                `LODSB:
                        begin
                                state <= IFETCH;
                                wrregs <= 1'b1;
                                w <= 1'b0;
                                rrr <= 3'd0;
                                res <= a[7:0];
                                if ( df) si <= si_dec;
                                if (!df) si <= si_inc;
                        end
                `LODSW:
                        begin
                                state <= IFETCH;
                                wrregs <= 1'b1;
                                w <= 1'b1;
                                rrr <= 3'd0;
                                res <= a;
                                if ( df) si <= si - 16'd2;
                                if (!df) si <= si + 16'd2;
                        end
 
                8'hD0,8'hD1,8'hD2,8'hD3,8'hC0,8'hC1:
                        begin
                                state <= IFETCH;
                                wrregs <= 1'b1;
                                rrr <= rm;
                                if (w)
                                        case(rrr)
                                        3'b000: // ROL
                                                begin
                                                        res <= shlo[15:0]|shlo[31:16];
                                                        cf <= bmsb;
                                                        vf <= bmsb^b[14];
                                                end
                                        3'b001: // ROR
                                                begin
                                                        res <= shruo[15:0]|shruo[31:16];
                                                        cf <= b[0];
                                                        vf <= cf^b[15];
                                                end
                                        3'b010: // RCL
                                                begin
                                                        res <= shlco[16:1]|shlco[32:17];
                                                        cf <= b[15];
                                                        vf <= b[15]^b[14];
                                                end
                                        3'b011: // RCR
                                                begin
                                                        res <= shrcuo[15:0]|shrcuo[31:16];
                                                        cf <= b[0];
                                                        vf <= cf^b[15];
                                                end
                                        3'b100: // SHL
                                                begin
                                                        $display("SHL:%h,%h,%d",shlo[15:0],b,shftamt);
                                                        res <= shlo[15:0];
                                                        cf <= shlo[16];
                                                        vf <= b[15]^b[14];
                                                end
                                        3'b101: // SHR
                                                begin
                                                        $display("SHR:%h,%h,%d",shruo[31:16],b,shftamt);
                                                        res <= shruo[31:16];
                                                        cf <= shruo[15];
                                                        vf <= b[15];
                                                end
                                        3'b111: // SAR
                                                begin
                                                        res <= shro;
                                                        cf <= b[0];
                                                        vf <= 1'b0;
                                                end
                                        endcase
                                else
                                        case(rrr)
                                        3'b000: // ROL
                                                begin
                                                        res <= shlo8[7:0]|shlo8[15:8];
                                                        cf <= b[7];
                                                        vf <= b[7]^b[6];
                                                end
                                        3'b001: // ROR
                                                begin
                                                        res <= shruo8[15:8]|shruo8[7:0];
                                                        cf <= b[0];
                                                        vf <= cf^b[7];
                                                end
                                        3'b010: // RCL
                                                begin
                                                        res <= shlco8[8:1]|shlco8[16:9];
                                                        cf <= b[7];
                                                        vf <= b[7]^b[6];
                                                end
                                        3'b011: // RCR
                                                begin
                                                        res <= shrcuo8[15:8]|shrcuo8[7:0];
                                                        cf <= b[0];
                                                        vf <= cf^b[7];
                                                end
                                        3'b100: // SHL
                                                begin
                                                        res <= shlo8[7:0];
                                                        cf <= shlo8[8];
                                                        vf <= b[7]^b[6];
                                                end
                                        3'b101: // SHR
                                                begin
                                                        res <= shruo8[15:8];
                                                        cf <= shruo8[7];
                                                        vf <= b[7];
                                                end
                                        3'b111: // SAR
                                                begin
                                                        res <= shro8;
                                                        cf <= b[0];
                                                        vf <= 1'b0;
                                                end
                                        endcase
                        end
 
                //-----------------------------------------------------------------
                //-----------------------------------------------------------------
                `GRPFF:
                        begin
                                case(rrr)
                                3'b000:         // INC
                                        begin
                                                state <= IFETCH;
                                                wrregs <= 1'b1;
                                                af <= carry   (1'b0,a[3],b[3],alu_o[3]);
                                                vf <= overflow(1'b0,a[15],b[15],alu_o[15]);
                                                w <= 1'b1;
                                                res <= alu_o;
                                                rrr <= rm;
                                                pf <= pres;
                                                sf <= resnw;
                                                zf <= reszw;
                                        end
                                3'b001:         // DEC
                                        begin
                                                state <= IFETCH;
                                                wrregs <= 1'b1;
                                                af <= carry   (1'b1,a[3],b[3],alu_o[3]);
                                                vf <= overflow(1'b1,a[15],b[15],alu_o[15]);
                                                w <= 1'b1;
                                                res <= alu_o;
                                                rrr <= rm;
                                                pf <= pres;
                                                sf <= resnw;
                                                zf <= reszw;
                                        end
                                3'b010: begin sp <= sp_dec; state <= CALL_IN; end
                                // These two should not be reachable here, as they would
                                // be trapped by the EACALC.
                                3'b011: state <= CALL_FIN;      // CALL FAR indirect
                                3'b101: // JMP FAR indirect
                                        begin
                                                ip <= offset;
                                                cs <= selector;
                                                state <= IFETCH;
                                        end
                                3'b110: begin sp <= sp_dec; state <= PUSH; end
                                default:
                                        begin
                                                af <= carry   (1'b0,a[3],b[3],alu_o[3]);
                                                vf <= overflow(1'b0,a[15],b[15],alu_o[15]);
                                        end
                                endcase
                        end
 
                //-----------------------------------------------------------------
                //-----------------------------------------------------------------
                default:
                        state <= IFETCH;
                endcase
        end
 

Line No.	Rev	Author	Line
1	2	robfinch	`// ============================================================================`
2			`// (C) 2009,2010,2012 Robert Finch`
3			`// robfinch<remove>@opencores.org`
4			`//`
5			`// EXECUTE`
6			`// - execute instruction`
7			`//`
8			`//`
9			`// This source file is free software: you can redistribute it and/or modify`
10			`// it under the terms of the GNU Lesser General Public License as published`
11			`// by the Free Software Foundation, either version 3 of the License, or`
12			`// (at your option) any later version.`
13			`//`
14			`// This source file is distributed in the hope that it will be useful,`
15			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
16			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
17			`// GNU General Public License for more details.`
18			`//`
19			`// You should have received a copy of the GNU General Public License`
20			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
21			`//`
22			`//`
23			`// Verilog`
24			`//`
25			`// ============================================================================`
26			`//`
27			`EXECUTE:`
28			`begin`
29			`casex(ir)`
30
31			`EXTOP:
32			`casex(ir2)`
33			`LxDT: state <= FETCH_DESC;
34			`endcase`
35
36			`DAA:
37			`begin`
38			`state <= IFETCH;`
39			`end`
40
41			`ALU_I2R8,`ALU_I2R16,`ADD,`ADD_ALI8,`ADD_AXI16,`ADC,`ADC_ALI8,`ADC_AXI16:
42			`begin`
43			`state <= IFETCH;`
44			`wrregs <= 1'b1;`
45			`res <= alu_o;`
46			`pf <= pres;`
47			`af <= carry (1'b0,a[3],b[3],alu_o[3]);`
48			`cf <= carry (1'b0,amsb,bmsb,resn);`
49			`vf <= overflow(1'b0,amsb,bmsb,resn);`
50			`sf <= resn;`
51			`zf <= resz;`
52			`end`
53
54			`AND,`OR,`XOR,`AND_ALI8,`OR_ALI8,`XOR_ALI8,`AND_AXI16,`OR_AXI16,`XOR_AXI16:
55			`begin`
56			`state <= IFETCH;`
57			`wrregs <= 1'b1;`
58			`res <= alu_o;`
59			`pf <= pres;`
60			`cf <= 1'b0;`
61			`vf <= 1'b0;`
62			`sf <= resn;`
63			`zf <= resz;`
64			`end`
65
66			`TEST:
67			`begin`
68			`state <= IFETCH;`
69			`res <= alu_o;`
70			`pf <= pres;`
71			`cf <= 1'b0;`
72			`vf <= 1'b0;`
73			`sf <= resn;`
74			`zf <= resz;`
75			`end`
76
77			`CMP,`CMP_ALI8,`CMP_AXI16:
78			`begin`
79			`state <= IFETCH;`
80			`pf <= pres;`
81			`af <= carry (1'b1,a[3],b[3],alu_o[3]);`
82			`cf <= carry (1'b1,amsb,bmsb,resn);`
83			`vf <= overflow(1'b1,amsb,bmsb,resn);`
84			`sf <= resn;`
85			`zf <= resz;`
86			`end`
87
88			`SBB,`SUB,`SBB_ALI8,`SUB_ALI8,`SBB_AXI16,`SUB_AXI16:
89			`begin`
90			`wrregs <= 1'b1;`
91			`state <= IFETCH;`
92			`res <= alu_o;`
93			`pf <= pres;`
94			`af <= carry (1'b1,a[3],b[3],alu_o[3]);`
95			`cf <= carry (1'b1,amsb,bmsb,resn);`
96			`vf <= overflow(1'b1,amsb,bmsb,resn);`
97			`sf <= resn;`
98			`zf <= resz;`
99			`end`
100
101			`8'hF6,8'hF7:`
102			`begin`
103			`wrregs <= 1'b1;`
104			`state <= IFETCH;`
105			`case(rrr)`
106			`3'd2: res <= ~b; // NOT`
107			`3'd3: res <= -b; // NEG`
108			`endcase`
109			`end`
110			`INC_REG:
111			`begin`
112			`state <= IFETCH;`
113			`wrregs <= 1'b1;`
114			`w <= 1'b1;`
115			`res <= alu_o;`
116			`pf <= pres;`
117			`af <= carry (1'b0,a[3],b[3],alu_o[3]);`
118			`vf <= overflow(1'b0,a[15],b[15],resnw);`
119			`sf <= resnw;`
120			`zf <= reszw;`
121			`end`
122			`DEC_REG:
123			`begin`
124			`state <= IFETCH;`
125			`wrregs <= 1'b1;`
126			`w <= 1'b1;`
127			`res <= alu_o;`
128			`pf <= pres;`
129			`af <= carry (1'b1,a[3],b[3],alu_o[3]);`
130			`vf <= overflow(1'b1,a[15],b[15],resnw);`
131			`sf <= resnw;`
132			`zf <= reszw;`
133			`end`
134			`IMUL:
135			`begin`
136			`state <= IFETCH;`
137			`wrregs <= 1'b1;`
138			`w <= 1'b1;`
139			`rrr <= 3'd0;`
140			`res <= alu_o;`
141			`if (w) begin`
142			`cf <= wp[31:16]!={16{resnw}};`
143			`vf <= wp[31:16]!={16{resnw}};`
144			`dx <= wp[31:16];`
145			`end`
146			`else begin`
147			`cf <= ah!={8{resnb}};`
148			`vf <= ah!={8{resnb}};`
149			`end`
150			`end`
151
152
153			`//-----------------------------------------------------------------`
154			`// Memory Operations`
155			`//-----------------------------------------------------------------`
156
157			`// registers not allowed on LEA`
158			`// invalid opcode`
159			`//`
160			`LEA:
161			`begin`
162			`w <= 1'b1;`
163			`res <= ea;`
164			`if (mod==2'b11) begin`
165			`int_num <= 8'h06;`
166			`state <= INT;`
167			`end`
168			`else begin`
169			`state <= IFETCH;`
170			`wrregs <= 1'b1;`
171			`end`
172			`end`
173			`LDS:
174			`begin`
175			`wrsregs <= 1'b1;`
176			`res <= alu_o;`
177			`rrr <= 3'd3;`
178			`state <= IFETCH;`
179			`end`
180			`LES:
181			`begin`
182			`wrsregs <= 1'b1;`
183			`res <= alu_o;`
184			`rrr <= 3'd0;`
185			`state <= IFETCH;`
186			`end`
187
188			`MOV_RR8,`MOV_RR16,
189			`MOV_MR,
190			`MOV_M2AL,`MOV_M2AX,
191			`MOV_I2AL,`MOV_I2DL,`MOV_I2CL,`MOV_I2BL,`MOV_I2AH,`MOV_I2DH,`MOV_I2CH,`MOV_I2BH,
192			`MOV_I2AX,`MOV_I2DX,`MOV_I2CX,`MOV_I2BX,`MOV_I2SP,`MOV_I2BP,`MOV_I2SI,`MOV_I2DI:
193			`begin`
194			`state <= IFETCH;`
195			`wrregs <= 1'b1;`
196			`res <= alu_o;`
197			`end`
198			`XCHG_MEM:
199			`begin`
200			`wrregs <= 1'b1;`
201			`if (mod==2'b11) rrr <= rm;`
202			`res <= alu_o;`
203			`b <= rrro;`
204			`state <= mod==2'b11 ? IFETCH : XCHG_MEM;`
205			`end`
206			`MOV_I8M,`MOV_I16M:
207			`begin`
208			`res <= alu_o;`
209			`state <= rrr==3'd0 ? STORE_DATA : INVALID_OPCODE;`
210			`end`
211
212			`MOV_S2R:
213			`begin`
214			`w <= 1'b1;`
215			`rrr <= rm;`
216			`res <= b;`
217			`if (mod==2'b11) begin`
218			`state <= IFETCH;`
219			`wrregs <= 1'b1;`
220			`end`
221			`else`
222			`state <= STORE_DATA;`
223			`end`
224			`MOV_R2S:
225			`begin`
226			`wrsregs <= 1'b1;`
227			`res <= alu_o;`
228			`state <= IFETCH;`
229			`end`
230
231			`LODSB:
232			`begin`
233			`state <= IFETCH;`
234			`wrregs <= 1'b1;`
235			`w <= 1'b0;`
236			`rrr <= 3'd0;`
237			`res <= a[7:0];`
238			`if ( df) si <= si_dec;`
239			`if (!df) si <= si_inc;`
240			`end`
241			`LODSW:
242			`begin`
243			`state <= IFETCH;`
244			`wrregs <= 1'b1;`
245			`w <= 1'b1;`
246			`rrr <= 3'd0;`
247			`res <= a;`
248			`if ( df) si <= si - 16'd2;`
249			`if (!df) si <= si + 16'd2;`
250			`end`
251
252			`8'hD0,8'hD1,8'hD2,8'hD3,8'hC0,8'hC1:`
253			`begin`
254			`state <= IFETCH;`
255			`wrregs <= 1'b1;`
256	5	robfinch	`rrr <= rm;`
257	2	robfinch	`if (w)`
258			`case(rrr)`
259			`3'b000: // ROL`
260			`begin`
261	4	robfinch	`res <= shlo[15:0]\|shlo[31:16];`
262	2	robfinch	`cf <= bmsb;`
263			`vf <= bmsb^b[14];`
264			`end`
265			`3'b001: // ROR`
266			`begin`
267	4	robfinch	`res <= shruo[15:0]\|shruo[31:16];`
268	2	robfinch	`cf <= b[0];`
269			`vf <= cf^b[15];`
270			`end`
271			`3'b010: // RCL`
272			`begin`
273	4	robfinch	`res <= shlco[16:1]\|shlco[32:17];`
274	2	robfinch	`cf <= b[15];`
275			`vf <= b[15]^b[14];`
276			`end`
277			`3'b011: // RCR`
278			`begin`
279	4	robfinch	`res <= shrcuo[15:0]\|shrcuo[31:16];`
280	2	robfinch	`cf <= b[0];`
281			`vf <= cf^b[15];`
282			`end`
283			`3'b100: // SHL`
284			`begin`
285	5	robfinch	`$display("SHL:%h,%h,%d",shlo[15:0],b,shftamt);`
286	4	robfinch	`res <= shlo[15:0];`
287			`cf <= shlo[16];`
288	2	robfinch	`vf <= b[15]^b[14];`
289			`end`
290			`3'b101: // SHR`
291			`begin`
292	5	robfinch	`$display("SHR:%h,%h,%d",shruo[31:16],b,shftamt);`
293	4	robfinch	`res <= shruo[31:16];`
294			`cf <= shruo[15];`
295	2	robfinch	`vf <= b[15];`
296			`end`
297			`3'b111: // SAR`
298			`begin`
299	4	robfinch	`res <= shro;`
300	2	robfinch	`cf <= b[0];`
301			`vf <= 1'b0;`
302			`end`
303			`endcase`
304			`else`
305			`case(rrr)`
306			`3'b000: // ROL`
307			`begin`
308	4	robfinch	`res <= shlo8[7:0]\|shlo8[15:8];`
309	2	robfinch	`cf <= b[7];`
310			`vf <= b[7]^b[6];`
311			`end`
312			`3'b001: // ROR`
313			`begin`
314	4	robfinch	`res <= shruo8[15:8]\|shruo8[7:0];`
315	2	robfinch	`cf <= b[0];`
316			`vf <= cf^b[7];`
317			`end`
318			`3'b010: // RCL`
319			`begin`
320	4	robfinch	`res <= shlco8[8:1]\|shlco8[16:9];`
321	2	robfinch	`cf <= b[7];`
322			`vf <= b[7]^b[6];`
323			`end`
324			`3'b011: // RCR`
325			`begin`
326	4	robfinch	`res <= shrcuo8[15:8]\|shrcuo8[7:0];`
327	2	robfinch	`cf <= b[0];`
328			`vf <= cf^b[7];`
329			`end`
330			`3'b100: // SHL`
331			`begin`
332	4	robfinch	`res <= shlo8[7:0];`
333			`cf <= shlo8[8];`
334	2	robfinch	`vf <= b[7]^b[6];`
335			`end`
336			`3'b101: // SHR`
337			`begin`
338	4	robfinch	`res <= shruo8[15:8];`
339			`cf <= shruo8[7];`
340	2	robfinch	`vf <= b[7];`
341			`end`
342			`3'b111: // SAR`
343			`begin`
344	4	robfinch	`res <= shro8;`
345	2	robfinch	`cf <= b[0];`
346			`vf <= 1'b0;`
347			`end`
348			`endcase`
349			`end`
350
351			`//-----------------------------------------------------------------`
352			`//-----------------------------------------------------------------`
353			`GRPFF:
354			`begin`
355			`case(rrr)`
356			`3'b000: // INC`
357			`begin`
358			`state <= IFETCH;`
359			`wrregs <= 1'b1;`
360			`af <= carry (1'b0,a[3],b[3],alu_o[3]);`
361			`vf <= overflow(1'b0,a[15],b[15],alu_o[15]);`
362			`w <= 1'b1;`
363			`res <= alu_o;`
364			`rrr <= rm;`
365			`pf <= pres;`
366			`sf <= resnw;`
367			`zf <= reszw;`
368			`end`
369			`3'b001: // DEC`
370			`begin`
371			`state <= IFETCH;`
372			`wrregs <= 1'b1;`
373			`af <= carry (1'b1,a[3],b[3],alu_o[3]);`
374			`vf <= overflow(1'b1,a[15],b[15],alu_o[15]);`
375			`w <= 1'b1;`
376			`res <= alu_o;`
377			`rrr <= rm;`
378			`pf <= pres;`
379			`sf <= resnw;`
380			`zf <= reszw;`
381			`end`
382			`3'b010: begin sp <= sp_dec; state <= CALL_IN; end`
383			`// These two should not be reachable here, as they would`
384			`// be trapped by the EACALC.`
385			`3'b011: state <= CALL_FIN; // CALL FAR indirect`
386			`3'b101: // JMP FAR indirect`
387			`begin`
388			`ip <= offset;`
389			`cs <= selector;`
390			`state <= IFETCH;`
391			`end`
392			`3'b110: begin sp <= sp_dec; state <= PUSH; end`
393			`default:`
394			`begin`
395			`af <= carry (1'b0,a[3],b[3],alu_o[3]);`
396			`vf <= overflow(1'b0,a[15],b[15],alu_o[15]);`
397			`end`
398			`endcase`
399			`end`
400
401			`//-----------------------------------------------------------------`
402			`//-----------------------------------------------------------------`
403			`default:`
404			`state <= IFETCH;`
405			`endcase`
406			`end`
407

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