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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [FETCH_DATA.v] - Blame information for rev 2

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//=============================================================================
//  (C) 2009-2012 Robert Finch, Stratford
//  robfinch<remove>@opencores.org
//
//  FETCH_DATA
//  Fetch data from memory.
//
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
//
//=============================================================================
//
FETCH_DATA:
        if (!cyc_o) begin
                cyc_type <= `CT_RDMEM;
                lock_o <= bus_locked | w;
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o  <= 1'b0;
                adr_o <= ea;
        end
        else if (ack_i) begin
                cyc_type <= `CT_PASSIVE;
                cyc_o <= w;
                stb_o <= 1'b0;
                if (d) begin
                        a <= rrro;
                        b[ 7:0] <= dat_i;
                        b[15:8] <= {8{dat_i[7]}};
                end
                else begin
                        b <= rrro;
                        a[ 7:0] <= dat_i;
                        a[15:8] <= {8{dat_i[7]}};
                end
                if (w)
                        state <= FETCH_DATA1;
                else begin
                        case(ir)
                        8'h80:  state <= FETCH_IMM8;
                        8'h81:  state <= FETCH_IMM16;
                        8'h83:  state <= FETCH_IMM8;
                        8'hC0:  state <= FETCH_IMM8;
                        8'hC1:  state <= FETCH_IMM8;
                        8'hC6:  state <= FETCH_IMM8;
                        8'hC7:  state <= FETCH_IMM16;
                        8'hF6:  state <= FETCH_IMM8;
                        8'hF7:  state <= FETCH_IMM16;
                        default: state <= EXECUTE;
                        endcase
                        hasFetchedData <= 1'b1;
                end
        end
FETCH_DATA1:
        if (!stb_o) begin
                cyc_type <= `CT_RDMEM;
                lock_o <= bus_locked | w;
                stb_o <= 1'b1;
                adr_o <= ea_inc;
        end
        else if (ack_i) begin
                cyc_type <= `CT_PASSIVE;
                lock_o <= bus_locked;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                if (d)
                        b[15:8] <= dat_i;
                else
                        a[15:8] <= dat_i;
                case(ir)
                8'h80:  state <= FETCH_IMM8;
                8'h81:  state <= FETCH_IMM16;
                8'h83:  state <= FETCH_IMM8;
                8'hC0:  state <= FETCH_IMM8;
                8'hC1:  state <= FETCH_IMM8;
                8'hC6:  state <= FETCH_IMM8;
                8'hC7:  state <= FETCH_IMM16;
                8'hF6:  state <= FETCH_IMM8;
                8'hF7:  state <= FETCH_IMM16;
                default: state <= EXECUTE;
                endcase
                hasFetchedData <= 1'b1;
        end

Line No.	Rev	Author	Line
1	2	robfinch	`//=============================================================================`
2			`// (C) 2009-2012 Robert Finch, Stratford`
3			`// robfinch<remove>@opencores.org`
4			`//`
5			`// FETCH_DATA`
6			`// Fetch data from memory.`
7			`//`
8			`//`
9			`// This source file is free software: you can redistribute it and/or modify`
10			`// it under the terms of the GNU Lesser General Public License as published`
11			`// by the Free Software Foundation, either version 3 of the License, or`
12			`// (at your option) any later version.`
13			`//`
14			`// This source file is distributed in the hope that it will be useful,`
15			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
16			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
17			`// GNU General Public License for more details.`
18			`//`
19			`// You should have received a copy of the GNU General Public License`
20			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
21			`//`
22			`//`
23			`//=============================================================================`
24			`//`
25			`FETCH_DATA:`
26			`if (!cyc_o) begin`
27			cyc_type <= `CT_RDMEM;
28			`lock_o <= bus_locked \| w;`
29			`cyc_o <= 1'b1;`
30			`stb_o <= 1'b1;`
31			`we_o <= 1'b0;`
32			`adr_o <= ea;`
33			`end`
34			`else if (ack_i) begin`
35			cyc_type <= `CT_PASSIVE;
36			`cyc_o <= w;`
37			`stb_o <= 1'b0;`
38			`if (d) begin`
39			`a <= rrro;`
40			`b[ 7:0] <= dat_i;`
41			`b[15:8] <= {8{dat_i[7]}};`
42			`end`
43			`else begin`
44			`b <= rrro;`
45			`a[ 7:0] <= dat_i;`
46			`a[15:8] <= {8{dat_i[7]}};`
47			`end`
48			`if (w)`
49			`state <= FETCH_DATA1;`
50			`else begin`
51			`case(ir)`
52			`8'h80: state <= FETCH_IMM8;`
53			`8'h81: state <= FETCH_IMM16;`
54			`8'h83: state <= FETCH_IMM8;`
55			`8'hC0: state <= FETCH_IMM8;`
56			`8'hC1: state <= FETCH_IMM8;`
57			`8'hC6: state <= FETCH_IMM8;`
58			`8'hC7: state <= FETCH_IMM16;`
59			`8'hF6: state <= FETCH_IMM8;`
60			`8'hF7: state <= FETCH_IMM16;`
61			`default: state <= EXECUTE;`
62			`endcase`
63			`hasFetchedData <= 1'b1;`
64			`end`
65			`end`
66			`FETCH_DATA1:`
67			`if (!stb_o) begin`
68			cyc_type <= `CT_RDMEM;
69			`lock_o <= bus_locked \| w;`
70			`stb_o <= 1'b1;`
71			`adr_o <= ea_inc;`
72			`end`
73			`else if (ack_i) begin`
74			cyc_type <= `CT_PASSIVE;
75			`lock_o <= bus_locked;`
76			`cyc_o <= 1'b0;`
77			`stb_o <= 1'b0;`
78			`if (d)`
79			`b[15:8] <= dat_i;`
80			`else`
81			`a[15:8] <= dat_i;`
82			`case(ir)`
83			`8'h80: state <= FETCH_IMM8;`
84			`8'h81: state <= FETCH_IMM16;`
85			`8'h83: state <= FETCH_IMM8;`
86			`8'hC0: state <= FETCH_IMM8;`
87			`8'hC1: state <= FETCH_IMM8;`
88			`8'hC6: state <= FETCH_IMM8;`
89			`8'hC7: state <= FETCH_IMM16;`
90			`8'hF6: state <= FETCH_IMM8;`
91			`8'hF7: state <= FETCH_IMM16;`
92			`default: state <= EXECUTE;`
93			`endcase`
94			`hasFetchedData <= 1'b1;`
95			`end`

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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [FETCH_DATA.v] - Blame information for rev 2