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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [IFETCH.v] - Blame information for rev 7

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//=============================================================================
//  Fetch instruction
//
//
//  (C) 2009,2010,2012 Robert Finch, Stratford
//  robfinch<remove>@opencores.org
//
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
//
// - All of the state control flags are reset.
//
// - If the current instruction is a prefix then we want to shift it
//   into the prefix buffer before fetching the instruction. Also
//   interrupts are blocked if the previous instruction is a prefix.
//
// - two bytes are fetched at once if the instruction is aligned on
//   an even address. This saves a bus cycle most of the time.
//
// ToDo:
// - add an exception if more than two prefixes are present.
//
//=============================================================================
//
IFETCH:
        begin
                $display("CSIP: %h", csip);
                // Reset all instruction processing flags at instruction fetch
                cyc_type <= `CT_PASSIVE;
                mod <= 2'd0;
                rrr <= 3'd0;
                rm <= 3'd0;
                sxi <= 1'b0;
                hasFetchedModrm <= 1'b0;
                hasFetchedDisp8 <= 1'b0;
                hasFetchedDisp16 <= 1'b0;
                hasFetchedVector <= 1'b0;
                hasStoredData <= 1'b0;
                hasFetchedData <= 1'b0;
                data16 <= 16'h0000;
                cnt <= 7'd0;
//              if (prefix1!=8'h00 && prefix2 !=8'h00 && is_prefix)
//                      state <= TRIPLE_PREFIX;
                if (is_prefix) begin
                        prefix1 <= ir;
                        prefix2 <= prefix1;
                end
                else begin
                        prefix1 <= 8'h00;
                        prefix2 <= 8'h00;
                end
 
        if (pe_nmi & checkForInts) begin
            state <= INT2;
            rst_nmi <= 1'b1;
            int_num <= 8'h02;
            ir <= `NOP;
        end
        else if (irq_i & ie & checkForInts) begin
            state <= INTA0;
            ir <= `NOP;
        end
        else if (ir==`HLT) begin
                        state <= IFETCH;
                cyc_type <= `CT_HALT;
        end
        else begin
                        state <= IFETCH_ACK;
                        read(`CT_CODE,csip);
                        inta_o <= 1'b0;
                        mio_o <= 1'b1;
                        lock_o <= bus_locked;
                end
        end
 
IFETCH_ACK:
        if (ack_i) begin
                nack_ir();
                $display("IR: %h",dat_i);
                if (!hasPrefix)
                        ir_ip <= ip;
//              ir_ip <= dat_i;
                w <= dat_i[0];
                d <= dat_i[1];
                v <= dat_i[1];
                sxi <= dat_i[1];
                sreg2 <= dat_i[4:3];
                sreg3 <= {1'b0,dat_i[4:3]};
                ir2 <= 8'h00;
                state <= DECODE;
        end
 
// Fetch extended opcode
//
XI_FETCH:
        begin
                read(`CT_CODE,csip);
                state <= XI_FETCH_ACK;
        end
 
XI_FETCH_ACK:
        if (ack_i) begin
                nack_ir2();
                state <= DECODER2;
        end

Line No.	Rev	Author	Line
1	2	robfinch	`//=============================================================================`
2			`// Fetch instruction`
3			`//`
4			`//`
5			`// (C) 2009,2010,2012 Robert Finch, Stratford`
6			`// robfinch<remove>@opencores.org`
7			`//`
8			`//`
9			`// This source file is free software: you can redistribute it and/or modify`
10			`// it under the terms of the GNU Lesser General Public License as published`
11			`// by the Free Software Foundation, either version 3 of the License, or`
12			`// (at your option) any later version.`
13			`//`
14			`// This source file is distributed in the hope that it will be useful,`
15			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
16			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
17			`// GNU General Public License for more details.`
18			`//`
19			`// You should have received a copy of the GNU General Public License`
20			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
21			`//`
22			`//`
23			`// - All of the state control flags are reset.`
24			`//`
25			`// - If the current instruction is a prefix then we want to shift it`
26			`// into the prefix buffer before fetching the instruction. Also`
27			`// interrupts are blocked if the previous instruction is a prefix.`
28			`//`
29			`// - two bytes are fetched at once if the instruction is aligned on`
30			`// an even address. This saves a bus cycle most of the time.`
31			`//`
32			`// ToDo:`
33			`// - add an exception if more than two prefixes are present.`
34			`//`
35			`//=============================================================================`
36			`//`
37			`IFETCH:`
38			`begin`
39	7	robfinch	`$display("CSIP: %h", csip);`
40	2	robfinch	`// Reset all instruction processing flags at instruction fetch`
41			cyc_type <= `CT_PASSIVE;
42			`mod <= 2'd0;`
43			`rrr <= 3'd0;`
44			`rm <= 3'd0;`
45			`sxi <= 1'b0;`
46			`hasFetchedModrm <= 1'b0;`
47			`hasFetchedDisp8 <= 1'b0;`
48			`hasFetchedDisp16 <= 1'b0;`
49			`hasFetchedVector <= 1'b0;`
50			`hasStoredData <= 1'b0;`
51			`hasFetchedData <= 1'b0;`
52			`data16 <= 16'h0000;`
53			`cnt <= 7'd0;`
54			`// if (prefix1!=8'h00 && prefix2 !=8'h00 && is_prefix)`
55			`// state <= TRIPLE_PREFIX;`
56			`if (is_prefix) begin`
57			`prefix1 <= ir;`
58			`prefix2 <= prefix1;`
59			`end`
60			`else begin`
61			`prefix1 <= 8'h00;`
62			`prefix2 <= 8'h00;`
63			`end`
64
65			`if (pe_nmi & checkForInts) begin`
66			`state <= INT2;`
67			`rst_nmi <= 1'b1;`
68			`int_num <= 8'h02;`
69			ir <= `NOP;
70			`end`
71			`else if (irq_i & ie & checkForInts) begin`
72			`state <= INTA0;`
73			ir <= `NOP;
74			`end`
75			else if (ir==`HLT) begin
76			`state <= IFETCH;`
77			cyc_type <= `CT_HALT;
78			`end`
79			`else begin`
80			`state <= IFETCH_ACK;`
81	7	robfinch	read(`CT_CODE,csip);
82	2	robfinch	`inta_o <= 1'b0;`
83			`mio_o <= 1'b1;`
84			`lock_o <= bus_locked;`
85			`end`
86			`end`
87
88			`IFETCH_ACK:`
89			`if (ack_i) begin`
90	7	robfinch	`nack_ir();`
91	2	robfinch	`$display("IR: %h",dat_i);`
92			`if (!hasPrefix)`
93			`ir_ip <= ip;`
94			`// ir_ip <= dat_i;`
95			`w <= dat_i[0];`
96			`d <= dat_i[1];`
97	4	robfinch	`v <= dat_i[1];`
98	2	robfinch	`sxi <= dat_i[1];`
99			`sreg2 <= dat_i[4:3];`
100			`sreg3 <= {1'b0,dat_i[4:3]};`
101			`ir2 <= 8'h00;`
102			`state <= DECODE;`
103			`end`
104
105			`// Fetch extended opcode`
106			`//`
107			`XI_FETCH:`
108			`begin`
109	7	robfinch	read(`CT_CODE,csip);
110	2	robfinch	`state <= XI_FETCH_ACK;`
111			`end`
112
113			`XI_FETCH_ACK:`
114			`if (ack_i) begin`
115	7	robfinch	`nack_ir2();`
116	2	robfinch	`state <= DECODER2;`
117			`end`

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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [IFETCH.v] - Blame information for rev 7