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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [IRET.v] - Blame information for rev 2

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1 2 robfinch 
// ============================================================================
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//  IRET
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//  - return from interrupt
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//
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//
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//  2009-2012  Robert Finch
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//  robfinch@opencores.org
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.
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//
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//
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//
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//  Verilog
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//
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//  IRET: return from interrupt
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//  Fetch cs:ip from stack
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//  pop ip
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//  pop cs
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//  pop flags
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// ============================================================================
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//
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IRET1:
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        begin
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                `INITIATE_STACK_POP
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                state <= IRET2;
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        end
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IRET2:
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        if (ack_i) begin
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                `PAUSE_STACK_POP
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                ip[7:0] <= dat_i;
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                state <= IRET3;
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        end
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IRET3:
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        begin
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                `CONTINUE_STACK_POP
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                state <= IRET4;
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        end
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IRET4:
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        if (ack_i) begin
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                `PAUSE_STACK_POP
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                ip[15:8] <= dat_i;
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                state <= IRET5;
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        end
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IRET5:
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        begin
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                `CONTINUE_STACK_POP
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                state <= IRET6;
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        end
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IRET6:
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        if (ack_i) begin
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                `PAUSE_STACK_POP
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                cs[7:0] <= dat_i;
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                state <= IRET7;
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        end
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IRET7:
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        begin
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                `CONTINUE_STACK_POP
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                state <= IRET8;
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        end
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IRET8:
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        if (ack_i) begin
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                `PAUSE_STACK_POP
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                cs[15:8] <= dat_i;
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                state <= IRET9;
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        end
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IRET9:
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        begin
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                `CONTINUE_STACK_POP
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                state <= IRET10;
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        end
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IRET10:
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        if (ack_i) begin
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                `PAUSE_STACK_POP
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                cf <= dat_i[0];
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                pf <= dat_i[2];
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                af <= dat_i[4];
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                zf <= dat_i[6];
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                sf <= dat_i[7];
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                state <= IRET11;
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        end
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IRET11:
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        begin
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                `CONTINUE_STACK_POP
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                state <= IRET12;
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        end
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IRET12:
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        if (ack_i) begin
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                cyc_type <= `CT_PASSIVE;
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                sp    <= sp_inc;
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                lock_o <= 1'b0;
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                cyc_o <= 1'b0;
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                stb_o <= 1'b0;
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                tf <= dat_i[0];
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                ie <= dat_i[1];
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                df <= dat_i[2];
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                vf <= dat_i[3];
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                state <= IFETCH;
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        end

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