OpenCores
URL https://opencores.org/ocsvn/rtf8088/rtf8088/trunk

Subversion Repositories rtf8088

[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [OUTSB.v] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 robfinch
// This source file is free software: you can redistribute it and/or modify 
2
// it under the terms of the GNU Lesser General Public License as published 
3
// by the Free Software Foundation, either version 3 of the License, or     
4
// (at your option) any later version.                                      
5
//                                                                          
6
// This source file is distributed in the hope that it will be useful,      
7
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
8
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
9
// GNU General Public License for more details.                             
10
//                                                                          
11
// You should have received a copy of the GNU General Public License        
12
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
13
//
14
OUTSB:
15
`include "check_for_ints.v"
16
        else if (repdone)
17
                state <= IFETCH;
18
        else if (!cyc_o) begin
19
                cyc_type <= `CT_RDMEM;
20
                cyc_o <= 1'b1;
21
                stb_o <= 1'b1;
22
                adr_o <= dssi;
23
        end
24
        else if (ack_i) begin
25
                cyc_type <= `CT_PASSIVE;
26
                cyc_o <= 1'b0;
27
                stb_o <= 1'b0;
28
                res[7:0] <= dat_i;
29
                state <= OUTSB2;
30
        end
31
OUTSB2:
32
        if (!cyc_o) begin
33
                cyc_type <= `CT_WRIO;
34
                cyc_o <= 1'b1;
35
                stb_o <= 1'b1;
36
                adr_o <= {`SEG_SHIFT,dx};
37
                dat_o <= res[7:0];
38
                we_o <= 1'b1;
39
        end
40
        else if (ack_i) begin
41
                cyc_type <= `CT_PASSIVE;
42
                cyc_o <= 1'b0;
43
                stb_o <= 1'b0;
44
                we_o <= 1'b0;
45
                if (df)
46
                        si <= si - 16'd1;
47
                else
48
                        si <= si + 16'd1;
49
                if (repz|repnz) cx <= cx_dec;
50
                state <= repz|repnz ? OUTSB : IFETCH;
51
        end

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.