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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [POP.v] - Blame information for rev 2

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// ============================================================================
//  POP register from stack
//
//
//  (C) 2009,2010  Robert Finch
//  robfinch[remove]@opencores.org
//  Stratford
//
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
//
//  Verilog 
//
// ============================================================================
//
POP:
        begin
                cyc_type <= `CT_RDMEM;
                lock_o <= 1'b1;
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                adr_o <= sssp;
                w <= 1'b1;
                rrr <= ir[2:0];
                state <= POP1;
        end
POP1:
        if (ack_i) begin
                cyc_type <= `CT_PASSIVE;
                stb_o <= 1'b0;
                sp <= sp_inc;
                res[7:0] <= dat_i;
                case(ir)
                `POP_SS: begin rrr <= 3'd2; end
                `POP_ES: begin rrr <= 3'd0; end
                `POP_DS: begin rrr <= 3'd3; end
                `POPF:
                        begin
                                cf <= dat_i[0];
                                pf <= dat_i[2];
                                af <= dat_i[4];
                                zf <= dat_i[6];
                                sf <= dat_i[7];
                        end
                default: ;
                endcase
                state <= POP2;
        end
POP2:
        begin
                `CONTINUE_STACK_POP
                state <= POP3;
        end
POP3:
        if (ack_i) begin
                state <= IFETCH;
                cyc_type <= `CT_PASSIVE;
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sp <= sp_inc;
                res[15:8] <= dat_i;
                case(ir)
                `POP_AX,`POP_CX,`POP_BX,`POP_DX,
                `POP_SI,`POP_DI,`POP_BP,`POP_SP:
                        wrregs <= 1'b1;
                `POP_SS,`POP_ES,`POP_DS:
                        wrsregs <= 1'b1;
                `POPF:
                        begin
                                tf <= dat_i[0];
                                ie <= dat_i[1];
                                df <= dat_i[2];
                                vf <= dat_i[3];
                        end
                `POP_MEM:
                        state <= STORE_DATA;
                default: ;
                endcase
        end

Line No.	Rev	Author	Line
1	2	robfinch	`// ============================================================================`
2			`// POP register from stack`
3			`//`
4			`//`
5			`// (C) 2009,2010 Robert Finch`
6			`// robfinch[remove]@opencores.org`
7			`// Stratford`
8			`//`
9			`//`
10			`// This source file is free software: you can redistribute it and/or modify`
11			`// it under the terms of the GNU Lesser General Public License as published`
12			`// by the Free Software Foundation, either version 3 of the License, or`
13			`// (at your option) any later version.`
14			`//`
15			`// This source file is distributed in the hope that it will be useful,`
16			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
17			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
18			`// GNU General Public License for more details.`
19			`//`
20			`// You should have received a copy of the GNU General Public License`
21			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
22			`//`
23			`//`
24			`// Verilog`
25			`//`
26			`// ============================================================================`
27			`//`
28			`POP:`
29			`begin`
30			cyc_type <= `CT_RDMEM;
31			`lock_o <= 1'b1;`
32			`cyc_o <= 1'b1;`
33			`stb_o <= 1'b1;`
34			`adr_o <= sssp;`
35			`w <= 1'b1;`
36			`rrr <= ir[2:0];`
37			`state <= POP1;`
38			`end`
39			`POP1:`
40			`if (ack_i) begin`
41			cyc_type <= `CT_PASSIVE;
42			`stb_o <= 1'b0;`
43			`sp <= sp_inc;`
44			`res[7:0] <= dat_i;`
45			`case(ir)`
46			`POP_SS: begin rrr <= 3'd2; end
47			`POP_ES: begin rrr <= 3'd0; end
48			`POP_DS: begin rrr <= 3'd3; end
49			`POPF:
50			`begin`
51			`cf <= dat_i[0];`
52			`pf <= dat_i[2];`
53			`af <= dat_i[4];`
54			`zf <= dat_i[6];`
55			`sf <= dat_i[7];`
56			`end`
57			`default: ;`
58			`endcase`
59			`state <= POP2;`
60			`end`
61			`POP2:`
62			`begin`
63			`CONTINUE_STACK_POP
64			`state <= POP3;`
65			`end`
66			`POP3:`
67			`if (ack_i) begin`
68			`state <= IFETCH;`
69			cyc_type <= `CT_PASSIVE;
70			`lock_o <= 1'b0;`
71			`cyc_o <= 1'b0;`
72			`stb_o <= 1'b0;`
73			`sp <= sp_inc;`
74			`res[15:8] <= dat_i;`
75			`case(ir)`
76			`POP_AX,`POP_CX,`POP_BX,`POP_DX,
77			`POP_SI,`POP_DI,`POP_BP,`POP_SP:
78			`wrregs <= 1'b1;`
79			`POP_SS,`POP_ES,`POP_DS:
80			`wrsregs <= 1'b1;`
81			`POPF:
82			`begin`
83			`tf <= dat_i[0];`
84			`ie <= dat_i[1];`
85			`df <= dat_i[2];`
86			`vf <= dat_i[3];`
87			`end`
88			`POP_MEM:
89			`state <= STORE_DATA;`
90			`default: ;`
91			`endcase`
92			`end`

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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [POP.v] - Blame information for rev 2