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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [STORE_DATA.v] - Blame information for rev 2
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robfinch |
// ============================================================================
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// STORE_DATA
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// - store data to memory.
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//
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//
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// (C) 2009,2010,2012 Robert Finch
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// robfinch[remove]@opencores.org
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// Verilog
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//
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// ============================================================================
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//
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STORE_DATA:
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begin
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cyc_type <= `CT_WRMEM;
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lock_o <= bus_locked | w;
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cyc_o <= 1'b1;
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stb_o <= 1'b1;
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we_o <= 1'b1;
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adr_o <= ea;
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dat_o <= res[7:0];
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state <= STORE_DATA1;
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end
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STORE_DATA1:
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if (ack_i) begin
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cyc_type <= `CT_PASSIVE;
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stb_o <= 1'b0;
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we_o <= 1'b0;
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if (w) begin
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state <= STORE_DATA2;
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end
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else begin
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cyc_o <= 1'b0;
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lock_o <= 1'b0;
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state <= IFETCH;
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end
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end
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STORE_DATA2:
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begin
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cyc_type <= `CT_WRMEM;
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stb_o <= 1'b1;
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we_o <= 1'b1;
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adr_o <= ea_inc;
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dat_o <= res[15:8];
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state <= STORE_DATA3;
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end
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STORE_DATA3:
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if (ack_i) begin
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cyc_type <= `CT_PASSIVE;
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lock_o <= 1'b0;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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we_o <= 1'b0;
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state <= IFETCH;
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end
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