URL https://opencores.org/ocsvn/rtf8088/rtf8088/trunk

Subversion Repositories rtf8088

[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [STOS.v] - Blame information for rev 8

Details | Compare with Previous | View Log


//=============================================================================
//  STOSB,STOSW
//  Store string data to memory.
//
//
//  2009-2013 Robert Finch
//  Stratford
//  robfinch<remove>@finitron.ca
//
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
//=============================================================================
//
STOS:
        if (pe_nmi) begin
                rst_nmi <= 1'b1;
                int_num <= 8'h02;
                ir <= `NOP;
                state <= INT2;
        end
        else if (irq_i & ie) begin
                ir <= `NOP;
                state <= INTA0;
        end
        else if (w && (di==16'hFFFF)) begin
                ir <= `NOP;
                int_num <= 8'd13;
                state <= INT2;
        end
        else if (repdone)
                state <= IFETCH;
        else begin
                if (!cyc_o) begin
                        cyc_type <= `CT_WRMEM;
                        lock_o <= w;
                        cyc_o <= 1'b1;
                        stb_o <= 1'b1;
                        we_o  <= 1'b1;
                        adr_o <= esdi;
                        dat_o <= (w & df) ? ah : al;
                end
                else if (ack_i) begin
                        cyc_type <= `CT_PASSIVE;
                        if (repz|repnz) begin
                                state <= w ? STOS1 : STOS;
                                cx <= cx_dec;
                        end
                        else
                                state <= w ? STOS1 : IFETCH;
                        lock_o <= w;
                        cyc_o <= w;
                        stb_o <= 1'b0;
                        we_o  <= 1'b0;
                        if (df)
                                di <= di_dec;
                        else
                                di <= di_inc;
                end
        end
STOS1:
        begin
                cyc_type <= `CT_WRMEM;
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o  <= 1'b1;
                adr_o <= esdi;
                dat_o <= df ? al : ah;
                state <= STOS2;
        end
STOS2:
        if (ack_i) begin
                cyc_type <= `CT_PASSIVE;
                if (repz|repnz)
                        state <= STOS;
                else
                        state <= IFETCH;
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o  <= 1'b0;
                if (df)
                        di <= di_dec;
                else
                        di <= di_inc;
        end

Line No.	Rev	Author	Line
1	2	robfinch	`//=============================================================================`
2			`// STOSB,STOSW`
3			`// Store string data to memory.`
4			`//`
5			`//`
6	8	robfinch	`// 2009-2013 Robert Finch`
7	2	robfinch	`// Stratford`
8	8	robfinch	`// robfinch<remove>@finitron.ca`
9	2	robfinch	`//`
10			`//`
11			`// This source file is free software: you can redistribute it and/or modify`
12			`// it under the terms of the GNU Lesser General Public License as published`
13			`// by the Free Software Foundation, either version 3 of the License, or`
14			`// (at your option) any later version.`
15			`//`
16			`// This source file is distributed in the hope that it will be useful,`
17			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
18			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
19			`// GNU General Public License for more details.`
20			`//`
21			`// You should have received a copy of the GNU General Public License`
22			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
23			`//`
24			`//=============================================================================`
25			`//`
26			`STOS:`
27	8	robfinch	`if (pe_nmi) begin`
28			`rst_nmi <= 1'b1;`
29			`int_num <= 8'h02;`
30			ir <= `NOP;
31			`state <= INT2;`
32			`end`
33			`else if (irq_i & ie) begin`
34			ir <= `NOP;
35			`state <= INTA0;`
36			`end`
37	2	robfinch	`else if (w && (di==16'hFFFF)) begin`
38			ir <= `NOP;
39			`int_num <= 8'd13;`
40	8	robfinch	`state <= INT2;`
41	2	robfinch	`end`
42			`else if (repdone)`
43			`state <= IFETCH;`
44			`else begin`
45			`if (!cyc_o) begin`
46			cyc_type <= `CT_WRMEM;
47			`lock_o <= w;`
48			`cyc_o <= 1'b1;`
49			`stb_o <= 1'b1;`
50			`we_o <= 1'b1;`
51			`adr_o <= esdi;`
52			`dat_o <= (w & df) ? ah : al;`
53			`end`
54			`else if (ack_i) begin`
55			cyc_type <= `CT_PASSIVE;
56			`if (repz\|repnz) begin`
57			`state <= w ? STOS1 : STOS;`
58			`cx <= cx_dec;`
59			`end`
60			`else`
61			`state <= w ? STOS1 : IFETCH;`
62			`lock_o <= w;`
63			`cyc_o <= w;`
64			`stb_o <= 1'b0;`
65			`we_o <= 1'b0;`
66			`if (df)`
67			`di <= di_dec;`
68			`else`
69			`di <= di_inc;`
70			`end`
71			`end`
72			`STOS1:`
73			`begin`
74			cyc_type <= `CT_WRMEM;
75			`cyc_o <= 1'b1;`
76			`stb_o <= 1'b1;`
77			`we_o <= 1'b1;`
78			`adr_o <= esdi;`
79			`dat_o <= df ? al : ah;`
80			`state <= STOS2;`
81			`end`
82			`STOS2:`
83			`if (ack_i) begin`
84			cyc_type <= `CT_PASSIVE;
85			`if (repz\|repnz)`
86			`state <= STOS;`
87			`else`
88			`state <= IFETCH;`
89			`lock_o <= 1'b0;`
90			`cyc_o <= 1'b0;`
91			`stb_o <= 1'b0;`
92			`we_o <= 1'b0;`
93			`if (df)`
94			`di <= di_dec;`
95			`else`
96			`di <= di_inc;`
97			`end`

Browse

Tools

Subversion Repositories rtf8088

[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [STOS.v] - Blame information for rev 8