OpenCores
URL https://opencores.org/ocsvn/rtf8088/rtf8088/trunk

Subversion Repositories rtf8088

[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [rtf8088.v] - Blame information for rev 4

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 robfinch
// ============================================================================
2
//  8088 Compatible CPU.
3
//
4
//
5
//  (C) 2009,2010  Robert Finch, Stratford
6
//  robfinch[remove]@opencores.org
7
//
8
//
9
//
10
// This source file is free software: you can redistribute it and/or modify 
11
// it under the terms of the GNU Lesser General Public License as published 
12
// by the Free Software Foundation, either version 3 of the License, or     
13
// (at your option) any later version.                                      
14
//                                                                          
15
// This source file is distributed in the hope that it will be useful,      
16
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
17
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
18
// GNU General Public License for more details.                             
19
//                                                                          
20
// You should have received a copy of the GNU General Public License        
21
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
22
//
23
//
24
//  Verilog 
25
//  Webpack 9.2i xc3s1000 4-ft256
26
//  2550 slices / 4900 LUTs / 61 MHz
27
//  650 ff's / 2 MULTs
28
//
29
//  Webpack 14.3  xc6slx45 3-csg324
30 4 robfinch
//  736 ff's 4433 LUTs / 90.360 MHz
31 2 robfinch
// ============================================================================
32
 
33
//`define BYTES_ONLY    1'b1
34
 
35
//`define BIG_SEGS
36
`ifdef BIG_SEGS
37
`define SEG_SHIFT               8'b0
38
`define AMSB                    23
39
`define CS_RESET                16'hFF00
40
`else
41
`define SEG_SHIFT               4'b0
42
`define AMSB                    19
43
`define CS_RESET                16'hF000
44
`endif
45
 
46
// Opcodes
47
//
48
`define MOV_RR  8'b1000100x
49
`define MOV_MR  8'b1000101x
50
`define MOV_IM  8'b1100011x
51
`define MOV_MA  8'b1010000x
52
`define MOV_AM  8'b0101001x
53
 
54
`define ADD                     8'b000000xx
55
`define ADD_ALI8        8'h04
56
`define ADD_AXI16       8'h05
57
`define PUSH_ES         8'h06
58
`define POP_ES          8'h07
59
`define OR          8'b000010xx
60
`define AAD                     8'h0A
61
`define AAM                     8'h0A
62
`define OR_ALI8         8'h0C
63
`define OR_AXI16        8'h0D
64
`define PUSH_CS     8'h0E
65
`define EXTOP           8'h0F   // extended opcode
66
 
67
`define ADC                     8'b000100xx
68
`define ADC_ALI8        8'h14
69
`define ADC_AXI16       8'h15
70
`define PUSH_SS     8'h16
71
`define POP_SS          8'h17
72
`define SBB         8'b000110xx
73
`define SBB_ALI8        8'h1C
74
`define SBB_AXI16       8'h1D
75
`define PUSH_DS     8'h1E
76
`define POP_DS          8'h1F
77
 
78
`define AND                     8'b001000xx
79
`define AND_ALI8        8'h24
80
`define AND_AXI16       8'h25
81
`define ES                      8'h26
82
`define DAA                     8'h27
83
`define SUB             8'b001010xx
84
`define SUB_ALI8        8'h2C
85
`define SUB_AXI16       8'h2D
86
`define CS                      8'h2E
87
`define DAS                     8'h2F
88
 
89
`define XOR             8'b001100xx
90
`define XOR_ALI8        8'h34
91
`define XOR_AXI16       8'h35
92
`define SS                      8'h36
93
`define AAA                     8'h37
94
`define CMP                     8'b001110xx
95
`define CMP_ALI8        8'h3C
96
`define CMP_AXI16       8'h3D
97
`define DS                      8'h3E
98
`define AAS                     8'h3F
99
 
100
`define INC_REG 8'b01000xxx
101
`define INC_AX  8'h40
102
`define INC_CX  8'h41
103
`define INC_DX  8'h42
104
`define INC_BX  8'h43
105
`define INC_SP  8'h44
106
`define INC_BP  8'h45
107
`define INC_SI  8'h46
108
`define INC_DI  8'h47
109
`define DEC_REG 8'b01001xxx
110
`define DEC_AX  8'h48
111
`define DEC_CX  8'h49
112
`define DEC_DX  8'h4A
113
`define DEC_BX  8'h4B
114
`define DEC_SP  8'h4C
115
`define DEC_BP  8'h4D
116
`define DEC_SI  8'h4E
117
`define DEC_DI  8'h4F
118
 
119
`define PUSH_REG        8'b01010xxx
120
`define PUSH_AX 8'h50
121
`define PUSH_CX 8'h51
122
`define PUSH_DX 8'h52
123
`define PUSH_BX 8'h53
124
`define PUSH_SP 8'h54
125
`define PUSH_BP 8'h55
126
`define PUSH_SI 8'h56
127
`define PUSH_DI 8'h57
128
`define POP_REG         8'b01011xxx
129
`define POP_AX  8'h58
130
`define POP_CX  8'h59
131
`define POP_DX  8'h5A
132
`define POP_BX  8'h5B
133
`define POP_SP  8'h5C
134
`define POP_BP  8'h5D
135
`define POP_SI  8'h5E
136
`define POP_DI  8'h5F
137
 
138
`define PUSHA   8'h60
139
`define POPA    8'h61
140
`define BOUND   8'h62
141
`define ARPL    8'h63
142
`define FS              8'h64
143
`define GS              8'h65
144
`define INSB    8'h6C
145
`define INSW    8'h6D
146
`define OUTSB   8'h6E
147
`define OUTSW   8'h6F
148
 
149
`define Jcc             8'b0111xxxx
150
`define JO              8'h70
151
`define JNO             8'h71
152
`define JB              8'h72
153
`define JAE             8'h73
154
`define JE              8'h74
155
`define JNE             8'h75
156
`define JBE             8'h76
157
`define JA              8'h77
158
`define JS              8'h78
159
`define JNS             8'h79
160
`define JP              8'h7A
161
`define JNP             8'h7B
162
`define JL              8'h7C
163
`define JNL             8'h7D
164
`define JLE             8'h7E
165
`define JNLE    8'h7F
166
 
167
`define JNA             8'h76
168
`define JNAE    8'h72
169
`define JNB     8'h73
170
`define JNBE    8'h77
171
`define JC      8'h72
172
`define JNC     8'h73
173
`define JG              8'h7F
174
`define JNG             8'h7E
175
`define JGE             8'h7D
176
`define JNGE    8'h7C
177
`define JPE     8'h7A
178
`define JPO     8'h7B
179
 
180
`define ALU_I2R8        8'h80
181
`define ALU_I2R16       8'h81
182
`define TEST        8'b1000010x
183
`define XCHG_MEM        8'h86
184
`define MOV_RR8         8'h88
185
`define MOV_RR16        8'h89
186
`define MOV_MR8         8'h8A
187
`define MOV_MR16        8'h8B
188
`define MOV_S2R         8'h8C
189
`define LEA                     8'h8D
190
`define MOV_R2S         8'h8E
191
`define POP_MEM         8'h8F
192
 
193
`define XCHG_AXR        8'b10010xxx
194
`define NOP                     8'h90
195
`define CBW                     8'h98
196
`define CWD                     8'h99
197
`define CALLF           8'h9A
198
`define WAI         8'h9B
199
`define PUSHF           8'h9C
200
`define POPF            8'h9D
201
`define SAHF            8'h9E
202
`define LAHF            8'h9F
203
 
204
`define MOV_M2AL        8'hA0
205
`define MOV_M2AX        8'hA1
206
`define MOV_AL2M        8'hA2
207
`define MOV_AX2M        8'hA3
208
 
209
`define MOVSB           8'hA4
210
`define MOVSW           8'hA5
211
`define CMPSB           8'hA6
212
`define CMPSW           8'hA7
213
`define STOSB           8'hAA
214
`define STOSW           8'hAB
215
`define LODSB           8'hAC
216
`define LODSW           8'hAD
217
`define SCASB           8'hAE
218
`define SCASW           8'hAF
219
 
220
`define MOV_I2BYTREG    8'h1011_0xxx
221
`define MOV_I2AL        8'hB0
222
`define MOV_I2CL        8'hB1
223
`define MOV_I2DL        8'hB2
224
`define MOV_I2BL        8'hB3
225
`define MOV_I2AH        8'hB4
226
`define MOV_I2CH        8'hB5
227
`define MOV_I2DH        8'hB6
228
`define MOV_I2BH        8'hB7
229
`define MOV_I2AX        8'hB8
230
`define MOV_I2CX        8'hB9
231
`define MOV_I2DX        8'hBA
232
`define MOV_I2BX        8'hBB
233
`define MOV_I2SP        8'hBC
234
`define MOV_I2BP        8'hBD
235
`define MOV_I2SI        8'hBE
236
`define MOV_I2DI        8'hBF
237
 
238
`define RETPOP          8'hC2
239
`define RET                     8'hC3
240
`define LES                     8'hC4
241
`define LDS                     8'hC5
242
`define MOV_I8M         8'hC6
243
`define MOV_I16M        8'hC7
244
`define LEAVE           8'hC9
245
`define RETFPOP         8'hCA
246
`define RETF            8'hCB
247
`define INT3            8'hCC
248
`define INT             8'hCD
249
`define INTO            8'hCE
250
`define IRET            8'hCF
251
 
252
`define RCL_81  8'hD0
253
`define RCL_161 8'hD1
254
`define MORE1   8'hD4
255
`define MORE2   8'hD5
256
`define XLAT    8'hD7
257
 
258
`define LOOPNZ  8'hE0
259
`define LOOPZ   8'hE1
260
`define LOOP    8'hE2
261
`define JCXZ    8'hE3
262
`define INB             8'hE4
263
`define INW             8'hE5
264
`define OUTB    8'hE6
265
`define OUTW    8'hE7
266
`define CALL    8'hE8
267
`define JMP     8'hE9
268
`define JMPF    8'hEA
269
`define JMPS    8'hEB
270
`define INB_DX  8'hEC
271
`define INW_DX  8'hED
272
`define OUTB_DX 8'hEE
273
`define OUTW_DX 8'hEF
274
 
275
`define LOCK    8'hF0
276
`define REPNZ   8'hF2
277
`define REPZ    8'hF3
278
`define HLT             8'hF4
279
`define CMC             8'hF5
280
`define IMUL    8'b1111011x
281
`define CLC             8'hF8
282
`define STC             8'hF9
283
`define CLI             8'hFA
284
`define STI             8'hFB
285
`define CLD             8'hFC
286
`define STD             8'hFD
287
`define GRPFF   8'b1111111x
288
 
289
// extended opcodes
290
// "OF"
291
`define LLDT    8'h00
292
`define LxDT    8'h01
293
`define LAR             8'h02
294
`define LSL             8'h03
295
`define CLTS    8'h06
296
 
297
`define LSS             8'hB2
298
`define LFS             8'hB4
299
`define LGS             8'hB5
300
 
301
`define INITIATE_CODE_READ              cyc_type <= `CT_CODE; cyc_o <= 1'b1; stb_o <= 1'b1; we_o <= 1'b0; adr_o <= csip;
302
`define TERMINATE_CYCLE                 cyc_type <= `CT_PASSIVE; cyc_o <= 1'b0; stb_o <= 1'b0; we_o <= 1'b0;
303
`define TERMINATE_CODE_READ             cyc_type <= `CT_PASSIVE; cyc_o <= 1'b0; stb_o <= 1'b0; we_o <= 1'b0; ip <= ip_inc;
304
`define PAUSE_CODE_READ                 cyc_type <= `CT_PASSIVE; stb_o <= 1'b0; ip <= ip_inc;
305
`define CONTINUE_CODE_READ              cyc_type <= `CT_CODE; stb_o <= 1'b1; adr_o <= csip;
306
`define INITIATE_STACK_WRITE    cyc_type <= `CT_WRMEM; cyc_o <= 1'b1; stb_o <= 1'b1; we_o <= 1'b1; adr_o <= sssp;
307
`define PAUSE_STACK_WRITE               cyc_type <= `CT_PASSIVE; sp <= sp_dec; stb_o <= 1'b0; we_o <= 1'b0;
308
 
309
`define INITIATE_STACK_POP              cyc_type <= `CT_RDMEM; lock_o <= 1'b1; cyc_o <= 1'b1; stb_o <= 1'b1; adr_o <= sssp;
310
`define COMPLETE_STACK_POP              cyc_type <= `CT_PASSIVE; lock_o <= bus_locked; cyc_o <= 1'b0; stb_o <= 1'b0; sp <= sp_inc;
311
`define PAUSE_STACK_POP                 cyc_type <= `CT_PASSIVE; stb_o <= 1'b0; sp <= sp_inc;
312
`define CONTINUE_STACK_POP              cyc_type <= `CT_RDMEM; stb_o <= 1'b1; adr_o <= sssp;
313
 
314
 
315
/*
316
Some modrm codes specify register-immediate or memory-immediate operations.
317
The operation to be performed is coded in the rrr field as only one register
318
spec (rm) is required.
319
 
320
80/81/83
321
        rrr   Operation
322
        ---------------
323
        000 = ADD
324
        001 = OR
325
        010 = ADC
326
        011 = SBB
327
        100 = AND
328
        101 = SUB
329
        110 = XOR
330
        111 = CMP
331
FE/FF
332
        000 = INC
333
        001 = DEC
334
        010 = CALL
335
        011 =
336
        100 =
337
        101 =
338
        110 =
339
        111 =
340
F6/F7:
341
        000 = TEST
342
        001 =
343
        010 = NOT
344
        011 = NEG
345
        100 = MUL
346
        101 =
347
        110 =
348
        111 =
349
*/
350
`define ADDRESS_INACTIVE        20'hFFFFF
351
`define DATA_INACTIVE           8'hFF
352
 
353
`include "cycle_types.v"
354
 
355
module rtf8088(rst_i, clk_i, nmi_i, irq_i, busy_i, inta_o, lock_o, mio_o, cyc_o, stb_o, ack_i, we_o, adr_o, dat_i, dat_o);
356
// States
357
parameter IFETCH=8'd1;
358
parameter IFETCH_ACK = 8'd2;
359
parameter XI_FETCH = 8'd3;
360
parameter XI_FETCH_ACK = 8'd4;
361 3 robfinch
parameter REGFETCHA = 8'd5;
362 2 robfinch
parameter DECODE = 8'd7;
363
parameter DECODER2 = 8'd8;
364
parameter DECODER3 = 8'd9;
365
 
366
parameter FETCH_VECTOR = 8'd10;
367
parameter FETCH_IMM8 = 8'd11;
368
parameter FETCH_IMM8_ACK = 8'd12;
369
parameter FETCH_IMM16 = 8'd13;
370
parameter FETCH_IMM16_ACK = 8'd14;
371
parameter FETCH_IMM16a = 8'd15;
372
parameter FETCH_IMM16a_ACK = 8'd16;
373
 
374
parameter MOV_I2BYTREG = 8'd17;
375
 
376
parameter FETCH_DISP8 = 8'd18;
377
parameter FETCH_DISP16 = 8'd19;
378
parameter FETCH_DISP16_ACK = 8'd20;
379
parameter FETCH_DISP16a = 8'd21;
380
parameter FETCH_DISP16a_ACK = 8'd22;
381
parameter FETCH_DISP16b = 8'd23;
382
 
383
parameter FETCH_OFFSET = 8'd24;
384
parameter FETCH_OFFSET1 = 8'd25;
385
parameter FETCH_OFFSET2 = 8'd26;
386
parameter FETCH_OFFSET3 = 8'd27;
387
parameter FETCH_SEGMENT = 8'd28;
388
parameter FETCH_SEGMENT1 = 8'd29;
389
parameter FETCH_SEGMENT2 = 8'd30;
390
parameter FETCH_SEGMENT3 = 8'd31;
391
parameter FETCH_STK_ADJ1 = 8'd32;
392
parameter FETCH_STK_ADJ1_ACK = 8'd33;
393
parameter FETCH_STK_ADJ2 = 8'd34;
394
parameter FETCH_STK_ADJ2_ACK = 8'd35;
395
parameter FETCH_DATA = 8'd36;
396
parameter FETCH_DATA1 = 8'd37;
397
 
398
parameter BRANCH1 = 8'd40;
399
parameter BRANCH2 = 8'd41;
400
parameter BRANCH3 = 8'd42;
401
 
402
parameter PUSHA = 8'd43;
403
parameter PUSHA1= 8'd44;
404
parameter POPA = 8'd45;
405
parameter POPA1 = 8'd46;
406
parameter RET = 8'd47;
407
parameter RETF = 8'd48;
408
parameter RETF1 = 8'd49;
409
parameter JMPF = 8'd50;
410
 
411
parameter CALLF = 8'd51;
412
parameter CALLF1 = 8'd52;
413
parameter CALLF2 = 8'd53;
414
parameter CALLF3 = 8'd54;
415
parameter CALLF4 = 8'd55;
416
parameter CALLF5 = 8'd56;
417
parameter CALLF6 = 8'd57;
418
parameter CALLF7 = 8'd58;
419
 
420
parameter CALL = 8'd59;
421
parameter CALL1 = 8'd60;
422
parameter CALL2 = 8'd61;
423
parameter CALL3 = 8'd62;
424
 
425
parameter PUSH = 8'd63;
426
parameter PUSH1 = 8'd64;
427
parameter PUSH2 = 8'd65;
428
parameter PUSH3 = 8'd66;
429
 
430
parameter IRET = 8'd70;
431
parameter IRET1 = 8'd71;
432
parameter IRET2 = 8'd72;
433
 
434
parameter POP = 8'd73;
435
parameter POP1 = 8'd74;
436
parameter POP2 = 8'd75;
437
parameter POP3 = 8'd76;
438
 
439
parameter CALL_IN = 8'd77;
440
parameter CALL_IN1 = 8'd78;
441
parameter CALL_IN2 = 8'd79;
442
parameter CALL_IN3 = 8'd80;
443
parameter CALL_IN4 = 8'd81;
444
 
445
parameter STOS = 8'd83;
446
parameter STOS1 = 8'd84;
447
parameter STOS2 = 8'd85;
448
parameter MOVS = 8'd86;
449
parameter MOVS1 = 8'd87;
450
parameter MOVS2 = 8'd88;
451
parameter MOVS3 = 8'd89;
452
parameter MOVS4 = 8'd90;
453
parameter MOVS5 = 8'd91;
454
 
455
parameter WRITE_REG = 8'd92;
456
 
457
parameter EACALC = 8'd93;
458
parameter EACALC1 = 8'd94;
459
parameter EACALC_DISP8 = 8'd95;
460
parameter EACALC_DISP8_ACK = 8'd96;
461
parameter EACALC_DISP16 =  8'd97;
462
parameter EACALC_DISP16_ACK =  8'd98;
463
parameter EACALC_DISP16a =  8'd99;
464
parameter EACALC_DISP16a_ACK =  8'd100;
465
parameter EXECUTE = 8'd101;
466
 
467
parameter INB = 8'd102;
468
parameter INB1 = 8'd103;
469
parameter INB2 = 8'd104;
470
parameter INB3 = 8'd105;
471
parameter INW = 8'd106;
472
parameter INW1 = 8'd107;
473
parameter INW2 = 8'd108;
474
parameter INW3 = 8'd109;
475
parameter INW4 = 8'd110;
476
parameter INW5 = 8'd111;
477
 
478
parameter OUTB = 8'd112;
479
parameter OUTB_NACK = 8'd113;
480
parameter OUTB1 = 8'd114;
481
parameter OUTB1_NACK = 8'd115;
482
parameter OUTW = 8'd116;
483
parameter OUTW_NACK = 8'd117;
484
parameter OUTW1 = 8'd118;
485
parameter OUTW1_NACK = 8'd119;
486
parameter OUTW2 = 8'd120;
487
parameter OUTW2_NACK = 8'd121;
488
parameter FETCH_PORTNUMBER = 8'd122;
489
 
490
parameter INVALID_OPCODE = 8'd123;
491
parameter IRQ1 = 8'd126;
492
 
493
parameter JUMP_VECTOR1 = 8'd127;
494
parameter JUMP_VECTOR2 = 8'd128;
495
parameter JUMP_VECTOR3 = 8'd129;
496
parameter JUMP_VECTOR4 = 8'd130;
497
parameter JUMP_VECTOR5 = 8'd131;
498
parameter JUMP_VECTOR6 = 8'd132;
499
parameter JUMP_VECTOR7 = 8'd133;
500
parameter JUMP_VECTOR8 = 8'd134;
501
parameter JUMP_VECTOR9 = 8'd135;
502
 
503
parameter STORE_DATA = 8'd136;
504
parameter STORE_DATA1 = 8'd137;
505
parameter STORE_DATA2 = 8'd138;
506
parameter STORE_DATA3 = 8'd139;
507
 
508
parameter INTO = 8'd140;
509
parameter FIRST = 8'd141;
510
 
511
parameter INTA0 = 8'd142;
512
parameter INTA1 = 8'd143;
513
parameter INTA2 = 8'd144;
514
parameter INTA3 = 8'd145;
515
 
516
parameter RETPOP = 8'd150;
517
parameter RETPOP_NACK = 8'd151;
518
parameter RETPOP1 = 8'd152;
519
parameter RETPOP1_NACK = 8'd153;
520
 
521
parameter RETFPOP = 8'd154;
522
parameter RETFPOP1 = 8'd155;
523
parameter RETFPOP2 = 8'd156;
524
parameter RETFPOP3 = 8'd157;
525
parameter RETFPOP4 = 8'd158;
526
parameter RETFPOP5 = 8'd159;
527
parameter RETFPOP6 = 8'd160;
528
parameter RETFPOP7 = 8'd161;
529
parameter RETFPOP8 = 8'd162;
530
 
531
parameter XLAT_ACK = 8'd166;
532
 
533
parameter FETCH_DESC = 8'd170;
534
parameter FETCH_DESC1 = 8'd171;
535
parameter FETCH_DESC2 = 8'd172;
536
parameter FETCH_DESC3 = 8'd173;
537
parameter FETCH_DESC4 = 8'd174;
538
parameter FETCH_DESC5 = 8'd175;
539
 
540
parameter INSB = 8'd180;
541
parameter INSB1 = 8'd181;
542
parameter OUTSB = 8'd182;
543
parameter OUTSB1 = 8'd183;
544
 
545
parameter SCASB = 8'd185;
546
parameter SCASB1 = 8'd186;
547
parameter SCASW = 8'd187;
548
parameter SCASW1 = 8'd188;
549
parameter SCASW2 = 8'd189;
550
 
551
parameter CMPSW = 8'd190;
552
parameter CMPSW1 = 8'd191;
553
parameter CMPSW2 = 8'd192;
554
parameter CMPSW3 = 8'd193;
555
parameter CMPSW4 = 8'd194;
556
parameter CMPSW5 = 8'd195;
557
 
558
parameter LODS = 8'd196;
559
parameter LODS_NACK = 8'd197;
560
parameter LODS1 = 8'd198;
561
parameter LODS1_NACK = 8'd199;
562
 
563
parameter INSW = 8'd200;
564
parameter INSW1 = 8'd201;
565
parameter INSW2 = 8'd202;
566
parameter INSW3 = 8'd203;
567
 
568
parameter OUTSW = 8'd205;
569
parameter OUTSW1 = 8'd206;
570
parameter OUTSW2 = 8'd207;
571
parameter OUTSW3 = 8'd208;
572
 
573
parameter CALL_FIN = 8'd210;
574
parameter CALL_FIN1 = 8'd211;
575
parameter CALL_FIN2 = 8'd212;
576
parameter CALL_FIN3 = 8'd213;
577
parameter CALL_FIN4 = 8'd214;
578
 
579
parameter INT = 8'd220;
580
parameter INT1 = 8'd221;
581
parameter INT2 = 8'd222;
582
parameter INT3 = 8'd223;
583
parameter INT4 = 8'd224;
584
parameter INT5 = 8'd225;
585
parameter INT6 = 8'd226;
586
parameter INT7 = 8'd227;
587
parameter INT8 = 8'd228;
588
parameter INT9 = 8'd229;
589
parameter INT10 = 8'd230;
590
parameter INT11 = 8'd231;
591
parameter INT12 = 8'd232;
592
parameter INT13 = 8'd233;
593
parameter INT14 = 8'd234;
594
 
595
parameter IRET3 = 8'd235;
596
parameter IRET4 = 8'd236;
597
parameter IRET5 = 8'd237;
598
parameter IRET6 = 8'd238;
599
parameter IRET7 = 8'd239;
600
parameter IRET8 = 8'd240;
601
parameter IRET9 = 8'd241;
602
parameter IRET10 = 8'd242;
603
parameter IRET11 = 8'd243;
604
parameter IRET12 = 8'd244;
605
 
606
parameter INSB2 = 8'd246;
607
parameter OUTSB2 = 8'd247;
608
parameter XCHG_MEM = 8'd248;
609
 
610
parameter CMPSB = 8'd250;
611
parameter CMPSB1 = 8'd251;
612
parameter CMPSB2 = 8'd252;
613
parameter CMPSB3 = 8'd253;
614
parameter CMPSB4 = 8'd254;
615
 
616
 
617
input rst_i;
618
input clk_i;
619
input nmi_i;
620
input irq_i;
621
input busy_i;
622
output inta_o;
623
output lock_o;
624
output mio_o;
625
output cyc_o;
626
output stb_o;
627
input  ack_i;
628
output we_o;
629
output [`AMSB:0] adr_o;
630
input  [ 7:0] dat_i;
631
output [ 7:0] dat_o;
632
 
633
reg inta_o;
634
reg lock_o;
635
reg cyc_o;
636
reg stb_o;
637
reg we_o;
638
reg [`AMSB:0] adr_o;
639
reg [ 7:0] dat_o;
640
 
641
reg    mio_o;
642
wire   busy_i;
643
 
644
reg [1:0] seg_sel;                       // segment selection    0=ES,1=SS,2=CS (or none), 3=DS
645
 
646
reg [7:0] state;                 // machine state
647
reg [7:0] substate;
648
reg hasFetchedModrm;
649
reg hasFetchedDisp8;
650
reg hasFetchedDisp16;
651
reg hasFetchedData;
652
reg hasStoredData;
653
reg hasFetchedVector;
654
 
655
reg [15:0] res;                          // result bus
656
wire pres;                                      // parity result
657
wire reszw;                                     // zero word
658
wire reszb;                                     // zero byte
659
wire resnb;                                     // negative byte
660
wire resnw;                                     // negative word
661
wire resn;
662
wire resz;
663
 
664
reg [2:0] cyc_type;                      // type of bus sycle
665
reg w;                                          // 0=8 bit, 1=16 bit
666
reg d;
667 4 robfinch
reg v;                                          // 1=count in cl, 0 = count is one
668 2 robfinch
reg [1:0] mod;
669
reg [2:0] rrr;
670
reg [2:0] rm;
671
reg sxi;
672
reg [2:0] sreg;
673
reg [1:0] sreg2;
674
reg [2:0] sreg3;
675
reg [2:0] TTT;
676
reg [7:0] lock_insn;
677
reg [7:0] prefix1;
678
reg [7:0] prefix2;
679
reg [7:0] int_num;                       // interrupt number to execute
680
reg [15:0] seg_reg;                      // segment register value for memory access
681
reg [15:0] data16;                       // caches data
682
reg [15:0] disp16;                       // caches displacement
683
reg [15:0] offset;                       // caches offset
684
reg [15:0] selector;             // caches selector
685
reg [`AMSB:0] ea;                                // effective address
686
reg [39:0] desc;                 // buffer for sescriptor
687
reg [6:0] cnt;                           // counter
688
reg [1:0] S43;
689
reg wrregs;
690
reg wrsregs;
691
wire take_br;
692 4 robfinch
reg [3:0] shftamt;
693 2 robfinch
 
694
reg nmi_armed;
695
reg rst_nmi;                            // reset the nmi flag
696
wire pe_nmi;                            // indicates positive edge on nmi signal
697
 
698
wire RESET = rst_i;
699
wire CLK = clk_i;
700
wire NMI = nmi_i;
701
 
702
`include "REGFILE.v"
703
`include "CONTROL_LOGIC.v"
704
`include "which_seg.v"
705
evaluate_branch u4 (ir,cx,zf,cf,sf,vf,pf,take_br);
706
`include "ALU.v"
707
nmi_detector u6 (RESET, CLK, NMI, rst_nmi, pe_nmi);
708
 
709
always @(posedge CLK)
710
        if (RESET) begin
711
                pf <= 1'b0;
712
                cf <= 1'b0;
713
                df <= 1'b0;
714
                vf <= 1'b0;
715
                zf <= 1'b0;
716
                ie <= 1'b0;
717
                hasFetchedModrm <= 1'b0;
718
                cs <= `CS_RESET;
719
                ip <= 16'hFFF0;
720
                inta_o <= 1'b0;
721
                mio_o <= 1'b1;
722
                lock_o <= 1'b0;
723
                cyc_o <= 1'b0;
724
                stb_o <= 1'b0;
725
                we_o <= 1'b0;
726
                cyc_type <= `CT_PASSIVE;
727
                ir <= `NOP;
728
                prefix1 <= 8'h00;
729
                prefix2 <= 8'h00;
730
                rst_nmi <= 1'b1;
731
                wrregs <= 1'b0;
732
                wrsregs <= 1'b0;
733
                state <= IFETCH;
734
        end
735
        else begin
736
                rst_nmi <= 1'b0;
737
                wrregs <= 1'b0;
738
                wrsregs <= 1'b0;
739
 
740
`include "WRITE_BACK.v"
741
 
742
                case(state)
743
 
744
`include "IFETCH.v"
745
`include "DECODE.v"
746
`include "DECODER2.v"
747 3 robfinch
`include "REGFETCHA.v"
748 2 robfinch
`include "EACALC.v"
749
`include "CMPSB.v"
750
`include "CMPSW.v"
751
`include "MOVS.v"
752
`include "LODS.v"
753
`include "STOS.v"
754
`include "SCASB.v"
755
`include "SCASW.v"
756
`include "EXECUTE.v"
757
`include "FETCH_DATA.v"
758
`include "FETCH_DISP8.v"
759
`include "FETCH_DISP16.v"
760
`include "FETCH_IMMEDIATE.v"
761
`include "FETCH_OFFSET_AND_SEGMENT.v"
762
`include "MOV_I2BYTREG.v"
763
`include "STORE_DATA.v"
764
`include "BRANCH.v"
765
`include "CALL.v"
766
`include "CALLF.v"
767
`include "CALL_IN.v"
768
`include "INTA.v"
769
`include "INT.v"
770
`include "FETCH_STK_ADJ.v"
771
`include "RETPOP.v"
772
`include "RETFPOP.v"
773
`include "IRET.v"
774
`include "JUMP_VECTOR.v"
775
`include "PUSH.v"
776
`include "POP.v"
777
`include "INB.v"
778
`include "INW.v"
779
`include "OUTB.v"
780
`include "OUTW.v"
781
`include "INSB.v"
782
`include "OUTSB.v"
783
`include "XCHG_MEM.v"
784
 
785
                        default:
786
                                state <= IFETCH;
787
                        endcase
788
                end
789
 
790
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.