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[/] [rxaui_interface_and_xaui_to_rxaui_interface_adapter/] [ClockReset/] [sip_rxaui_clk_reset.v] - Blame information for rev 2

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1 2 tsahidanie 
//-----------------------------------------------------------------------------
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// Title         : Cloks and Reset generation
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// Project       : SIP
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//-----------------------------------------------------------------------------
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// File          : sip_rxaui_clk_reset.v
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// Author        : Lior Valency
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// Created       : 20/02/2008
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// Last modified : 20/02/2008
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//-----------------------------------------------------------------------------
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// Description : This block receive clock from serdes and generate clock for
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// port (serdes divided by 2). It also generate reset for all clock domains.
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//-----------------------------------------------------------------------------
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// Copyright (c) 2007  Marvell International Ltd.
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//
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// THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL SEMICONDUCTOR, INC.
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// NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT
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// OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE
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// DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL.
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// THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESS,
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// IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE.
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//
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//------------------------------------------------------------------------------
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// Modification history :
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// 12/12/2007  : created
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//-----------------------------------------------------------------------------
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`timescale 10ps / 10ps
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module sip_rxaui_clk_reset (/*AUTOARG*/
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   // Outputs
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   serdes_rx_clk_div2, rx_clk0, rx_clk1, serdes_rx_clk_reset_,
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   serdes_rx_clk_div2_reset_, txclk_out, serdes_txclk_in0_reset_,
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   serdes_txclk_in1_reset_, serdes_tx_clk_reset_,
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   // Inputs
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   scan_mode_, reset_, media_interface_mode, serdes_mode,
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   serdes_rx_clk, serdes_tx_clk, txclk_in0, txclk_in1
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   );
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   ///////////////
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   // INTERFACE //
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   ///////////////
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   // General
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   input      scan_mode_;
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   input      reset_;
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   input      media_interface_mode;
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   input      serdes_mode;
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   // Rx Clocks
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   input      serdes_rx_clk;
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   output     serdes_rx_clk_div2;
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   output     rx_clk0;
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   output     rx_clk1;
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   // Rx reset
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   output     serdes_rx_clk_reset_;
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   output     serdes_rx_clk_div2_reset_;
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   // TX Clocks
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   input      serdes_tx_clk;
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   input      txclk_in0;
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   input      txclk_in1;
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   output     txclk_out;
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   // Tx Reset
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   output     serdes_txclk_in0_reset_;
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   output     serdes_txclk_in1_reset_;
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   output     serdes_tx_clk_reset_;
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   /*AUTO-OUTPUT*/
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   // Beginning of automatic outputs (from unused autoinst outputs)
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   // End of automatics
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   /*AUTOINPUT*/
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   // Beginning of automatic inputs (from unused autoinst inputs)
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   // End of automatics
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   /*AUTOWIRE*/
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   // Beginning of automatic wires (for undeclared instantiated-module outputs)
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   // End of automatics
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   ////////////////////
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   // INTERNAL WIRES //
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   ////////////////////
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   wire       bypass_divider;
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   wire       serdes_tx_clk_div2;
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   wire       serdes_rx_clk_reset;
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   ///////////
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   // Logic //
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   ///////////
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   assign bypass_divider = ((scan_mode_ == 1'b0) |
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                            ((media_interface_mode == 1'b0) && (serdes_mode == 1'b0)));
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   ////////////
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   // CLOCKS //
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   ////////////
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   /* sip_clock_divider_by_2 AUTO_TEMPLATE(
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    .clk_div2           (serdes_rx_clk_div2),
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    .reset_             (serdes_rx_clk_reset_),
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    .clk                (serdes_rx_clk),
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    )*/
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   sip_clock_divider_by_2
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     rx_clk_div2(/*AUTOINST*/
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                 // Outputs
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                 .clk_div2              (serdes_rx_clk_div2),    // Templated
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                 // Inputs
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                 .reset_                (serdes_rx_clk_reset_),  // Templated
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                 .clk                   (serdes_rx_clk));        // Templated
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   sip_clk_mux rx_clk_mux0(.clk_in0(serdes_rx_clk_div2), .clk_in1(serdes_rx_clk), .selector(bypass_divider), .clk_out(rx_clk0));
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   sip_clk_mux rx_clk_mux1(.clk_in0(serdes_rx_clk_div2), .clk_in1(serdes_rx_clk), .selector(bypass_divider), .clk_out(rx_clk1));
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   /*sip_clock_divider_by_2 AUTO_TEMPLATE(
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    .clk_div2           (serdes_tx_clk_div2),
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    .reset_             (serdes_tx_clk_reset_),
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    .clk                (serdes_tx_clk),
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    )*/
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   sip_clock_divider_by_2
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     tx_clk_div2(/*AUTOINST*/
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                 // Outputs
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                 .clk_div2              (serdes_tx_clk_div2),    // Templated
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                 // Inputs
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                 .reset_                (serdes_tx_clk_reset_),  // Templated
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                 .clk                   (serdes_tx_clk));        // Templated
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   // Interface to the xpcs
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   sip_clk_mux xpcs_tx_clk_mux0(.clk_in0(serdes_tx_clk_div2), .clk_in1(serdes_tx_clk), .selector(bypass_divider), .clk_out(txclk_out));
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   ////////////
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   // RESETS //
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   ////////////
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   /*sip_reset_sync AUTO_TEMPLATE(
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    .load_config_       (),
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    .reset_out_         (serdes_rx_clk_reset_),
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    .reset_chg_         (),
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    .clk                (serdes_rx_clk),
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    .reset_in_          (reset_),
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   )*/
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   sip_reset_sync
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     rx_clk_reset(/*AUTOINST*/
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                  // Outputs
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                  .load_config_         (),                      // Templated
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                  .reset_out_           (serdes_rx_clk_reset_),  // Templated
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                  .reset_chg_           (),                      // Templated
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                  // Inputs
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                  .clk                  (serdes_rx_clk),         // Templated
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                  .reset_in_            (reset_),                // Templated
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                  .scan_mode_           (scan_mode_));
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   /*sip_reset_sync AUTO_TEMPLATE(
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    .load_config_       (),
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    .reset_out_         (serdes_rx_clk_div2_reset_),
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    .reset_chg_         (),
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    .clk                (serdes_rx_clk_div2),
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    .reset_in_          (reset_),
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   )*/
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   sip_reset_sync
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     rx_clk_div2_reset(/*AUTOINST*/
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                       // Outputs
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                       .load_config_    (),                      // Templated
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                       .reset_out_      (serdes_rx_clk_div2_reset_), // Templated
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                       .reset_chg_      (),                      // Templated
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                       // Inputs
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                       .clk             (serdes_rx_clk_div2),    // Templated
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                       .reset_in_       (reset_),                // Templated
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                       .scan_mode_      (scan_mode_));
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   /*sip_reset_sync AUTO_TEMPLATE(
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    .load_config_       (),
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    .reset_out_         (serdes_tx_clk_reset_),
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    .reset_chg_         (),
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    .clk                (serdes_tx_clk),
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    .reset_in_          (reset_),
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   )*/
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   sip_reset_sync
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     tx_clk_reset(/*AUTOINST*/
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                  // Outputs
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                  .load_config_         (),                      // Templated
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                  .reset_out_           (serdes_tx_clk_reset_),  // Templated
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                  .reset_chg_           (),                      // Templated
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                  // Inputs
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                  .clk                  (serdes_tx_clk),         // Templated
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                  .reset_in_            (reset_),                // Templated
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                  .scan_mode_           (scan_mode_));
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   /*sip_reset_sync AUTO_TEMPLATE(
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    .load_config_       (),
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    .reset_out_         (serdes_txclk_in0_reset_),
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    .reset_chg_         (),
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    .clk                (txclk_in0),
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    .reset_in_          (reset_),
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   )*/
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   sip_reset_sync
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     txclk_in0_reset(/*AUTOINST*/
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                     // Outputs
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                     .load_config_      (),                      // Templated
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                     .reset_out_        (serdes_txclk_in0_reset_), // Templated
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                     .reset_chg_        (),                      // Templated
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                     // Inputs
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                     .clk               (txclk_in0),             // Templated
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                     .reset_in_         (reset_),                // Templated
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                     .scan_mode_        (scan_mode_));
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   /*sip_reset_sync AUTO_TEMPLATE(
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    .load_config_       (),
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    .reset_out_         (serdes_txclk_in1_reset_),
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    .reset_chg_         (),
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    .clk                (txclk_in1),
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    .reset_in_          (reset_),
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   )*/
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   sip_reset_sync
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     txclk_in1_reset(/*AUTOINST*/
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                     // Outputs
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                     .load_config_      (),                      // Templated
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                     .reset_out_        (serdes_txclk_in1_reset_), // Templated
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                     .reset_chg_        (),                      // Templated
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                     // Inputs
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                     .clk               (txclk_in1),             // Templated
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                     .reset_in_         (reset_),                // Templated
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                     .scan_mode_        (scan_mode_));
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endmodule
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// Local Variables:
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// verilog-library-directories:( "." "../GenericModules/")
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// End:
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