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[/] [rxaui_interface_and_xaui_to_rxaui_interface_adapter/] [GenericModules/] [sip_clock_divider_by_2_glue.v] - Blame information for rev 2

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//-----------------------------------------------------------------------------
// Title         :Clock divider Glue
// Project       : SIP
//-----------------------------------------------------------------------------
// File          : sip_clock_divider_by_2_glue.v
// Author        : Lior Valency
// Created       : 21/02/2008 
// Last modified : 21/02/2008 
//-----------------------------------------------------------------------------
// Description : This clock set the value of <dp> and <dn> since we want
// the clock to be divided by 2, <dp> and <dn> should have the same value for
// every cc.
//-----------------------------------------------------------------------------
// Copyright (c) 2007  Marvell International Ltd.
//
// THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL SEMICONDUCTOR, INC.
// NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT
// OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE
// DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL.
// THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESS,
// IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE.
//
//------------------------------------------------------------------------------
// Modification history :
// 12/12/2007  : created
//-----------------------------------------------------------------------------
module sip_clock_divider_by_2_glue(/*AUTOARG*/
   // Outputs
   clk_div2,
   // Inputs
   reset_, clk
   );
 
   ///////////////
   // INTERFACE //  
   ///////////////
 
   // General
   input          reset_;
   input          clk;
 
   // Divider cell interface 
   output         clk_div2;
 
   /////////////////////
   // Regsiter & Wire //
   /////////////////////
 
   wire           clk_div2_inv;
   reg            clk_div2;
 
   ///////////
   // Logic //
   ///////////
 
   // Devide clock by 2
   assign clk_div2_inv = ~clk_div2;
 
   ////////
   // FF //
   ////////
 
   always @ (posedge clk or negedge reset_)
     begin
       if(~reset_)
         begin
           clk_div2 <= #1 1'b1;
         end
       else
         begin
           clk_div2 <= #1 clk_div2_inv;
         end
     end
 
endmodule // sip_clock_divider_by_2_glue

Line No.	Rev	Author	Line
1	2	tsahidanie	`//-----------------------------------------------------------------------------`
2			`// Title :Clock divider Glue`
3			`// Project : SIP`
4			`//-----------------------------------------------------------------------------`
5			`// File : sip_clock_divider_by_2_glue.v`
6			`// Author : Lior Valency`
7			`// Created : 21/02/2008`
8			`// Last modified : 21/02/2008`
9			`//-----------------------------------------------------------------------------`
10			`// Description : This clock set the value of <dp> and <dn> since we want`
11			`// the clock to be divided by 2, <dp> and <dn> should have the same value for`
12			`// every cc.`
13			`//-----------------------------------------------------------------------------`
14			`// Copyright (c) 2007 Marvell International Ltd.`
15			`//`
16			`// THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL SEMICONDUCTOR, INC.`
17			`// NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT`
18			`// OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE`
19			`// DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL.`
20			`// THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESS,`
21			`// IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE.`
22			`//`
23			`//------------------------------------------------------------------------------`
24			`// Modification history :`
25			`// 12/12/2007 : created`
26			`//-----------------------------------------------------------------------------`
27			`module sip_clock_divider_by_2_glue(/AUTOARG/`
28			`// Outputs`
29			`clk_div2,`
30			`// Inputs`
31			`reset_, clk`
32			`);`
33
34			`///////////////`
35			`// INTERFACE //`
36			`///////////////`
37
38			`// General`
39			`input reset_;`
40			`input clk;`
41
42			`// Divider cell interface`
43			`output clk_div2;`
44
45			`/////////////////////`
46			`// Regsiter & Wire //`
47			`/////////////////////`
48
49			`wire clk_div2_inv;`
50			`reg clk_div2;`
51
52			`///////////`
53			`// Logic //`
54			`///////////`
55
56			`// Devide clock by 2`
57			`assign clk_div2_inv = ~clk_div2;`
58
59			`////////`
60			`// FF //`
61			`////////`
62
63			`always @ (posedge clk or negedge reset_)`
64			`begin`
65			`if(~reset_)`
66			`begin`
67			`clk_div2 <= #1 1'b1;`
68			`end`
69			`else`
70			`begin`
71			`clk_div2 <= #1 clk_div2_inv;`
72			`end`
73			`end`
74
75			`endmodule // sip_clock_divider_by_2_glue`

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[/] [rxaui_interface_and_xaui_to_rxaui_interface_adapter/] [GenericModules/] [sip_clock_divider_by_2_glue.v] - Blame information for rev 2