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//-----------------------------------------------------------------------------
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// Title : Rxaui top
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// Project : SIP
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//-----------------------------------------------------------------------------
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// File : sip_rxaui_top.v
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// Author : Lior Valency
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// Created : 17/02/2008
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// Last modified : 17/02/2008
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//-----------------------------------------------------------------------------
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// Description : This block implement rxaui.
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// The purpose of this block is interleave 2 lanes to one serdes,
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// this block work in 2 clock dominas.
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//-----------------------------------------------------------------------------
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// Copyright (c) 2007 Marvell International Ltd.
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//
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// THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL SEMICONDUCTOR, INC.
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// NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT
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// OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE
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// DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL.
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// THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESS,
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// IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE.
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//
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//------------------------------------------------------------------------------
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// Modification history :
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// 12/12/2007 : created
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//-----------------------------------------------------------------------------
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`timescale 10ps / 10ps
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module sip_rxaui_top(/*AUTOARG*/
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// Outputs
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txclk_out, rxaui_tx_data, lock, rxdata_serdes0, rxdata_serdes1,
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rx_clk0, rx_clk1, rxaui_status,
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// Inputs
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reset_in_, media_interface_mode, scan_mode_, serdes_mode,
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txclk_in0, txclk_in1, txdata_serdes0, txdata_serdes1, s_tx_clk,
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lane0_sync_ok, lane1_sync_ok, rxaui_rx_data, s_sigdet, s_rx_clk
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);
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`include "sip_rxaui_params.inc"
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/* AUTO_CONSTANT (1'b0 or 1'b1 or 10'd0)*/
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///////////////
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// INTERFACE //
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///////////////
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// General
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input reset_in_;
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input media_interface_mode;
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input scan_mode_;
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input serdes_mode;
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// Tx Interface
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// XPCS
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input txclk_in0;
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input txclk_in1;
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input [19:0] txdata_serdes0;
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input [19:0] txdata_serdes1;
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output txclk_out;
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// Serdes
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input s_tx_clk;
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output [19:0] rxaui_tx_data;
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// Rx Interface
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// XPCS
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input lane0_sync_ok;
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input lane1_sync_ok;
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output lock;
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output [19:0] rxdata_serdes0;
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output [19:0] rxdata_serdes1;
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output rx_clk0;
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output rx_clk1;
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// Serdes
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input [19:0] rxaui_rx_data;
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input s_sigdet;
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input s_rx_clk;
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// Status
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output [8:0] rxaui_status;
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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// End of automatics
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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// End of automatics
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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// End of automatics
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////////////////////
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// INTERNAL WIRES //
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////////////////////
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wire serdes_rx_clk_div2;
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wire serdes_rx_clk_div2_reset_;
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wire serdes_rx_clk_reset_;
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wire serdes_tx_clk_reset_;
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wire serdes_txclk_in0_reset_;
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wire serdes_txclk_in1_reset_;
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/*sip_rxaui_rx_top AUTO_TEMPLATE(
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.serdes_rx_clk_reset({~serdes_rx_clk_reset_}),
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.serdes_rx_data (rxaui_rx_data[SERDES_DATA_W-1:0]),
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.serdes_rx_clk (s_rx_clk),
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)*/
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sip_rxaui_rx_top
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sip_rxaui_rx_top(/*AUTOINST*/
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// Outputs
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.lock (lock),
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.rxdata_serdes0 (rxdata_serdes0[SERDES_DATA_W-1:0]),
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.rxdata_serdes1 (rxdata_serdes1[SERDES_DATA_W-1:0]),
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.rxaui_status (rxaui_status[STATUS_REG_W-1:0]),
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// Inputs
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.serdes_rx_clk (s_rx_clk), // Templated
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.serdes_rx_clk_div2(serdes_rx_clk_div2),
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.serdes_rx_clk_reset_(serdes_rx_clk_reset_),
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.serdes_rx_clk_reset({~serdes_rx_clk_reset_}), // Templated
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.serdes_rx_clk_div2_reset_(serdes_rx_clk_div2_reset_),
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.rx_clk0 (rx_clk0),
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.rx_clk1 (rx_clk1),
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.media_interface_mode(media_interface_mode),
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.serdes_mode (serdes_mode),
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.lane0_sync_ok (lane0_sync_ok),
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.lane1_sync_ok (lane1_sync_ok),
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.s_sigdet (s_sigdet),
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.serdes_rx_data (rxaui_rx_data[SERDES_DATA_W-1:0])); // Templated
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/*sip_rxaui_tx_top AUTO_TEMPLATE(
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.serdes_tx_clk (s_tx_clk),
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)*/
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sip_rxaui_tx_top
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sip_rxaui_tx_top(/*AUTOINST*/
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// Outputs
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.rxaui_tx_data (rxaui_tx_data[SERDES_DATA_W-1:0]),
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// Inputs
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.serdes_tx_clk (s_tx_clk), // Templated
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.serdes_txclk_in0_reset_(serdes_txclk_in0_reset_),
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.serdes_txclk_in1_reset_(serdes_txclk_in1_reset_),
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.serdes_tx_clk_reset_(serdes_tx_clk_reset_),
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.media_interface_mode(media_interface_mode),
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.serdes_mode (serdes_mode),
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.txclk_in0 (txclk_in0),
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.txdata_serdes0 (txdata_serdes0[SERDES_DATA_W-1:0]),
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.txclk_in1 (txclk_in1),
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.txdata_serdes1 (txdata_serdes1[SERDES_DATA_W-1:0]));
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/*sip_rxaui_clk_reset AUTO_TEMPLATE(
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.reset_ (reset_in_),
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.serdes_tx_clk (s_tx_clk),
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.serdes_rx_clk (s_rx_clk),
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)*/
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sip_rxaui_clk_reset
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sip_rxaui_clk_reset(/*AUTOINST*/
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// Outputs
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.serdes_rx_clk_div2 (serdes_rx_clk_div2),
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.rx_clk0 (rx_clk0),
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.rx_clk1 (rx_clk1),
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.serdes_rx_clk_reset_ (serdes_rx_clk_reset_),
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.serdes_rx_clk_div2_reset_(serdes_rx_clk_div2_reset_),
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.txclk_out (txclk_out),
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.serdes_txclk_in0_reset_(serdes_txclk_in0_reset_),
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.serdes_txclk_in1_reset_(serdes_txclk_in1_reset_),
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.serdes_tx_clk_reset_ (serdes_tx_clk_reset_),
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// Inputs
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.scan_mode_ (scan_mode_),
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.reset_ (reset_in_), // Templated
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.media_interface_mode (media_interface_mode),
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.serdes_mode (serdes_mode),
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.serdes_rx_clk (s_rx_clk), // Templated
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.serdes_tx_clk (s_tx_clk), // Templated
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.txclk_in0 (txclk_in0),
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.txclk_in1 (txclk_in1));
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endmodule // sip_rxaui_top
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// Local Variables:
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// verilog-library-directories:( "." "../RxPath/" "../TxPath/" "../ClockReset/" "/proj1/galileo101/tomcat/MODELS/current/Model_link/")
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// End:
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