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[/] [scalable_arbiter/] [trunk/] [rtl/] [verilog/] [shifter.v] - Blame information for rev 12

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1 12 kendallc
/*
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 * Copyright (c) 2008-2009, Kendall Correll
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 *
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 * Permission to use, copy, modify, and distribute this software for any
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 * purpose with or without fee is hereby granted, provided that the above
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 * copyright notice and this permission notice appear in all copies.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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 */
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`timescale 1ns / 1ps
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module shifter #(
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        parameter depth = 0,
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        parameter width = 0
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)(
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        input enable,
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        input load,
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        input [(depth*width)-1:0] parallel_in,
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        input [width-1:0] serial_in,
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        output [(depth*width)-1:0] parallel_out,
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        output [width-1:0] serial_out,
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        input clock
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);
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reg [(depth*width)-1:0] internal;
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assign parallel_out = internal;
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assign serial_out = internal[width-1:0];
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integer i;
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always @(posedge clock)
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begin
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        if(enable)
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        begin
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                internal[(depth*width)-1-:width] <= load
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                        ? parallel_in[(depth*width)-1-:width]
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                        : serial_in;
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                for(i = depth - 1; i > 0; i = i - 1)
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                begin
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                        internal[(i*width)-1-:width] <= load
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                                ? parallel_in[(i*width)-1-:width]
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                                : internal[((i+1)*width)-1-:width];
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                end
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        end
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end
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endmodule

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