Subversion Repositories sdram

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<B><FONT COLOR="#bf0000" SIZE="+2" FACE="Helvetica, Arial">Project

                  Name: Synchronous-DRAM Controller (PC100 compliant)</FONT></B></P>

                  <P> </P>

                  <P><B><FONT SIZE="+1">Description</FONT></B></P>

                  <P>The Synchronous-DRAM controller core allows any synchronous

                  bus masters, such as most Intel microcontroller and x86 processors,

                  to effortlessly interface to a large capacity SDRAM as though

                  it were an SRAM. The core supports PC100 timing specifications.</P>

                  <P>By default the core is configured to work with 512K x 2 Bank

                  x 32-bit SDRAMs such as Samsung KM432S2030CT and Fujitsu MB81F643242B.

                  Easy modifications allows the core to work with different capacity

                  SDRAMs. Most of the critical parameters are defines in a global

                  include file allowing easy reconfigurability of the core.</P>

                  <P>The core handles much of the low level functions such as address

                  multiplexing, refresh generation and busy status generation.

                  In addtion, the non-trivial powerup initialization sequence is

                  also handled transparently to the host. Flexible refresh generation

                  permits burst refresh, normal refresh or everything in between.

                  The SDRAM mode-register can also be reprogrammed on the fly by

                  the host, although the core intializes the MRS with a default

                  value. This value can be compile-time adjustable.</P>

                  <P>The present design only supports 1 transfer per access. An

                  access is a host's request for a read or a write to the SDRAM.

                  A transfer is any data size from 1 byte, 1 word (16bit) or 1

                  long-word (32 bit). As soon as a multi-longword (i.e. burst)

                  data transfer protocol for the OR1K is adopted, variants of the

                  SDRAM controller supporting it will be offered.</P>

                  <P>The core also includes a set of synthesiable "test"

                  modules. When enabled for compilation, these test modules becomes

                  a host to the SDRAM controller and issues a series of read/write

                  test sequences to the SDRAM. This allows designers working on

                  FPGA/CPLD platforms to turn the SDRAM controller core into a

                  "stand-alone" SDRAM tester.</P>

                  <P>The core has been sucessfully tested with a Samsung KM416S1120D

                  SDRAM on Altera Flex10K20 FPGA and :Lattice isp3256 CPLD devices

                  (using the built-in tester).</P>

                  <P> </P>

                  <P><CENTER><IMG SRC="intefacing%20block%20diagram.gif"

                  ALIGN="BOTTOM" BORDER="0" NATURALSIZEFLAG="0"> <BR>

                  <I>Picture 1: Interfacing block diagram</I></CENTER></P>

                  <P> </P>

                  <P>Current Status:</P>

                  <UL>

                    <LI>Initial stable version avaible for down load : Use tag "sdram_8Mb_2Mx32_020200"

                    <LI>Fully parameterized version to be available. Use tag "sdram_param"

                    <LI><A HREF="http://www.opencores.org/cores/sdram/sdram_doc.pdf">Working

                    documentation</A> (72 KB) is available in Adobe PDF format.

                  </UL>

                  <P>Maintainer(s):</P>

                  <UL>

                    <P>Joon Lee, joon.lee@quantum.com_NOSPAM

                  </UL>

                  <P>Author(s):</P>

                  <UL>

                    <P>Joon Lee, joon.lee@quantum.com_NOSPAM

                  </UL>

                  <P>Mailing-list:</P>

                  <UL>

                    <P><A HREF="mailto:cores@opencores.org_NOSPAM">cores@opencores.org_NOSPAM</A>

                    <A HREF="mailto:cores@opencores.org_NOSPAM"></UL></A>

                  </UL>

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