Subversion Repositories sdram

                  Project

                  Name: Synchronous-DRAM Controller

                  
Description

                  
The Synchronous-DRAM controller core allows any asynchronous

                  bus masters, such as most Intel microcontroller and x86 processors,

                  to effortlessly interface to a large capacity SDRAM. By default

                  the core is configured to work with 2-bank x 512-Word x 16-bit

                  SDRAMs such as NEC uPD451616A, Samsung KM416S1120D, OKIMSM56V16160D.

                  Easy modifications allows the core to work with different capacity

                  SDRAMs. Most of the critical parameters are defines in a global

                  include file allowing easy reconfigurability of the core.

                  
The core handles much of the low level functions such as address

                  demultiplexing, refresh generation and busy status generation.

                  In addtion, the non-trivial powerup initialization sequence is

                  also handled transparently to the host. Flexible refresh generation

                  permits burst refresh, normal refresh or everything in between.

                  The SDRAM mode-register can also be reprogrammed on the fly by

                  the host, although the core uses a default value upon powerup.

                  
The core also includes a set of synthesiable "test"

                  modules. When enabled for compilation, these test modules becomes

                  a host to the SDRAM controller and issues a series of read/write

                  test sequences to the SDRAM. This allows designers working on

                  FPGA/CPLD platforms to turn the SDRAM controller core into a

                  "stand-alone" SDRAM tester. 

                  
The core has been sucessfully tested with a Samsung KM416S1120D

                  SDRAM on Altera Flex10K20 FPGA and :Lattice isp3256 CPLD devices

                  (using the built-in tester).

                  
Picture 1: Interfacing block diagram

                  
Current Status:

                    
Initial release available in CVS for download.

                    
Working on the specification documentation.

                    Preliminary document (726 KB) is available in Adobe PDF format.

                  
Maintainer(s):

                    
Joon Lee, joon.lee@quantum.com_NOSPAM

                  
Author(s):

                    
Joon Lee, joon.lee@quantum.com_NOSPAM

                  
Mailing-list:

                    
cores@opencores.org_NOSPAM