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1 4 lynn0p 
/****************************************************************************************
2 
*
3 
*    File Name:  ddr.v
4 
*      Version:  6.00
5 
*        Model:  BUS Functional
6 
*
7 
* Dependencies:  ddr_parameters.v
8 
*
9 
*  Description:  Micron SDRAM DDR (Double Data Rate)
10 
*
11 
*   Limitation:  - Doesn't check for 8K-cycle refresh.
12 
*                - Doesn't check power-down entry/exit
13 
*                - Doesn't check self-refresh entry/exit.
14 
*
15 
*         Note:  - Set simulator resolution to "ps" accuracy
16 
*                - Set DEBUG = 0 to disable $display messages
17 
*                - Model assume Clk and Clk# crossing at both edge
18 
*
19 
*   Disclaimer   This software code and all associated documentation, comments or other
20 
*  of Warranty:  information (collectively "Software") is provided "AS IS" without
21 
*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
22 
*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
23 
*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
24 
*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
25 
*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
26 
*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
27 
*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
28 
*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
29 
*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
30 
*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
31 
*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
32 
*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
33 
*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
34 
*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
35 
*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
36 
*                DAMAGES. Because some jurisdictions prohibit the exclusion or
37 
*                limitation of liability for consequential or incidental damages, the
38 
*                above limitation may not apply to you.
39 
*
40 
*                Copyright 2003 Micron Technology, Inc. All rights reserved.
41 
*
42 
* Rev  Author Date        Changes
43 
* ---  ------ ----------  ---------------------------------------
44 
* 2.1   SPH    03/19/2002  - Second Release
45 
*                          - Fix tWR and several incompatability
46 
*                            between different simulators
47 
* 3.0   TFK    02/18/2003  - Added tDSS and tDSH timing checks.
48 
*                          - Added tDQSH and tDQSL timing checks.
49 
* 3.1   CAH    05/28/2003  - update all models to release version 3.1
50 
*                            (no changes to this model)
51 
* 3.2   JMK    06/16/2003  - updated all DDR400 models to support CAS Latency 3
52 
* 3.3   JMK    09/11/2003  - Added initialization sequence checks.
53 
* 4.0   JMK    12/01/2003  - Grouped parameters into "ddr_parameters.v"
54 
*                          - Fixed tWTR check
55 
* 4.1   JMK    01/14/2004  - Grouped specify parameters by speed grade
56 
*                          - Fixed mem_sizes parameter
57 
* 4.2   JMK    03/19/2004  - Fixed pulse width checking on Dqs
58 
* 4.3   JMK    04/27/2004  - Changed BL wire size in tb module
59 
*                          - Changed Dq_buf size to [15:0]
60 
* 5.0   JMK    06/16/2004  - Added read to write checking.
61 
*                          - Added read with precharge truncation to write checking.
62 
*                          - Added associative memory array to reduce memory consumption.
63 
*                          - Added checking for required DQS edges during write.
64 
* 5.1   JMK    08/16/2004  - Fixed checking for required DQS edges during write.
65 
*                          - Fixed wdqs_valid window.
66 
* 5.2   JMK    09/24/2004  - Read or Write without activate will be ignored.
67 
* 5.3   JMK    10/27/2004  - Added tMRD checking during Auto Refresh and Activate.
68 
*                          - Added tRFC checking during Load Mode and Precharge.
69 
* 5.4   JMK    12/13/2004  - The model will not respond to illegal command sequences.
70 
* 5.5   SPH    01/13/2005  - The model will issue a halt on illegal command sequences.
71 
*       JMK    02/11/2005  - Changed the display format for numbers to hex.
72 
* 5.6   JMK    04/22/2005  - Fixed Write with auto precharge calculation.
73 
* 5.7   JMK    08/05/2005  - Changed conditions for read with precharge truncation error.
74 
*                          - Renamed parameters file with .vh extension.
75 
* 5.8   BAS    12/26/2006  - Added parameters for T46A part - 256Mb
76 
*                          - Added x32 functionality
77 
* 6.00  JMK    05/31/2007  - Added ddr_184_dimm module model
78 
* 6.00  BAS    05/31/2007  - Updated 128Mb, 256Mb, 512Mb, and 1024Mb parameter sheets
79 
****************************************************************************************/
80 
`define sg6T
81 
`define x16
82 
 
83 
// DO NOT CHANGE THE TIMESCALE
84 
// MAKE SURE YOUR SIMULATOR USE "PS" RESOLUTION
85 
`timescale 1ns / 1ps
86 
 
87 
module ddr (Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Ba , Addr, Dm, Dq, Dqs);
88 
    `include "ddr_parameters.vh"
89 
 
90 
    // Port Declarations
91 
    input                         Clk;
92 
    input                         Clk_n;
93 
    input                         Cke;
94 
    input                         Cs_n;
95 
    input                         Ras_n;
96 
    input                         Cas_n;
97 
    input                         We_n;
98 
    input                 [1 : 0] Ba;
99 
    input     [ADDR_BITS - 1 : 0] Addr;
100 
    input       [DM_BITS - 1 : 0] Dm;
101 
    inout       [DQ_BITS - 1 : 0] Dq;
102 
    inout      [DQS_BITS - 1 : 0] Dqs;
103 
 
104 
    // Internal Wires (fixed width)
105 
    wire                 [31 : 0] Dq_in;
106 
    wire                  [3 : 0] Dqs_in;
107 
    wire                  [3 : 0] Dm_in;
108 
 
109 
    assign Dq_in   [DQ_BITS - 1 : 0] = Dq;
110 
    assign Dqs_in [DQS_BITS - 1 : 0] = Dqs;
111 
    assign Dm_in   [DM_BITS - 1 : 0] = Dm;
112 
 
113 
    // Data pair
114 
    reg                  [31 : 0] dq_rise;
115 
    reg                   [3 : 0] dm_rise;
116 
    reg                  [31 : 0] dq_fall;
117 
    reg                   [3 : 0] dm_fall;
118 
    reg                   [7 : 0] dm_pair;
119 
    reg                  [31 : 0] Dq_buf;
120 
 
121 
    // Mode Register
122 
    reg       [ADDR_BITS - 1 : 0] Mode_reg;
123 
 
124 
    // Internal System Clock
125 
    reg                           CkeZ, Sys_clk;
126 
 
127 
    // Internal Dqs initialize
128 
    reg                           Dqs_int;
129 
 
130 
    // Dqs buffer
131 
    reg        [DQS_BITS - 1 : 0] Dqs_out;
132 
 
133 
    // Dq buffer
134 
    reg         [DQ_BITS - 1 : 0] Dq_out;
135 
 
136 
    // Read pipeline variables
137 
    reg                           Read_cmnd [0 : 6];
138 
    reg                   [1 : 0] Read_bank [0 : 6];
139 
    reg        [COL_BITS - 1 : 0] Read_cols [0 : 6];
140 
 
141 
    // Write pipeline variables
142 
    reg                           Write_cmnd [0 : 3];
143 
    reg                   [1 : 0] Write_bank [0 : 3];
144 
    reg        [COL_BITS - 1 : 0] Write_cols [0 : 3];
145 
 
146 
    // Auto precharge variables
147 
    reg                           Read_precharge  [0 : 3];
148 
    reg                           Write_precharge [0 : 3];
149 
    integer                       Count_precharge [0 : 3];
150 
 
151 
    // Manual precharge variables
152 
    reg                           A10_precharge  [0 : 6];
153 
    reg                   [1 : 0] Bank_precharge [0 : 6];
154 
    reg                           Cmnd_precharge [0 : 6];
155 
 
156 
    // Burst terminate variables
157 
    reg                           Cmnd_bst [0 : 6];
158 
 
159 
    // Memory Banks
160 
`ifdef FULL_MEM
161 
    reg         [DQ_BITS - 1 : 0] mem_array  [0 : (1<<full_mem_bits)-1];
162 
`else
163 
    reg         [DQ_BITS - 1 : 0] mem_array  [0 : (1<<part_mem_bits)-1];
164 
    reg   [full_mem_bits - 1 : 0] addr_array [0 : (1<<part_mem_bits)-1];
165 
    reg   [part_mem_bits     : 0] mem_used;
166 
    initial mem_used = 0;
167 
`endif
168 
 
169 
    // Dqs edge checking
170 
    integer i;
171 
    reg  [3 :0] expect_pos_dqs;
172 
    reg  [3 :0] expect_neg_dqs;
173 
 
174 
    // Burst counter
175 
    reg        [COL_BITS - 1 : 0] Burst_counter;
176 
 
177 
    // Precharge variables
178 
    reg                           Pc_b0, Pc_b1, Pc_b2, Pc_b3;
179 
 
180 
    // Activate variables
181 
    reg                           Act_b0, Act_b1, Act_b2, Act_b3;
182 
 
183 
    // Data IO variables
184 
    reg                           Data_in_enable;
185 
    reg                           Data_out_enable;
186 
 
187 
    // Internal address mux variables
188 
    reg                   [1 : 0] Prev_bank;
189 
    reg                   [1 : 0] Bank_addr;
190 
    reg        [COL_BITS - 1 : 0] Cols_addr, Cols_brst, Cols_temp;
191 
    reg       [ADDR_BITS - 1 : 0] Rows_addr;
192 
    reg       [ADDR_BITS - 1 : 0] B0_row_addr;
193 
    reg       [ADDR_BITS - 1 : 0] B1_row_addr;
194 
    reg       [ADDR_BITS - 1 : 0] B2_row_addr;
195 
    reg       [ADDR_BITS - 1 : 0] B3_row_addr;
196 
 
197 
    // DLL Reset variable
198 
    reg                           DLL_enable;
199 
    reg                           DLL_reset;
200 
    reg                           DLL_done;
201 
    integer                       DLL_count;
202 
    integer                       aref_count;
203 
    integer                       Prech_count;
204 
    reg                           power_up_done;
205 
 
206 
    // Write DQS for tDSS, tDSH, tDQSH, tDQSL checks
207 
    wire      wdqs_valid = Write_cmnd[2] || Write_cmnd[1] || Data_in_enable;
208 
 
209 
    // Commands Decode
210 
    wire      Active_enable   = ~Cs_n & ~Ras_n &  Cas_n &  We_n;
211 
    wire      Aref_enable     = ~Cs_n & ~Ras_n & ~Cas_n &  We_n;
212 
    wire      Burst_term      = ~Cs_n &  Ras_n &  Cas_n & ~We_n;
213 
    wire      Ext_mode_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n &  Ba[0] & ~Ba[1];
214 
    wire      Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n & ~Ba[0] & ~Ba[1];
215 
    wire      Prech_enable    = ~Cs_n & ~Ras_n &  Cas_n & ~We_n;
216 
    wire      Read_enable     = ~Cs_n &  Ras_n & ~Cas_n &  We_n;
217 
    wire      Write_enable    = ~Cs_n &  Ras_n & ~Cas_n & ~We_n;
218 
 
219 
    // Burst Length Decode
220 
    wire [3:0] burst_length = 1 << (Mode_reg[2:0]);
221 
    reg  [3:0] read_precharge_truncation;
222 
 
223 
    // CAS Latency Decode
224 
    wire [2:0] cas_latency_x2 = (Mode_reg[6:4] === 3'o6) ? 5 : 2*Mode_reg[6:4];
225 
 
226 
    // DQS Buffer
227 
    assign    Dqs = Dqs_out;
228 
 
229 
    // DQ Buffer
230 
    assign    Dq  = Dq_out;
231 
 
232 
    // Timing Check
233 
    time      MRD_chk;
234 
    time      RFC_chk;
235 
    time      RRD_chk;
236 
    time      RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
237 
    time      RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3;
238 
    time      RC_chk0, RC_chk1, RC_chk2, RC_chk3;
239 
    time      RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
240 
    time      RP_chk0, RP_chk1, RP_chk2, RP_chk3;
241 
    time      WR_chk0, WR_chk1, WR_chk2, WR_chk3;
242 
 
243 
    initial begin
244 
        CkeZ = 1'b0;
245 
        Sys_clk = 1'b0;
246 
        {Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000;
247 
        {Act_b0, Act_b1, Act_b2, Act_b3} = 4'b1111;
248 
        Dqs_int = 1'b0;
249 
        Dqs_out = {DQS_BITS{1'bz}};
250 
        Dq_out = {DQ_BITS{1'bz}};
251 
        Data_in_enable = 1'b0;
252 
        Data_out_enable = 1'b0;
253 
        DLL_enable = 1'b0;
254 
        DLL_reset = 1'b0;
255 
        DLL_done = 1'b0;
256 
        DLL_count = 0;
257 
        aref_count = 0;
258 
        Prech_count = 0;
259 
        power_up_done = 0;
260 
        MRD_chk = 0;
261 
        RFC_chk = 0;
262 
        RRD_chk = 0;
263 
        {RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3} = 0;
264 
        {RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3} = 0;
265 
        {RC_chk0, RC_chk1, RC_chk2, RC_chk3} = 0;
266 
        {RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3} = 0;
267 
        {RP_chk0, RP_chk1, RP_chk2, RP_chk3} = 0;
268 
        {WR_chk0, WR_chk1, WR_chk2, WR_chk3} = 0;
269 
        $timeformat (-9, 3, " ns", 12);
270 
    end
271 
 
272 
    // System Clock
273 
    always begin
274 
        @ (posedge Clk) begin
275 
            Sys_clk = CkeZ;
276 
            CkeZ = Cke;
277 
        end
278 
        @ (negedge Clk) begin
279 
            Sys_clk = 1'b0;
280 
        end
281 
    end
282 
 
283 
    // Check to make sure that we have a Deselect or NOP command on the bus when CKE is brought high
284 
    always @(Cke) begin
285 
        if (Cke === 1'b1) begin
286 
            if (!((Cs_n) || (~Cs_n &  Ras_n & Cas_n &  We_n))) begin
287 
                $display ("%m: at time %t MEMORY ERROR:  You must have a Deselect or NOP command applied", $time);
288 
                $display ("%m:           when the Clock Enable is brought High.");
289 
            end
290 
        end
291 
    end
292 
 
293 
    // Check the initialization sequence
294 
    initial begin
295 
        @ (posedge Cke) begin
296 
            @ (posedge DLL_enable) begin
297 
                aref_count = 0;
298 
                @ (posedge DLL_reset) begin
299 
                    @ (Prech_count) begin
300 
                        if (aref_count >= 2) begin
301 
                            if (DEBUG) $display ("%m: at time %t MEMORY:  Power Up and Initialization Sequence is complete", $time);
302 
                            power_up_done = 1;
303 
                        end else begin
304 
                            aref_count = 0;
305 
                            @ (aref_count >= 2) begin
306 
                                if (DEBUG) $display ("%m: at time %t MEMORY:  Power Up and Initialization Sequence is complete", $time);
307 
                                power_up_done = 1;
308 
                            end
309 
                        end
310 
                    end
311 
                end
312 
            end
313 
        end
314 
    end
315 
 
316 
    // Write Memory
317 
    task write_mem;
318 
        input [full_mem_bits - 1 : 0] addr;
319 
        input       [DQ_BITS - 1 : 0] data;
320 
        reg       [part_mem_bits : 0] i;
321 
        begin
322 
`ifdef FULL_MEM
323 
            mem_array[addr] = data;
324 
`else
325 
            begin : loop
326 
                for (i = 0; i < mem_used; i = i + 1) begin
327 
                    if (addr_array[i] === addr) begin
328 
                        disable loop;
329 
                    end
330 
                end
331 
            end
332 
            if (i === mem_used) begin
333 
                if (i === (1<<part_mem_bits)) begin
334 
                    $display ("At time %t ERROR: Memory overflow.\n  Write to Address %h with Data %h will be lost.\n  You must increase the part_mem_bits parameter or `define FULL_MEM.", $time, addr, data);
335 
                end else begin
336 
                    mem_used = mem_used + 1;
337 
                    addr_array[i] = addr;
338 
                end
339 
            end
340 
            mem_array[i] = data;
341 
`endif
342 
        end
343 
    endtask
344 
 
345 
    // Read Memory
346 
    task read_mem;
347 
        input [full_mem_bits - 1 : 0] addr;
348 
        output      [DQ_BITS - 1 : 0] data;
349 
        reg       [part_mem_bits : 0] i;
350 
        begin
351 
`ifdef FULL_MEM
352 
            data = mem_array[addr];
353 
`else
354 
            begin : loop
355 
                for (i = 0; i < mem_used; i = i + 1) begin
356 
                    if (addr_array[i] === addr) begin
357 
                        disable loop;
358 
                    end
359 
                end
360 
            end
361 
            if (i <= mem_used) begin
362 
                data = mem_array[i];
363 
            end
364 
`endif
365 
        end
366 
    endtask
367 
 
368 
    // Burst Decode
369 
    task Burst_Decode;
370 
    begin
371 
 
372 
        // Advance Burst Counter
373 
        if (Burst_counter < burst_length) begin
374 
            Burst_counter = Burst_counter + 1;
375 
        end
376 
 
377 
        // Burst Type
378 
        if (Mode_reg[3] === 1'b0) begin                         // Sequential Burst
379 
            Cols_temp = Cols_addr + 1;
380 
        end else if (Mode_reg[3] === 1'b1) begin                // Interleaved Burst
381 
            Cols_temp[2] =  Burst_counter[2] ^ Cols_brst[2];
382 
            Cols_temp[1] =  Burst_counter[1] ^ Cols_brst[1];
383 
            Cols_temp[0] =  Burst_counter[0] ^ Cols_brst[0];
384 
        end
385 
 
386 
        // Burst Length
387 
        if (burst_length === 2) begin
388 
            Cols_addr [0] = Cols_temp [0];
389 
        end else if (burst_length === 4) begin
390 
            Cols_addr [1 : 0] = Cols_temp [1 : 0];
391 
        end else if (burst_length === 8) begin
392 
            Cols_addr [2 : 0] = Cols_temp [2 : 0];
393 
        end else begin
394 
            Cols_addr = Cols_temp;
395 
        end
396 
 
397 
        // Data Counter
398 
        if (Burst_counter >= burst_length) begin
399 
            Data_in_enable = 1'b0;
400 
            Data_out_enable = 1'b0;
401 
            read_precharge_truncation = 4'h0;
402 
        end
403 
 
404 
    end
405 
    endtask
406 
 
407 
    // Manual Precharge Pipeline
408 
    task Manual_Precharge_Pipeline;
409 
    begin
410 
        // A10 Precharge Pipeline
411 
        A10_precharge[0] = A10_precharge[1];
412 
        A10_precharge[1] = A10_precharge[2];
413 
        A10_precharge[2] = A10_precharge[3];
414 
        A10_precharge[3] = A10_precharge[4];
415 
        A10_precharge[4] = A10_precharge[5];
416 
        A10_precharge[5] = A10_precharge[6];
417 
        A10_precharge[6] = 1'b0;
418 
 
419 
        // Bank Precharge Pipeline
420 
        Bank_precharge[0] = Bank_precharge[1];
421 
        Bank_precharge[1] = Bank_precharge[2];
422 
        Bank_precharge[2] = Bank_precharge[3];
423 
        Bank_precharge[3] = Bank_precharge[4];
424 
        Bank_precharge[4] = Bank_precharge[5];
425 
        Bank_precharge[5] = Bank_precharge[6];
426 
        Bank_precharge[6] = 2'b0;
427 
 
428 
        // Command Precharge Pipeline
429 
        Cmnd_precharge[0] = Cmnd_precharge[1];
430 
        Cmnd_precharge[1] = Cmnd_precharge[2];
431 
        Cmnd_precharge[2] = Cmnd_precharge[3];
432 
        Cmnd_precharge[3] = Cmnd_precharge[4];
433 
        Cmnd_precharge[4] = Cmnd_precharge[5];
434 
        Cmnd_precharge[5] = Cmnd_precharge[6];
435 
        Cmnd_precharge[6] = 1'b0;
436 
 
437 
        // Terminate a Read if same bank or all banks
438 
        if (Cmnd_precharge[0] === 1'b1) begin
439 
            if (Bank_precharge[0] === Bank_addr || A10_precharge[0] === 1'b1) begin
440 
                if (Data_out_enable === 1'b1) begin
441 
                    Data_out_enable = 1'b0;
442 
                    read_precharge_truncation = 4'hF;
443 
                end
444 
            end
445 
        end
446 
    end
447 
    endtask
448 
 
449 
    // Burst Terminate Pipeline
450 
    task Burst_Terminate_Pipeline;
451 
    begin
452 
        // Command Precharge Pipeline
453 
        Cmnd_bst[0] = Cmnd_bst[1];
454 
        Cmnd_bst[1] = Cmnd_bst[2];
455 
        Cmnd_bst[2] = Cmnd_bst[3];
456 
        Cmnd_bst[3] = Cmnd_bst[4];
457 
        Cmnd_bst[4] = Cmnd_bst[5];
458 
        Cmnd_bst[5] = Cmnd_bst[6];
459 
        Cmnd_bst[6] = 1'b0;
460 
 
461 
        // Terminate a Read regardless of banks
462 
        if (Cmnd_bst[0] === 1'b1 && Data_out_enable === 1'b1) begin
463 
            Data_out_enable = 1'b0;
464 
        end
465 
    end
466 
    endtask
467 
 
468 
    // Dq and Dqs Drivers
469 
    task Dq_Dqs_Drivers;
470 
    begin
471 
        // read command pipeline
472 
        Read_cmnd [0] = Read_cmnd [1];
473 
        Read_cmnd [1] = Read_cmnd [2];
474 
        Read_cmnd [2] = Read_cmnd [3];
475 
        Read_cmnd [3] = Read_cmnd [4];
476 
        Read_cmnd [4] = Read_cmnd [5];
477 
        Read_cmnd [5] = Read_cmnd [6];
478 
        Read_cmnd [6] = 1'b0;
479 
 
480 
        // read bank pipeline
481 
        Read_bank [0] = Read_bank [1];
482 
        Read_bank [1] = Read_bank [2];
483 
        Read_bank [2] = Read_bank [3];
484 
        Read_bank [3] = Read_bank [4];
485 
        Read_bank [4] = Read_bank [5];
486 
        Read_bank [5] = Read_bank [6];
487 
        Read_bank [6] = 2'b0;
488 
 
489 
        // read column pipeline
490 
        Read_cols [0] = Read_cols [1];
491 
        Read_cols [1] = Read_cols [2];
492 
        Read_cols [2] = Read_cols [3];
493 
        Read_cols [3] = Read_cols [4];
494 
        Read_cols [4] = Read_cols [5];
495 
        Read_cols [5] = Read_cols [6];
496 
        Read_cols [6] = 0;
497 
 
498 
        // Initialize Read command
499 
        if (Read_cmnd [0] === 1'b1) begin
500 
            Data_out_enable = 1'b1;
501 
            Bank_addr = Read_bank [0];
502 
            Cols_addr = Read_cols [0];
503 
            Cols_brst = Cols_addr [2 : 0];
504 
            Burst_counter = 0;
505 
 
506 
            // Row Address Mux
507 
            case (Bank_addr)
508 
                2'd0    : Rows_addr = B0_row_addr;
509 
                2'd1    : Rows_addr = B1_row_addr;
510 
                2'd2    : Rows_addr = B2_row_addr;
511 
                2'd3    : Rows_addr = B3_row_addr;
512 
                default : $display ("At time %t ERROR: Invalid Bank Address", $time);
513 
            endcase
514 
        end
515 
 
516 
        // Toggle Dqs during Read command
517 
        if (Data_out_enable === 1'b1) begin
518 
            Dqs_int = 1'b0;
519 
            if (Dqs_out === {DQS_BITS{1'b0}}) begin
520 
                Dqs_out = {DQS_BITS{1'b1}};
521 
            end else if (Dqs_out === {DQS_BITS{1'b1}}) begin
522 
                Dqs_out = {DQS_BITS{1'b0}};
523 
            end else begin
524 
                Dqs_out = {DQS_BITS{1'b0}};
525 
            end
526 
        end else if (Data_out_enable === 1'b0 && Dqs_int === 1'b0) begin
527 
            Dqs_out = {DQS_BITS{1'bz}};
528 
        end
529 
 
530 
        // Initialize dqs for Read command
531 
        if (Read_cmnd [2] === 1'b1) begin
532 
            if (Data_out_enable === 1'b0) begin
533 
                Dqs_int = 1'b1;
534 
                Dqs_out = {DQS_BITS{1'b0}};
535 
            end
536 
        end
537 
 
538 
        // Read latch
539 
        if (Data_out_enable === 1'b1) begin
540 
            // output data
541 
            read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_out);
542 
            if (DEBUG) begin
543 
                $display ("At time %t READ : Bank = %h, Row = %h, Col = %h, Data = %h", $time, Bank_addr, Rows_addr, Cols_addr, Dq_out);
544 
            end
545 
        end else begin
546 
            Dq_out = {DQ_BITS{1'bz}};
547 
        end
548 
    end
549 
    endtask
550 
 
551 
    // Write FIFO and DM Mask Logic
552 
    task Write_FIFO_DM_Mask_Logic;
553 
    begin
554 
        // Write command pipeline
555 
        Write_cmnd [0] = Write_cmnd [1];
556 
        Write_cmnd [1] = Write_cmnd [2];
557 
        Write_cmnd [2] = Write_cmnd [3];
558 
        Write_cmnd [3] = 1'b0;
559 
 
560 
        // Write command pipeline
561 
        Write_bank [0] = Write_bank [1];
562 
        Write_bank [1] = Write_bank [2];
563 
        Write_bank [2] = Write_bank [3];
564 
        Write_bank [3] = 2'b0;
565 
 
566 
        // Write column pipeline
567 
        Write_cols [0] = Write_cols [1];
568 
        Write_cols [1] = Write_cols [2];
569 
        Write_cols [2] = Write_cols [3];
570 
        Write_cols [3] = {COL_BITS{1'b0}};
571 
 
572 
        // Initialize Write command
573 
        if (Write_cmnd [0] === 1'b1) begin
574 
            Data_in_enable = 1'b1;
575 
            Bank_addr = Write_bank [0];
576 
            Cols_addr = Write_cols [0];
577 
            Cols_brst = Cols_addr [2 : 0];
578 
            Burst_counter = 0;
579 
 
580 
            // Row address mux
581 
            case (Bank_addr)
582 
                2'd0    : Rows_addr = B0_row_addr;
583 
                2'd1    : Rows_addr = B1_row_addr;
584 
                2'd2    : Rows_addr = B2_row_addr;
585 
                2'd3    : Rows_addr = B3_row_addr;
586 
                default : $display ("At time %t ERROR: Invalid Row Address", $time);
587 
            endcase
588 
        end
589 
 
590 
        // Write data
591 
        if (Data_in_enable === 1'b1) begin
592 
 
593 
            // Data Buffer
594 
            read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf);
595 
 
596 
            // write negedge Dqs on posedge Sys_clk
597 
            if (Sys_clk) begin
598 
                if (!dm_fall[0]) begin
599 
                    Dq_buf [ 7 : 0] = dq_fall [ 7 : 0];
600 
                end
601 
                if (!dm_fall[1]) begin
602 
                    Dq_buf [15 : 8] = dq_fall [15 : 8];
603 
                end
604 
                if (!dm_fall[2]) begin
605 
                    Dq_buf [23 : 16] = dq_fall [23 : 16];
606 
                end
607 
                if (!dm_fall[3]) begin
608 
                    Dq_buf [31 : 24] = dq_fall [31 : 24];
609 
                end
610 
                if (~&dm_fall) begin
611 
                    if (DEBUG) begin
612 
                        $display ("At time %t WRITE: Bank = %h, Row = %h, Col = %h, Data = %h", $time, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]);
613 
                    end
614 
                end
615 
            // write posedge Dqs on negedge Sys_clk
616 
            end else begin
617 
                if (!dm_rise[0]) begin
618 
                    Dq_buf [ 7 : 0] = dq_rise [ 7 : 0];
619 
                end
620 
                if (!dm_rise[1]) begin
621 
                    Dq_buf [15 : 8] = dq_rise [15 : 8];
622 
                end
623 
                if (!dm_rise[2]) begin
624 
                    Dq_buf [23 : 16] = dq_rise [23 : 16];
625 
                end
626 
                if (!dm_rise[3]) begin
627 
                    Dq_buf [31 : 24] = dq_rise [31 : 24];
628 
                end
629 
                if (~&dm_rise) begin
630 
                    if (DEBUG) begin
631 
                        $display ("At time %t WRITE: Bank = %h, Row = %h, Col = %h, Data = %h", $time, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]);
632 
                    end
633 
                end
634 
            end
635 
 
636 
            // Write Data
637 
            write_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf);
638 
 
639 
            // tWR start and tWTR check
640 
            if (Sys_clk && &dm_pair === 1'b0)  begin
641 
                case (Bank_addr)
642 
                    2'd0    : WR_chk0 = $time;
643 
                    2'd1    : WR_chk1 = $time;
644 
                    2'd2    : WR_chk2 = $time;
645 
                    2'd3    : WR_chk3 = $time;
646 
                    default : $display ("At time %t ERROR: Invalid Bank Address (tWR)", $time);
647 
                endcase
648 
 
649 
                // tWTR check
650 
                if (Read_enable === 1'b1) begin
651 
                    $display ("At time %t ERROR: tWTR violation during Read", $time);
652 
                end
653 
            end
654 
        end
655 
    end
656 
    endtask
657 
 
658 
    // Auto Precharge Calculation
659 
    task Auto_Precharge_Calculation;
660 
    begin
661 
        // Precharge counter
662 
        if (Read_precharge [0] === 1'b1 || Write_precharge [0] === 1'b1) begin
663 
            Count_precharge [0] = Count_precharge [0] + 1;
664 
        end
665 
        if (Read_precharge [1] === 1'b1 || Write_precharge [1] === 1'b1) begin
666 
            Count_precharge [1] = Count_precharge [1] + 1;
667 
        end
668 
        if (Read_precharge [2] === 1'b1 || Write_precharge [2] === 1'b1) begin
669 
            Count_precharge [2] = Count_precharge [2] + 1;
670 
        end
671 
        if (Read_precharge [3] === 1'b1 || Write_precharge [3] === 1'b1) begin
672 
            Count_precharge [3] = Count_precharge [3] + 1;
673 
        end
674 
 
675 
        // Read with AutoPrecharge Calculation
676 
        //      The device start internal precharge when:
677 
        //          1.  Meet tRAS requirement
678 
        //          2.  BL/2 cycles after command
679 
        if ((Read_precharge[0] === 1'b1) && ($time - RAS_chk0 >= tRAS)) begin
680 
            if (Count_precharge[0] >= burst_length/2) begin
681 
                Pc_b0 = 1'b1;
682 
                Act_b0 = 1'b0;
683 
                RP_chk0 = $time;
684 
                Read_precharge[0] = 1'b0;
685 
            end
686 
        end
687 
        if ((Read_precharge[1] === 1'b1) && ($time - RAS_chk1 >= tRAS)) begin
688 
            if (Count_precharge[1] >= burst_length/2) begin
689 
                Pc_b1 = 1'b1;
690 
                Act_b1 = 1'b0;
691 
                RP_chk1 = $time;
692 
                Read_precharge[1] = 1'b0;
693 
            end
694 
        end
695 
        if ((Read_precharge[2] === 1'b1) && ($time - RAS_chk2 >= tRAS)) begin
696 
            if (Count_precharge[2] >= burst_length/2) begin
697 
                Pc_b2 = 1'b1;
698 
                Act_b2 = 1'b0;
699 
                RP_chk2 = $time;
700 
                Read_precharge[2] = 1'b0;
701 
            end
702 
        end
703 
        if ((Read_precharge[3] === 1'b1) && ($time - RAS_chk3 >= tRAS)) begin
704 
            if (Count_precharge[3] >= burst_length/2) begin
705 
                Pc_b3 = 1'b1;
706 
                Act_b3 = 1'b0;
707 
                RP_chk3 = $time;
708 
                Read_precharge[3] = 1'b0;
709 
            end
710 
        end
711 
 
712 
        // Write with AutoPrecharge Calculation
713 
        //      The device start internal precharge when:
714 
        //          1.  Meet tRAS requirement
715 
        //          2.  Write Latency PLUS BL/2 cycles PLUS tWR after Write command
716 
 
717 
        if ((Write_precharge[0] === 1'b1) && ($time - RAS_chk0 >= tRAS)) begin
718 
            if ((Count_precharge[0] >= burst_length/2+1) && ($time - WR_chk0 >= tWR)) begin
719 
                Pc_b0 = 1'b1;
720 
                Act_b0 = 1'b0;
721 
                RP_chk0 = $time;
722 
                Write_precharge[0] = 1'b0;
723 
            end
724 
        end
725 
        if ((Write_precharge[1] === 1'b1) && ($time - RAS_chk1 >= tRAS)) begin
726 
            if ((Count_precharge[1] >= burst_length/2+1) && ($time - WR_chk1 >= tWR)) begin
727 
                Pc_b1 = 1'b1;
728 
                Act_b1 = 1'b0;
729 
                RP_chk1 = $time;
730 
                Write_precharge[1] = 1'b0;
731 
            end
732 
        end
733 
        if ((Write_precharge[2] === 1'b1) && ($time - RAS_chk2 >= tRAS)) begin
734 
            if ((Count_precharge[2] >= burst_length/2+1) && ($time - WR_chk2 >= tWR)) begin
735 
                Pc_b2 = 1'b1;
736 
                Act_b2 = 1'b0;
737 
                RP_chk2 = $time;
738 
                Write_precharge[2] = 1'b0;
739 
            end
740 
        end
741 
        if ((Write_precharge[3] === 1'b1) && ($time - RAS_chk3 >= tRAS)) begin
742 
            if ((Count_precharge[3] >= burst_length/2+1) && ($time - WR_chk3 >= tWR)) begin
743 
                Pc_b3 = 1'b1;
744 
                Act_b3 = 1'b0;
745 
                RP_chk3 = $time;
746 
                Write_precharge[3] = 1'b0;
747 
            end
748 
        end
749 
    end
750 
    endtask
751 
 
752 
    // DLL Counter
753 
    task DLL_Counter;
754 
    begin
755 
        if (DLL_reset === 1'b1 && DLL_done === 1'b0) begin
756 
            DLL_count = DLL_count + 1;
757 
            if (DLL_count >= 200) begin
758 
                DLL_done = 1'b1;
759 
            end
760 
        end
761 
    end
762 
    endtask
763 
 
764 
    // Control Logic
765 
    task Control_Logic;
766 
    begin
767 
        // Auto Refresh
768 
        if (Aref_enable === 1'b1) begin
769 
            // Display DEBUG Message
770 
            if (DEBUG) begin
771 
                $display ("At time %t AREF : Auto Refresh", $time);
772 
            end
773 
 
774 
            // Precharge to Auto Refresh
775 
            if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
776 
                ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
777 
                $display ("At time %t ERROR: tRP violation during Auto Refresh", $time);
778 
            end
779 
 
780 
            // LMR/EMR to Auto Refresh
781 
            if ($time - MRD_chk < tMRD) begin
782 
                $display ("At time %t ERROR: tMRD violation during Auto Refresh", $time);
783 
            end
784 
 
785 
            // Auto Refresh to Auto Refresh
786 
            if ($time - RFC_chk < tRFC) begin
787 
                $display ("At time %t ERROR: tRFC violation during Auto Refresh", $time);
788 
            end
789 
 
790 
            // Precharge to Auto Refresh
791 
            if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
792 
                $display ("At time %t ERROR: All banks must be Precharged before Auto Refresh", $time);
793 
                if (!no_halt) $stop (0);
794 
            end else begin
795 
                aref_count = aref_count + 1;
796 
                RFC_chk = $time;
797 
            end
798 
        end
799 
 
800 
        // Extended Mode Register
801 
        if (Ext_mode_enable === 1'b1) begin
802 
            if (DEBUG) begin
803 
                $display ("At time %t EMR  : Extended Mode Register", $time);
804 
            end
805 
 
806 
            // Precharge to LMR/EMR
807 
            if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
808 
                ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
809 
                $display ("At time %t ERROR: tRP violation during Extended Mode Register", $time);
810 
            end
811 
 
812 
            // LMR/EMR to LMR/EMR
813 
            if ($time - MRD_chk < tMRD) begin
814 
                $display ("At time %t ERROR: tMRD violation during Extended Mode Register", $time);
815 
            end
816 
 
817 
            // Auto Refresh to LMR/EMR
818 
            if ($time - RFC_chk < tRFC) begin
819 
                $display ("At time %t ERROR: tRFC violation during Extended Mode Register", $time);
820 
            end
821 
 
822 
            // Precharge to LMR/EMR
823 
            if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
824 
                $display ("At time %t ERROR: all banks must be Precharged before Extended Mode Register", $time);
825 
                if (!no_halt) $stop (0);
826 
            end else begin
827 
                if (Addr[0] === 1'b0) begin
828 
                    DLL_enable = 1'b1;
829 
                    if (DEBUG) begin
830 
                        $display ("At time %t EMR  : Enable DLL", $time);
831 
                    end
832 
                end else begin
833 
                    DLL_enable = 1'b0;
834 
                    if (DEBUG) begin
835 
                        $display ("At time %t EMR  : Disable DLL", $time);
836 
                    end
837 
                end
838 
                MRD_chk = $time;
839 
            end
840 
        end
841 
 
842 
        // Load Mode Register
843 
        if (Mode_reg_enable === 1'b1) begin
844 
            if (DEBUG) begin
845 
                $display ("At time %t LMR  : Load Mode Register", $time);
846 
            end
847 
 
848 
            // Precharge to LMR/EMR
849 
            if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
850 
                ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
851 
                $display ("At time %t ERROR: tRP violation during Load Mode Register", $time);
852 
            end
853 
 
854 
            // LMR/EMR to LMR/EMR
855 
            if ($time - MRD_chk < tMRD) begin
856 
                $display ("At time %t ERROR: tMRD violation during Load Mode Register", $time);
857 
            end
858 
 
859 
            // Auto Refresh to LMR/EMR
860 
            if ($time - RFC_chk < tRFC) begin
861 
                $display ("At time %t ERROR: tRFC violation during Load Mode Register", $time);
862 
            end
863 
 
864 
            // Precharge to LMR/EMR
865 
            if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
866 
                $display ("At time %t ERROR: all banks must be Precharged before Load Mode Register", $time);
867 
            end else begin
868 
                // Register Mode
869 
                Mode_reg = Addr;
870 
 
871 
                // DLL Reset
872 
                if (DLL_enable === 1'b1 && Addr [8] === 1'b1) begin
873 
                    DLL_reset = 1'b1;
874 
                    DLL_done = 1'b0;
875 
                    DLL_count = 0;
876 
                end else if (DLL_enable === 1'b1 && DLL_reset === 1'b0 && Addr [8] === 1'b0) begin
877 
                    $display ("At time %t ERROR: DLL is ENABLE: DLL RESET is required.", $time);
878 
                end else if (DLL_enable === 1'b0 && Addr [8] === 1'b1) begin
879 
                    $display ("At time %t ERROR: DLL is DISABLE: DLL RESET will be ignored.", $time);
880 
                end
881 
 
882 
                // Burst Length
883 
                case (Addr [2 : 0])
884 
                    3'b001  : $display ("At time %t LMR  : Burst Length = 2", $time);
885 
                    3'b010  : $display ("At time %t LMR  : Burst Length = 4", $time);
886 
                    3'b011  : $display ("At time %t LMR  : Burst Length = 8", $time);
887 
                    default : $display ("At time %t ERROR: Burst Length not supported", $time);
888 
                endcase
889 
 
890 
                // CAS Latency
891 
                case (Addr [6 : 4])
892 
                    3'b010  : $display ("At time %t LMR  : CAS Latency = 2", $time);
893 
                    3'b110  : $display ("At time %t LMR  : CAS Latency = 2.5", $time);
894 
                    3'b011  : $display ("At time %t LMR  : CAS Latency = 3", $time);
895 
                    default : $display ("At time %t ERROR: CAS Latency not supported", $time);
896 
                endcase
897 
 
898 
                // Record current tMRD time
899 
                MRD_chk = $time;
900 
            end
901 
        end
902 
 
903 
        // Activate Block
904 
        if (Active_enable === 1'b1) begin
905 
            if (!(power_up_done)) begin
906 
                $display ("%m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Activate command", $time);
907 
            end
908 
            // Display DEBUG Message
909 
            if (DEBUG) begin
910 
                $display ("At time %t ACT  : Bank = %h, Row = %h", $time, Ba, Addr);
911 
            end
912 
 
913 
            // Activate to Activate (different bank)
914 
            if ((Prev_bank != Ba) && ($time - RRD_chk < tRRD)) begin
915 
                $display ("At time %t ERROR: tRRD violation during Activate bank %h", $time, Ba);
916 
            end
917 
 
918 
            // LMR/EMR to Activate
919 
            if ($time - MRD_chk < tMRD) begin
920 
                $display ("At time %t ERROR: tMRD violation during Activate bank %h", $time, Ba);
921 
            end
922 
 
923 
            // AutoRefresh to Activate
924 
            if ($time - RFC_chk < tRFC) begin
925 
                $display ("At time %t ERROR: tRFC violation during Activate bank %h", $time, Ba);
926 
            end
927 
 
928 
            // Precharge to Activate
929 
            if ((Ba === 2'b00 && Pc_b0  === 1'b0) || (Ba === 2'b01 && Pc_b1  === 1'b0) ||
930 
                (Ba === 2'b10 && Pc_b2  === 1'b0) || (Ba === 2'b11 && Pc_b3  === 1'b0)) begin
931 
                $display ("At time %t ERROR: Bank = %h is already activated - Command Ignored", $time, Ba);
932 
                if (!no_halt) $stop (0);
933 
            end else begin
934 
                // Activate Bank 0
935 
                if (Ba === 2'b00 && Pc_b0 === 1'b1) begin
936 
                    // Activate to Activate (same bank)
937 
                    if ($time - RC_chk0 < tRC) begin
938 
                        $display ("At time %t ERROR: tRC violation during Activate bank %h", $time, Ba);
939 
                    end
940 
 
941 
                    // Precharge to Activate
942 
                    if ($time - RP_chk0 < tRP) begin
943 
                        $display ("At time %t ERROR: tRP violation during Activate bank %h", $time, Ba);
944 
                    end
945 
 
946 
                    // Record variables for checking violation
947 
                    Act_b0 = 1'b1;
948 
                    Pc_b0 = 1'b0;
949 
                    B0_row_addr = Addr;
950 
                    RC_chk0  = $time;
951 
                    RCD_chk0 = $time;
952 
                    RAS_chk0 = $time;
953 
                    RAP_chk0 = $time;
954 
                end
955 
 
956 
                // Activate Bank 1
957 
                if (Ba === 2'b01 && Pc_b1 === 1'b1) begin
958 
                    // Activate to Activate (same bank)
959 
                    if ($time - RC_chk1 < tRC) begin
960 
                        $display ("At time %t ERROR: tRC violation during Activate bank %h", $time, Ba);
961 
                    end
962 
 
963 
                    // Precharge to Activate
964 
                    if ($time - RP_chk1 < tRP) begin
965 
                        $display ("At time %t ERROR: tRP violation during Activate bank %h", $time, Ba);
966 
                    end
967 
 
968 
                    // Record variables for checking violation
969 
                    Act_b1 = 1'b1;
970 
                    Pc_b1 = 1'b0;
971 
                    B1_row_addr = Addr;
972 
                    RC_chk1  = $time;
973 
                    RCD_chk1 = $time;
974 
                    RAS_chk1 = $time;
975 
                    RAP_chk1 = $time;
976 
                end
977 
 
978 
                // Activate Bank 2
979 
                if (Ba === 2'b10 && Pc_b2 === 1'b1) begin
980 
                    // Activate to Activate (same bank)
981 
                    if ($time - RC_chk2 < tRC) begin
982 
                        $display ("At time %t ERROR: tRC violation during Activate bank %h", $time, Ba);
983 
                    end
984 
 
985 
                    // Precharge to Activate
986 
                    if ($time - RP_chk2 < tRP) begin
987 
                        $display ("At time %t ERROR: tRP violation during Activate bank %h", $time, Ba);
988 
                    end
989 
 
990 
                    // Record variables for checking violation
991 
                    Act_b2 = 1'b1;
992 
                    Pc_b2 = 1'b0;
993 
                    B2_row_addr = Addr;
994 
                    RC_chk2  = $time;
995 
                    RCD_chk2 = $time;
996 
                    RAS_chk2 = $time;
997 
                    RAP_chk2 = $time;
998 
                end
999 
 
1000 
                // Activate Bank 3
1001 
                if (Ba === 2'b11 && Pc_b3 === 1'b1) begin
1002 
                    // Activate to Activate (same bank)
1003 
                    if ($time - RC_chk3 < tRC) begin
1004 
                        $display ("At time %t ERROR: tRC violation during Activate bank %h", $time, Ba);
1005 
                    end
1006 
 
1007 
                    // Precharge to Activate
1008 
                    if ($time - RP_chk3 < tRP) begin
1009 
                        $display ("At time %t ERROR: tRP violation during Activate bank %h", $time, Ba);
1010 
                    end
1011 
 
1012 
                    // Record variables for checking violation
1013 
                    Act_b3 = 1'b1;
1014 
                    Pc_b3 = 1'b0;
1015 
                    B3_row_addr = Addr;
1016 
                    RC_chk3  = $time;
1017 
                    RCD_chk3 = $time;
1018 
                    RAS_chk3 = $time;
1019 
                    RAP_chk3 = $time;
1020 
                end
1021 
                // Record variable for checking violation
1022 
                RRD_chk = $time;
1023 
                Prev_bank = Ba;
1024 
                read_precharge_truncation[Ba] = 1'b0;
1025 
            end
1026 
        end
1027 
 
1028 
        // Precharge Block - consider NOP if bank already precharged or in process of precharging
1029 
        if (Prech_enable === 1'b1) begin
1030 
            // Display DEBUG Message
1031 
            if (DEBUG) begin
1032 
                $display ("At time %t PRE  : Addr[10] = %b, Bank = %b", $time, Addr[10], Ba);
1033 
            end
1034 
 
1035 
            // LMR/EMR to Precharge
1036 
            if ($time - MRD_chk < tMRD) begin
1037 
                $display ("At time %t ERROR: tMRD violation during Precharge", $time);
1038 
            end
1039 
 
1040 
            // AutoRefresh to Precharge
1041 
            if ($time - RFC_chk < tRFC) begin
1042 
                $display ("At time %t ERROR: tRFC violation during Precharge", $time);
1043 
            end
1044 
 
1045 
            // Precharge bank 0
1046 
            if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b00)) && Act_b0 === 1'b1) begin
1047 
                Act_b0 = 1'b0;
1048 
                Pc_b0 = 1'b1;
1049 
                RP_chk0 = $time;
1050 
 
1051 
                // Activate to Precharge Bank
1052 
                if ($time - RAS_chk0 < tRAS) begin
1053 
                    $display ("At time %t ERROR: tRAS violation during Precharge", $time);
1054 
                end
1055 
 
1056 
                // tWR violation check for Write
1057 
                if ($time - WR_chk0 < tWR) begin
1058 
                    $display ("At time %t ERROR: tWR violation during Precharge", $time);
1059 
                end
1060 
            end
1061 
 
1062 
            // Precharge bank 1
1063 
            if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b01)) && Act_b1 === 1'b1) begin
1064 
                Act_b1 = 1'b0;
1065 
                Pc_b1 = 1'b1;
1066 
                RP_chk1 = $time;
1067 
 
1068 
                // Activate to Precharge Bank 1
1069 
                if ($time - RAS_chk1 < tRAS) begin
1070 
                    $display ("At time %t ERROR: tRAS violation during Precharge", $time);
1071 
                end
1072 
 
1073 
                // tWR violation check for Write
1074 
                if ($time - WR_chk1 < tWR) begin
1075 
                    $display ("At time %t ERROR: tWR violation during Precharge", $time);
1076 
                end
1077 
            end
1078 
 
1079 
            // Precharge bank 2
1080 
            if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b10)) && Act_b2 === 1'b1) begin
1081 
                Act_b2 = 1'b0;
1082 
                Pc_b2 = 1'b1;
1083 
                RP_chk2 = $time;
1084 
 
1085 
                // Activate to Precharge Bank 2
1086 
                if ($time - RAS_chk2 < tRAS) begin
1087 
                    $display ("At time %t ERROR: tRAS violation during Precharge", $time);
1088 
                end
1089 
 
1090 
                // tWR violation check for Write
1091 
                if ($time - WR_chk2 < tWR) begin
1092 
                    $display ("At time %t ERROR: tWR violation during Precharge", $time);
1093 
                end
1094 
            end
1095 
 
1096 
            // Precharge bank 3
1097 
            if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b11)) && Act_b3 === 1'b1) begin
1098 
                Act_b3 = 1'b0;
1099 
                Pc_b3 = 1'b1;
1100 
                RP_chk3 = $time;
1101 
 
1102 
                // Activate to Precharge Bank 3
1103 
                if ($time - RAS_chk3 < tRAS) begin
1104 
                    $display ("At time %t ERROR: tRAS violation during Precharge", $time);
1105 
                end
1106 
 
1107 
                // tWR violation check for Write
1108 
                if ($time - WR_chk3 < tWR) begin
1109 
                    $display ("At time %t ERROR: tWR violation during Precharge", $time);
1110 
                end
1111 
            end
1112 
 
1113 
            // Prech_count is to make sure we have met part of the initialization sequence
1114 
            Prech_count = Prech_count + 1;
1115 
 
1116 
            // Pipeline for READ
1117 
            A10_precharge [cas_latency_x2] = Addr[10];
1118 
            Bank_precharge[cas_latency_x2] = Ba;
1119 
            Cmnd_precharge[cas_latency_x2] = 1'b1;
1120 
        end
1121 
 
1122 
        // Burst terminate
1123 
        if (Burst_term === 1'b1) begin
1124 
            // Display DEBUG Message
1125 
            if (DEBUG) begin
1126 
                $display ("At time %t BST  : Burst Terminate",$time);
1127 
            end
1128 
 
1129 
            if (Data_in_enable === 1'b1) begin
1130 
                // Illegal to burst terminate a Write
1131 
                $display ("At time %t ERROR: It's illegal to burst terminate a Write", $time);
1132 
                if (!no_halt) $stop (0);
1133 
            end else if (Read_precharge[0] === 1'b1 || Read_precharge[1] === 1'b1 ||
1134 
                // Illegal to burst terminate a Read with Auto Precharge
1135 
                Read_precharge[2] === 1'b1 || Read_precharge[3] === 1'b1) begin
1136 
                $display ("At time %t ERROR: It's illegal to burst terminate a Read with Auto Precharge", $time);
1137 
                if (!no_halt) $stop (0);
1138 
            end else begin
1139 
                // Burst Terminate Command Pipeline for Read
1140 
                Cmnd_bst[cas_latency_x2] = 1'b1;
1141 
            end
1142 
 
1143 
        end
1144 
 
1145 
        // Read Command
1146 
        if (Read_enable === 1'b1) begin
1147 
            if (!(power_up_done)) begin
1148 
                $display ("%m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Read Command", $time);
1149 
            end
1150 
            // Check for DLL reset before Read
1151 
            if (DLL_reset === 1 && DLL_done === 0) begin
1152 
                $display ("%m: at time %t ERROR: You need to wait 200 tCK after DLL Reset Enable to Read, Not %0d clocks.", $time, DLL_count);
1153 
            end
1154 
            // Display DEBUG Message
1155 
            if (DEBUG) begin
1156 
                $display ("At time %t READ : Bank = %h, Col = %h", $time, Ba, {Addr [11], Addr [9 : 0]});
1157 
            end
1158 
 
1159 
            // Terminate a Write
1160 
            if (Data_in_enable === 1'b1) begin
1161 
                Data_in_enable = 1'b0;
1162 
            end
1163 
 
1164 
            // Activate to Read without Auto Precharge
1165 
            if ((Addr [10] === 1'b0 && Ba === 2'b00 && $time - RCD_chk0 < tRCD) ||
1166 
                (Addr [10] === 1'b0 && Ba === 2'b01 && $time - RCD_chk1 < tRCD) ||
1167 
                (Addr [10] === 1'b0 && Ba === 2'b10 && $time - RCD_chk2 < tRCD) ||
1168 
                (Addr [10] === 1'b0 && Ba === 2'b11 && $time - RCD_chk3 < tRCD)) begin
1169 
                $display("At time %t ERROR: tRCD violation during Read", $time);
1170 
            end
1171 
 
1172 
            // Activate to Read with Auto Precharge
1173 
            if ((Addr [10] === 1'b1 && Ba === 2'b00 && $time - RAP_chk0 < tRAP) ||
1174 
                (Addr [10] === 1'b1 && Ba === 2'b01 && $time - RAP_chk1 < tRAP) ||
1175 
                (Addr [10] === 1'b1 && Ba === 2'b10 && $time - RAP_chk2 < tRAP) ||
1176 
                (Addr [10] === 1'b1 && Ba === 2'b11 && $time - RAP_chk3 < tRAP)) begin
1177 
                $display ("At time %t ERROR: tRAP violation during Read", $time);
1178 
            end
1179 
 
1180 
            // Interrupt a Read with Auto Precharge (same bank only)
1181 
            if (Read_precharge [Ba] === 1'b1) begin
1182 
                $display ("At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge", $time);
1183 
                if (!no_halt) $stop (0);
1184 
                // Cancel Auto Precharge
1185 
                if (Addr[10] === 1'b0) begin
1186 
                    Read_precharge [Ba]= 1'b0;
1187 
                end
1188 
            end
1189 
            // Activate to Read
1190 
            if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) ||
1191 
                (Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin
1192 
                $display("At time %t ERROR: Bank is not Activated for Read", $time);
1193 
                if (!no_halt) $stop (0);
1194 
            end else begin
1195 
                // CAS Latency pipeline
1196 
                Read_cmnd[cas_latency_x2] = 1'b1;
1197 
                Read_bank[cas_latency_x2] = Ba;
1198 
                Read_cols[cas_latency_x2] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]};
1199 
                // Auto Precharge
1200 
                if (Addr[10] === 1'b1) begin
1201 
                    Read_precharge [Ba]= 1'b1;
1202 
                    Count_precharge [Ba]= 0;
1203 
                end
1204 
            end
1205 
        end
1206 
 
1207 
        // Write Command
1208 
        if (Write_enable === 1'b1) begin
1209 
            if (!(power_up_done)) begin
1210 
                $display ("%m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Write Command", $time);
1211 
                if (!no_halt) $stop (0);
1212 
            end
1213 
            // display DEBUG message
1214 
            if (DEBUG) begin
1215 
                $display ("At time %t WRITE: Bank = %h, Col = %h", $time, Ba, {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]});
1216 
            end
1217 
 
1218 
            // Activate to Write
1219 
            if ((Ba === 2'b00 && $time - RCD_chk0 < tRCD) ||
1220 
                (Ba === 2'b01 && $time - RCD_chk1 < tRCD) ||
1221 
                (Ba === 2'b10 && $time - RCD_chk2 < tRCD) ||
1222 
                (Ba === 2'b11 && $time - RCD_chk3 < tRCD)) begin
1223 
                $display("At time %t ERROR: tRCD violation during Write to Bank %h", $time, Ba);
1224 
            end
1225 
 
1226 
            // Read to Write
1227 
            if (Read_cmnd[0] || Read_cmnd[1] || Read_cmnd[2] || Read_cmnd[3] ||
1228 
                Read_cmnd[4] || Read_cmnd[5] || Read_cmnd[6] || (Burst_counter < burst_length)) begin
1229 
                if (Data_out_enable || read_precharge_truncation[Ba]) begin
1230 
                    $display("At time %t ERROR: Read to Write violation", $time);
1231 
                end
1232 
            end
1233 
 
1234 
            // Interrupt a Write with Auto Precharge (same bank only)
1235 
            if (Write_precharge [Ba] === 1'b1) begin
1236 
                $display ("At time %t ERROR: it's illegal to interrupt a Write with Auto Precharge", $time);
1237 
                if (!no_halt) $stop (0);
1238 
                // Cancel Auto Precharge
1239 
                if (Addr[10] === 1'b0) begin
1240 
                    Write_precharge [Ba]= 1'b0;
1241 
                end
1242 
            end
1243 
            // Activate to Write
1244 
            if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) ||
1245 
                (Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin
1246 
                $display("At time %t ERROR: Bank is not Activated for Write", $time);
1247 
                if (!no_halt) $stop (0);
1248 
            end else begin
1249 
                // Pipeline for Write
1250 
                Write_cmnd [3] = 1'b1;
1251 
                Write_bank [3] = Ba;
1252 
                Write_cols [3] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]};
1253 
                // Auto Precharge
1254 
                if (Addr[10] === 1'b1) begin
1255 
                    Write_precharge [Ba]= 1'b1;
1256 
                    Count_precharge [Ba]= 0;
1257 
                end
1258 
            end
1259 
        end
1260 
    end
1261 
    endtask
1262 
 
1263 
    task check_neg_dqs;
1264 
    begin
1265 
        if (Write_cmnd[2] || Write_cmnd[1] || Data_in_enable) begin
1266 
            for (i=0; i<DQS_BITS; i=i+1) begin
1267 
                if (expect_neg_dqs[i]) begin
1268 
                    $display ("At time %t ERROR: Negative DQS[%1d] transition required.", $time, i);
1269 
                end
1270 
                expect_neg_dqs[i] = 1'b1;
1271 
            end
1272 
        end else begin
1273 
            expect_pos_dqs = 0;
1274 
            expect_neg_dqs = 0;
1275 
        end
1276 
    end
1277 
    endtask
1278 
 
1279 
    task check_pos_dqs;
1280 
    begin
1281 
        if (Write_cmnd[2] || Write_cmnd[1] || Data_in_enable) begin
1282 
            for (i=0; i<DQS_BITS; i=i+1) begin
1283 
                if (expect_pos_dqs[i]) begin
1284 
                    $display ("At time %t ERROR: Positive DQS[%1d] transition required.", $time, i);
1285 
                end
1286 
                expect_pos_dqs[i] = 1'b1;
1287 
            end
1288 
        end else begin
1289 
            expect_pos_dqs = 0;
1290 
            expect_neg_dqs = 0;
1291 
        end
1292 
    end
1293 
    endtask
1294 
 
1295 
    // Main Logic
1296 
    always @ (posedge Sys_clk) begin
1297 
        Manual_Precharge_Pipeline;
1298 
        Burst_Terminate_Pipeline;
1299 
        Dq_Dqs_Drivers;
1300 
        Write_FIFO_DM_Mask_Logic;
1301 
        Burst_Decode;
1302 
        check_neg_dqs;
1303 
        Auto_Precharge_Calculation;
1304 
        DLL_Counter;
1305 
        Control_Logic;
1306 
    end
1307 
 
1308 
    always @ (negedge Sys_clk) begin
1309 
        Manual_Precharge_Pipeline;
1310 
        Burst_Terminate_Pipeline;
1311 
        Dq_Dqs_Drivers;
1312 
        Write_FIFO_DM_Mask_Logic;
1313 
        Burst_Decode;
1314 
        check_pos_dqs;
1315 
    end
1316 
 
1317 
    // Dqs Receiver
1318 
    always @ (posedge Dqs_in[0]) begin
1319 
        // Latch data at posedge Dqs
1320 
        dq_rise[7 : 0] = Dq_in[7 : 0];
1321 
        dm_rise[0] = Dm_in[0];
1322 
        expect_pos_dqs[0] = 0;
1323 
    end
1324 
 
1325 
    always @ (posedge Dqs_in[1]) begin
1326 
        // Latch data at posedge Dqs
1327 
        dq_rise[15 : 8] = Dq_in[15 : 8];
1328 
        dm_rise[1] = Dm_in [1];
1329 
        expect_pos_dqs[1] = 0;
1330 
    end
1331 
 
1332 
    always @ (posedge Dqs_in[2]) begin
1333 
        // Latch data at posedge Dqs
1334 
        dq_rise[23 : 16] = Dq_in[23 : 16];
1335 
        dm_rise[2] = Dm_in [2];
1336 
        expect_pos_dqs[2] = 0;
1337 
    end
1338 
 
1339 
    always @ (posedge Dqs_in[3]) begin
1340 
        // Latch data at posedge Dqs
1341 
        dq_rise[31 : 24] = Dq_in[31 : 24];
1342 
        dm_rise[3] = Dm_in [3];
1343 
        expect_pos_dqs[3] = 0;
1344 
    end
1345 
 
1346 
    always @ (negedge Dqs_in[0]) begin
1347 
        // Latch data at negedge Dqs
1348 
        dq_fall[7 : 0] = Dq_in[7 : 0];
1349 
        dm_fall[0] = Dm_in[0];
1350 
        dm_pair[1:0]  = {dm_rise[0], dm_fall[0]};
1351 
        expect_neg_dqs[0] = 0;
1352 
    end
1353 
 
1354 
    always @ (negedge Dqs_in[1]) begin
1355 
        // Latch data at negedge Dqs
1356 
        dq_fall[15: 8] = Dq_in[15 : 8];
1357 
        dm_fall[1] = Dm_in[1];
1358 
        dm_pair[3:2]  = {dm_rise[1], dm_fall[1]};
1359 
        expect_neg_dqs[1] = 0;
1360 
    end
1361 
 
1362 
    always @ (negedge Dqs_in[2]) begin
1363 
        // Latch data at negedge Dqs
1364 
        dq_fall[23: 16] = Dq_in[23 : 16];
1365 
        dm_fall[2] = Dm_in[2];
1366 
        dm_pair[5:4]  = {dm_rise[2], dm_fall[2]};
1367 
        expect_neg_dqs[2] = 0;
1368 
    end
1369 
 
1370 
    always @ (negedge Dqs_in[3]) begin
1371 
        // Latch data at negedge Dqs
1372 
        dq_fall[31: 24] = Dq_in[31 : 24];
1373 
        dm_fall[3] = Dm_in[3];
1374 
        dm_pair[7:6]  = {dm_rise[3], dm_fall[3]};
1375 
        expect_neg_dqs[3] = 0;
1376 
    end
1377 
 
1378 
    specify
1379 
                                              // SYMBOL UNITS DESCRIPTION
1380 
                                              // ------ ----- -----------
1381 
`ifdef sg5B                                   //              specparams for -5B (CL = 3)
1382 
        specparam tDSS             =     1.0; // tDSS   ns    DQS falling edge to CLK rising (setup time) = 0.2*tCK
1383 
        specparam tDSH             =     1.0; // tDSH   ns    DQS falling edge from CLK rising (hold time) = 0.2*tCK
1384 
        specparam tIH              =   0.750; // tIH    ns    Input Hold Time
1385 
        specparam tIS              =   0.750; // tIS    ns    Input Setup Time
1386 
        specparam tDQSH            =    1.75; // tDQSH  ns    DQS input High Pulse Width = 0.35*tCK
1387 
        specparam tDQSL            =    1.75; // tDQSL  ns    DQS input Low Pulse Width = 0.35*tCK
1388 
`else `ifdef sg6                              //              specparams for -6 (CL = 2.5)
1389 
        specparam tDSS             =     1.2; // tDSS   ns    DQS falling edge to CLK rising (setup time) = 0.2*tCK
1390 
        specparam tDSH             =     1.2; // tDSH   ns    DQS falling edge from CLK rising (hold time) = 0.2*tCK
1391 
        specparam tIH              =   0.750; // tIH    ns    Input Hold Time
1392 
        specparam tIS              =   0.750; // tIS    ns    Input Setup Time
1393 
        specparam tDQSH            =     2.1; // tDQSH  ns    DQS input High Pulse Width = 0.35*tCK
1394 
        specparam tDQSL            =     2.1; // tDQSL  ns    DQS input Low Pulse Width = 0.35*tCK
1395 
`else `ifdef sg6T                             //              specparams for -6 (CL = 2.5)
1396 
        specparam tDSS             =     1.2; // tDSS   ns    DQS falling edge to CLK rising (setup time) = 0.2*tCK
1397 
        specparam tDSH             =     1.2; // tDSH   ns    DQS falling edge from CLK rising (hold time) = 0.2*tCK
1398 
        specparam tIH              =   0.750; // tIH    ns    Input Hold Time
1399 
        specparam tIS              =   0.750; // tIS    ns    Input Setup Time
1400 
        specparam tDQSH            =     2.1; // tDQSH  ns    DQS input High Pulse Width = 0.35*tCK
1401 
        specparam tDQSL            =     2.1; // tDQSL  ns    DQS input Low Pulse Width = 0.35*tCK
1402 
`else `ifdef sg75                             //              specparams for -75E (CL = 2)
1403 
        specparam tDSS             =     1.5; // tDSS   ns    DQS falling edge to CLK rising (setup time) = 0.2*tCK
1404 
        specparam tDSH             =     1.5; // tDSH   ns    DQS falling edge from CLK rising (hold time) = 0.2*tCK
1405 
        specparam tIH              =   0.900; // tIH    ns    Input Hold Time
1406 
        specparam tIS              =   0.900; // tIS    ns    Input Setup Time
1407 
        specparam tDQSH            =   2.625; // tDQSH  ns    DQS input High Pulse Width = 0.35*tCK
1408 
        specparam tDQSL            =   2.625; // tDQSL  ns    DQS input Low Pulse Width = 0.35*tCK
1409 
`else `ifdef sg75E                            //              specparams for -75E (CL = 2)
1410 
        specparam tDSS             =     1.5; // tDSS   ns    DQS falling edge to CLK rising (setup time) = 0.2*tCK
1411 
        specparam tDSH             =     1.5; // tDSH   ns    DQS falling edge from CLK rising (hold time) = 0.2*tCK
1412 
        specparam tIH              =   0.900; // tIH    ns    Input Hold Time
1413 
        specparam tIS              =   0.900; // tIS    ns    Input Setup Time
1414 
        specparam tDQSH            =   2.625; // tDQSH  ns    DQS input High Pulse Width = 0.35*tCK
1415 
        specparam tDQSL            =   2.625; // tDQSL  ns    DQS input Low Pulse Width = 0.35*tCK
1416 
`else `define sg75Z                           //              specparams for -75Z (CL = 2)
1417 
        specparam tDSS             =     1.5; // tDSS   ns    DQS falling edge to CLK rising (setup time) = 0.2*tCK
1418 
        specparam tDSH             =     1.5; // tDSH   ns    DQS falling edge from CLK rising (hold time) = 0.2*tCK
1419 
        specparam tIH              =   0.900; // tIH    ns    Input Hold Time
1420 
        specparam tIS              =   0.900; // tIS    ns    Input Setup Time
1421 
        specparam tDQSH            =   2.625; // tDQSH  ns    DQS input High Pulse Width = 0.35*tCK
1422 
        specparam tDQSL            =   2.625; // tDQSL  ns    DQS input Low Pulse Width = 0.35*tCK
1423 
`endif `endif `endif `endif `endif
1424 
        $width    (posedge Dqs_in[0] &&& wdqs_valid, tDQSH);
1425 
        $width    (posedge Dqs_in[1] &&& wdqs_valid, tDQSH);
1426 
        $width    (negedge Dqs_in[0] &&& wdqs_valid, tDQSL);
1427 
        $width    (negedge Dqs_in[1] &&& wdqs_valid, tDQSL);
1428 
        $setuphold(posedge Clk,   Cke,   tIS, tIH);
1429 
        $setuphold(posedge Clk,   Cs_n,  tIS, tIH);
1430 
        $setuphold(posedge Clk,   Cas_n, tIS, tIH);
1431 
        $setuphold(posedge Clk,   Ras_n, tIS, tIH);
1432 
        $setuphold(posedge Clk,   We_n,  tIS, tIH);
1433 
        $setuphold(posedge Clk,   Addr,  tIS, tIH);
1434 
        $setuphold(posedge Clk,   Ba,    tIS, tIH);
1435 
        $setuphold(posedge Clk, negedge Dqs &&& wdqs_valid, tDSS, tDSH);
1436 
    endspecify
1437 
 
1438 
endmodule

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