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zpekic |
# Simple UART for FPGA
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Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART controller was implemented using VHDL 93 and is applicable to any FPGA.
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**Simple UART for FPGA requires: 1 start bit, 8 data bits, 1 stop bit!**
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The UART controller was simulated and tested in hardware.
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# Table of inputs and outputs ports:
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Port name | IN/OUT | Width | Port description
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---|:---:|:---:|---
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CLK | IN | 1b | System clock.
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RST | IN | 1b | High active synchronous reset.
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UART_TXD | OUT | 1b | Serial transmit data.
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UART_RXD | IN | 1b | Serial receive data.
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DATA_IN | IN | 8b | Data byte for transmit.
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DATA_SEND | IN | 1b | Send data byte for transmit.
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BUSY | OUT | 1b | Transmitter is busy, can not send next data.
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DATA_OUT | OUT | 8b | Received data byte.
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DATA_VLD | OUT | 1b | Received data byte is valid.
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FRAME_ERROR | OUT | 1b | Stop bit is invalid, data may be corrupted.
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# Table of generics:
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Generic name | Type | Default value | Generic description
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---|:---:|:---:|:---
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CLK_FREQ | integer | 50e6 | System clock.
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BAUD_RATE | integer | 115200 | Baud rate value.
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PARITY_BIT | string | "none" | Type of parity: "none", "even", "odd", "mark", "space".
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USE_DEBOUNCER | boolean | True | Use debounce?
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# Table of resource usage summary:
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Use debouncer | Parity type | LE (LUT+FF) | LUT | FF | BRAM | Fmax
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:---:|:---:|:---:|:---:|:---:|:---:|:---:
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True | none | 77 | 64 | 55 | 0 | 202.2 MHz
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True | even/odd | 82 | 75 | 58 | 0 | 162.5 MHz
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True | mark/space | 80 | 68 | 58 | 0 | 184.5 MHz
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False | none | 72 | 59 | 50 | 0 | 182.7 MHz
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False | even/odd | 77 | 70 | 53 | 0 | 155.6 MHz
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False | mark/space | 75 | 62 | 53 | 0 | 200.8 MHz
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*Synthesis was performed using Quartus II 64-Bit Version 13.0.1 for FPGA Altera Cyclone II with enable force use of synchronous clear. Setting of some generics: BAUD_RATE = 115200, CLK_FREQ = 50e6.*
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# License:
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This UART controller is available under the MIT license (MIT). Please read [LICENSE file](LICENSE).
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