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[/] [soc_auto_vbus/] [trunk/] [src/] [vBUS1.vhd] - Blame information for rev 2

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1 2 pozniak 
use std.textio.all;
2 
library ieee;
3 
use ieee.std_logic_1164.all;
4 
 
5 
package vBUS is
6 
  -- interface declaration
7 
  type TvBUSnodeType is (INPUT, OUTPUT);
8 
  type TvBUSnodeMode is (PART, PREG, WORD, WREG);
9 
  type TvBUSnodeDesc is record
10 
                   name :string(1 to 32);
11 
                    dir :TvBUSnodeType;
12 
                   mode :TvBUSnodeMode;
13 
                   size :positive;
14 
                 end record;
15 
  type TvBUSdesc is array (natural range <>) of TvBUSnodeDesc;
16 
  function vBUSnodeDesc(name :string; dir :TvBUSnodeType; mode :TvBUSnodeMode; size: natural) return TvBUSnodeDesc;
17 
  -- interface configuration
18 
  type TvBUSnodeCfg is record
19 
                      name :string(TvBUSnodeDesc.name'range);
20 
                       dir :TvBUSnodeType;
21 
                      mode :TvBUSnodeMode;
22 
                      size :natural;
23 
                      addr :natural;
24 
                      vpos :natural;
25 
                    end record;
26 
  type TvBUScfg is array (natural range <>) of TvBUSnodeCfg;
27 
  impure function vBUScreator(asize, dsize :positive; desc :TvBUSdesc; fname :string) return TvBUScfg;
28 
  function vBUSlength(cfg :TvBUScfg) return natural;
29 
  -- nodes implementation
30 
  function vBUSnodeWordSize    (name :string; cfg :TvBUScfg) return natural;
31 
  function vBUSnodeOutputData  (name :string; cfg :TvBUScfg; vBUS       :std_logic_vector) return std_logic_vector;
32 
  function vBUSnodeOutputEnable(name :string; cfg :TvBUScfg; vBUS       :std_logic_vector) return std_logic_vector;
33 
  function vBUSnodeInputData   (name :string; cfg :TvBUScfg; vBUS, data :std_logic_vector) return std_logic_vector;
34 
  function vBUSnodeInputEnable (name :string; cfg :TvBUScfg; vBUS       :std_logic_vector) return std_logic_vector;
35 
  -- local interface implementation
36 
  component vBUSinterface is
37 
   generic (
38 
     vBUScfg                    :TvBUScfg);
39 
   port(
40 
     resetN                     :in    std_logic;
41 
     enableN                    :in    std_logic;
42 
     strobeN                    :in    std_logic;
43 
     readN                      :in    std_logic;
44 
     addr                       :in    std_logic_vector;
45 
     data_wr                    :in    std_logic_vector;
46 
     data_rd                    :out   std_logic_vector;
47 
     vbus                       :inout std_logic_vector);
48 
  end component vBUSinterface;
49 
end package;
50 
 
51 
package body vBUS is
52 
 
53 
  function \vBUSname\(name :string) return string is
54 
    variable iname :string(1 to TvBUSnodeDesc.name'length);
55 
  begin
56 
    iname := (others => ' ');
57 
    iname(1 to name'length) := name;
58 
    return(iname);
59 
  end function;
60 
 
61 
  function vBUSnodeDesc(name :string; dir :TvBUSnodeType; mode :TvBUSnodeMode; size: natural) return TvBUSnodeDesc is
62 
    variable item :TvBUSnodeDesc;
63 
  begin
64 
    item.name := \vBUSname\(name);
65 
    item.dir  := dir;
66 
    item.mode := mode;
67 
    item.size := size;
68 
    return(item);
69 
  end function;
70 
 
71 
  impure function vBUScreator(asize, dsize :positive; desc :TvBUSdesc; fname :string) return TvBUScfg is
72 
    variable  vBUS :TvBUScfg(0 to desc'length) := (others => ((others => ' '),INPUT,PART,0,0,0));
73 
    variable  addr, num, vpos :natural := 0;
74 
    file      fid :text open write_mode is fname;
75 
    variable  l : line;
76 
    variable  c : character;
77 
    function \size\(arg :natural) return natural is begin
78 
      for index in 1 to 30 loop
79 
        if (2**index>arg) then return(index); end if;
80 
      end loop;
81 
      return (31);
82 
    end function;
83 
  begin
84 
    -- bus configuration
85 
    for i in 0 to desc'length-1 loop
86 
      num := (desc(i).size-1)/dsize+1;
87 
      vBUS(i+1).name := desc(i).name;
88 
      vBUS(i+1).dir  := desc(i).dir;
89 
      vBUS(i+1).addr := addr;
90 
      vBUS(i+1).size := desc(i).size;
91 
      vBUS(i+1).vpos := vpos;
92 
      vBUS(i+1).mode := desc(i).mode;
93 
      addr := addr + num;
94 
      if (desc(i).dir=OUTPUT) then
95 
        case desc(i).mode is
96 
          when PART => vpos := vpos + num;
97 
          when PREG => vpos := vpos + desc(i).size + num;
98 
          when WORD => vpos := vpos + (num-1)*dsize + 1;
99 
          when WREG => vpos := vpos + desc(i).size + (num-1)*dsize + 1;
100 
        end case;
101 
      else
102 
        case desc(i).mode is
103 
          when PART => vpos := vpos + desc(i).size + num;
104 
          when PREG => vpos := vpos + 2*desc(i).size + num;
105 
          when WORD => vpos := vpos + 2*desc(i).size + 1; if (num>1) then vpos := vpos - dsize; end if;
106 
          when WREG => vpos := vpos + 2*desc(i).size + 1;
107 
        end case;
108 
      end if;
109 
    end loop;
110 
    vBUS(0).addr := asize;
111 
    vBUS(0).size := dsize;
112 
    vBUS(0).vpos := vpos+dsize;
113 
    -- bus configuration checking and description file generation
114 
    assert (addr>0) report "vBUScfg: empty configuration" severity warning;
115 
    assert (\size\(addr-1)<=asize) report "vBUScfg: address size exceeded" severity error;
116 
    write(l,string'("<?xml version=""1.0"" encoding=""ISO-8859-1"" ?>"));
117 
    writeline(fid,l);
118 
    write(l,string'("<bus name=""vBUS"" addr="""&integer'image(vBUS(0).addr)&""" data="""&integer'image(vBUS(0).size)&""">"));
119 
    writeline(fid,l);
120 
    vpos := TvBUSnodeCfg.name'length;
121 
    for i in 1 to vBUS'length-1 loop
122 
      for j in i+1 to vBUS'length-1 loop
123 
        assert (vBUS(i).name /= vBUS(0).name) report "vBUScfg: empty name" severity error;
124 
        assert (vBUS(i).name /= vBUS(j).name) report "vBUScfg: names duplicate" severity error;
125 
      end loop;
126 
      num := vpos;
127 
      for j in 1 to vpos loop
128 
        if (vBUS(i).name(j)=' ') then
129 
          num := j-1;
130 
          assert (vBUS(i).name(j to vpos) = vBUS(0).name(j to vpos)) report "vBUScfg: wrong name" severity error;
131 
          exit;
132 
        end if;
133 
      end loop;
134 
      if vBUS(i).dir=INPUT then c:='r'; else c:='w'; end if;
135 
      write(l,string'("  <node name="""&vBUS(i).name(1 to num)&""" permission="""&c&""" addr="""&
136 
                       integer'image(vBUS(i).addr)&""" size="""&integer'image(vBUS(i).size)&"""/>"));
137 
      writeline(fid,l);
138 
    end loop;
139 
    write(l,string'("</bus>"));
140 
    writeline(fid,l);
141 
    return (vBUS);
142 
  end function;
143 
 
144 
  function vBUSlength(cfg :TvBUScfg) return natural is
145 
  begin
146 
    return(cfg(0).vpos);
147 
  end function;
148 
 
149 
  function \vBUSnodeIdx\(name :string; cfg :TvBUScfg) return natural is
150 
    variable n :string(1 to TvBUSnodeCfg.name'length);
151 
  begin
152 
    n := (others => ' ');
153 
    n(1 to name'length) := name;
154 
    for i in 1 to cfg'length-1 loop
155 
      if(cfg(i).name=n) then return(i); end if;
156 
    end loop;
157 
    return(0);
158 
  end function;
159 
 
160 
  function vBUSnodeWordSize(name :string; cfg :TvBUScfg) return natural is
161 
    constant n: natural := \vBUSnodeIdx\(name,cfg);
162 
  begin
163 
    if (n>0) then return(cfg(n).size); end if;
164 
    assert (false) report "vBUSnodeSize: node <" & name & "> not exist" severity error;
165 
    return (0);
166 
  end function;
167 
 
168 
  function vBUSnodeOutputData(name :string; cfg :TvBUScfg; vBUS :std_logic_vector) return std_logic_vector is
169 
    constant n              :natural := \vBUSnodeIdx\(name,cfg);
170 
    variable d              :std_logic_vector(cfg(n).size-1 downto 0);
171 
    variable dv, mv, nv, pv, sv :natural;
172 
  begin
173 
    if (n>0) then
174 
      if (cfg(n).dir=OUTPUT) then
175 
        d  := (others => '0');
176 
        dv := cfg(0).size; mv := dv;
177 
        nv := (cfg(n).size-1)/cfg(0).size+1;
178 
        pv := cfg(n).vpos;
179 
        sv := cfg(n).size;
180 
        for p in 0 to nv-1 loop
181 
          if (p=nv-1) then mv := sv-(nv-1)*dv; end if;
182 
          case cfg(n).mode is
183 
            when PART =>
184 
              d(p*dv+mv-1 downto p*dv) := vBUS(cfg(0).vpos-dv+mv-1 downto cfg(0).vpos-dv);
185 
            when PREG =>
186 
              d(p*dv+mv-1 downto p*dv) := vBUS(pv+p*dv+mv-1 downto pv+p*dv);
187 
            when WORD =>
188 
              if (nv>1 and p<nv-1) then
189 
                d((p+1)*dv-1 downto p*dv) := vBUS(pv+(p+1)*dv-1 downto pv+p*dv);
190 
              else
191 
                d(p*dv+mv-1 downto p*dv) := vBUS(cfg(0).vpos-dv+mv-1 downto cfg(0).vpos-dv);
192 
              end if;
193 
            when WREG =>
194 
              if (nv>1 and p<nv-1) then
195 
                d((p+1)*dv-1 downto p*dv) := vBUS(pv+sv+(p+1)*dv-1 downto pv+sv+p*dv);
196 
              else
197 
                d(p*dv+mv-1 downto p*dv) := vBUS(pv+p*dv+mv-1 downto pv+p*dv);
198 
              end if;
199 
          end case;
200 
        end loop;
201 
        return(d);
202 
      else
203 
        report "vBUSnodeWrData: node <" & name & "> is read only" severity error;
204 
      end if;
205 
    else
206 
      report "vBUSnodeWrData: node <" & name & "> not exist" severity error;
207 
    end if;
208 
    return ("");
209 
  end function;
210 
 
211 
  function vBUSnodeOutputEnable(name :string; cfg :TvBUScfg; vBUS :std_logic_vector) return std_logic_vector is
212 
    constant n              :natural := \vBUSnodeIdx\(name,cfg);
213 
    variable m              :std_logic_vector(cfg(n).size-1 downto 0);
214 
    variable dv, mv, nv, pv, sv :natural;
215 
  begin
216 
    if (n>0) then
217 
      if (cfg(n).dir=OUTPUT) then
218 
        m  := (others => '0');
219 
        dv := cfg(0).size; mv := dv;
220 
        nv := (cfg(n).size-1)/cfg(0).size+1;
221 
        pv := cfg(n).vpos;
222 
        sv := cfg(n).size;
223 
        for p in 0 to nv-1 loop
224 
          if (p=nv-1) then mv := sv-(nv-1)*dv; end if;
225 
          case cfg(n).mode is
226 
            when PART =>
227 
              m(p*dv+mv-1 downto p*dv) := (others => vBUS(pv+p));
228 
            when PREG =>
229 
              m(p*dv+mv-1 downto p*dv) := (others => vBUS(pv+sv+p));
230 
            when WORD =>
231 
              if (p=nv-1) then
232 
                m := (others => vBUS(pv+(nv-1)*dv));
233 
              end if;
234 
            when WREG =>
235 
              if (p=nv-1) then
236 
                m := (others => vBUS(pv+sv+(nv-1)*dv));
237 
              end if;
238 
          end case;
239 
        end loop;
240 
        return(m);
241 
      else
242 
        report "vBUSnodeWrEna: node <" & name & "> is read only" severity error;
243 
      end if;
244 
    else
245 
      report "vBUSnodeWrEna: node <" & name & "> not exist" severity error;
246 
    end if;
247 
    return ("");
248 
  end function;
249 
 
250 
  function vBUSnodeInputData(name :string; cfg :TvBUScfg; vBUS, data :std_logic_vector) return std_logic_vector is
251 
    constant n: natural := \vBUSnodeIdx\(name,cfg);
252 
    constant d: std_logic_vector(data'length-1 downto 0) := data;
253 
    variable v: std_logic_vector(vBUS'range);
254 
  begin
255 
    if (n>0) then
256 
      if (cfg(n).dir=INPUT) then
257 
        v := (others => 'Z');
258 
        v(cfg(n).vpos+1*cfg(n).size-1 downto 0*cfg(n).size+cfg(n).vpos) := d;
259 
        return(v);
260 
      else
261 
        report "vBUSnodeRdData: node <" & name & "> is write only" severity error;
262 
      end if;
263 
    else
264 
      report "vBUSnodeRdData: node <" & name & "> not exist" severity error;
265 
    end if;
266 
    return ("");
267 
  end function;
268 
 
269 
  function vBUSnodeInputEnable(name :string; cfg :TvBUScfg; vBUS :std_logic_vector) return std_logic_vector is
270 
    constant n              :natural := \vBUSnodeIdx\(name,cfg);
271 
    variable m              :std_logic_vector(cfg(n).size-1 downto 0);
272 
    variable dv, mv, nv, pv, sv :natural;
273 
  begin
274 
    if (n>0) then
275 
      if (cfg(n).dir=INPUT) then
276 
        m  := (others => '0');
277 
        dv := cfg(0).size; mv := dv;
278 
        nv := (cfg(n).size-1)/cfg(0).size+1;
279 
        pv := cfg(n).vpos;
280 
        sv := cfg(n).size;
281 
        for p in 0 to nv-1 loop
282 
          if (p=nv-1) then mv := sv-(nv-1)*dv; end if;
283 
          case cfg(n).mode is
284 
            when PART =>
285 
              m(p*dv+mv-1 downto p*dv) := (others => vBUS(pv+sv+p));
286 
            when PREG =>
287 
              m(p*dv+mv-1 downto p*dv) := (others => vBUS(pv+2*sv+p));
288 
            when WORD =>
289 
              if (nv=1) then
290 
                m := (others => vBUS(pv+sv));
291 
              else
292 
                m := (others => vBUS(pv+2*sv-dv));
293 
              end if;
294 
            when WREG =>
295 
              if (p=nv-1) then
296 
                m := (others => vBUS(pv+2*sv));
297 
              end if;
298 
          end case;
299 
        end loop;
300 
        return(m);
301 
      else
302 
        report "vBUSnodeRdEna: node <" & name & "> is write only" severity error;
303 
      end if;
304 
    else
305 
      report "vBUSnodeRdEna: node <" & name & "> not exist" severity error;
306 
    end if;
307 
    return ("");
308 
  end function;
309 
 
310 
end package body;
311 
 
312 
---------------------------------------------------------------------------
313 
 
314 
library ieee;
315 
use ieee.std_logic_1164.all;
316 
use ieee.std_logic_arith.all;
317 
use work.vBUS.all;
318 
 
319 
entity vBUSinterface is
320 
  generic (
321 
    vBUScfg                     :TvBUScfg
322 
  );
323 
  port(
324 
    resetN                      :in    std_logic;
325 
    enableN                     :in    std_logic;
326 
    strobeN                     :in    std_logic;
327 
    readN                               :in    std_logic;
328 
    addr                        :in    std_logic_vector;
329 
    data_wr                     :in    std_logic_vector;
330 
    data_rd                     :out   std_logic_vector;
331 
    vbus                        :inout std_logic_vector
332 
  );
333 
end entity vBUSinterface;
334 
 
335 
architecture behaviour of vBUSinterface is
336 
 
337 
  signal vbus_awr, vbus_swr, vbus_ard, vbus_srd :std_logic_vector(vbus'range) := (others => '0');
338 
 
339 
begin
340 
 
341 
  async_wr: process (enableN, readN, addr, vbus) is
342 
    variable bv                 :std_logic_vector(vbus'range);
343 
    variable av                 :std_logic;
344 
    variable dv, nv, pv, sv :natural;
345 
  begin
346 
    bv := (others => '0');
347 
    for i in 1 to vBUScfg'length-1 loop
348 
      if (vBUScfg(i).dir=OUTPUT) then
349 
        dv := vBUScfg(0).size;
350 
        nv := (vBUScfg(i).size-1)/vBUScfg(0).size+1;
351 
        pv := vBUScfg(i).vpos;
352 
        sv := vBUScfg(i).size;
353 
        for p in 0 to nv-1 loop
354 
          if (enableN='0' and readN='1' and vBUScfg(i).addr+p=unsigned(addr)) then av := '1'; else av := '0'; end if;
355 
          case vBUScfg(i).mode is
356 
            when PART =>
357 
              bv(pv+p) := av;
358 
            when PREG =>
359 
              bv(pv+sv+p) := av;
360 
            when WORD =>
361 
              if (p=nv-1) then
362 
                bv(pv+(nv-1)*dv) := av;
363 
              end if;
364 
            when WREG =>
365 
              if (p=nv-1) then
366 
                bv(pv+sv+(nv-1)*dv) := av;
367 
              end if;
368 
          end case;
369 
        end loop;
370 
      end if;
371 
    end loop;
372 
    vbus_awr <= bv;
373 
  end process;
374 
 
375 
  sync_wr: process (resetN, strobeN) is
376 
    variable mv, dv, nv, pv, sv :natural;
377 
  begin
378 
    if (resetN='0') then
379 
      vbus_swr <= (others => '0');
380 
    elsif (strobeN'event and strobeN='1') then
381 
      for i in 1 to vBUScfg'length-1 loop
382 
        if (vBUScfg(i).dir=OUTPUT) then
383 
          dv := vBUScfg(0).size; mv := dv;
384 
          nv := (vBUScfg(i).size-1)/vBUScfg(0).size+1;
385 
          pv := vBUScfg(i).vpos;
386 
          sv := vBUScfg(i).size;
387 
          for p in 0 to nv-1 loop
388 
            if (p=nv-1) then mv := sv-(nv-1)*dv; end if;
389 
            if (enableN='0' and readN='1' and vBUScfg(i).addr+p=unsigned(addr)) then
390 
              case vBUScfg(i).mode is
391 
                when PART =>
392 
                  null;
393 
                when PREG =>
394 
                  vbus_swr(pv+p*dv+mv-1 downto pv+p*dv) <= data_wr(mv-1 downto 0);
395 
                when WORD =>
396 
                  if (p<nv-1) then
397 
                    vbus_swr(pv+(p+1)*dv-1 downto pv+p*dv) <= data_wr;
398 
                  end if;
399 
                when WREG =>
400 
                  vbus_swr(pv+p*dv+mv-1 downto pv+p*dv) <= data_wr(mv-1 downto 0);
401 
                  if (nv>1 and p=nv-1) then
402 
                    vbus_swr(pv+sv+p*dv-1 downto pv+sv) <= vbus_swr(pv+p*dv-1 downto pv);
403 
                  end if;
404 
              end case;
405 
            end if;
406 
          end loop;
407 
        end if;
408 
      end loop;
409 
    end if;
410 
  end process;
411 
 
412 
  sync_rd: process (resetN, strobeN) is
413 
    variable mv, dv, nv, pv, sv :natural;
414 
  begin
415 
    if (resetN='0') then
416 
      vbus_srd <= (others => '0');
417 
    elsif (strobeN'event and strobeN='0') then
418 
      for i in 1 to vBUScfg'length-1 loop
419 
        if (vBUScfg(i).dir=INPUT) then
420 
          dv := vBUScfg(0).size; mv := dv;
421 
          nv := (vBUScfg(i).size-1)/vBUScfg(0).size+1;
422 
          pv := vBUScfg(i).vpos;
423 
          sv := vBUScfg(i).size;
424 
          for p in 0 to nv-1 loop
425 
            if(enableN='0' and readN='0' and vBUScfg(i).addr+p=unsigned(addr)) then
426 
              if (p=nv-1) then mv := sv-(nv-1)*vBUScfg(0).size; end if;
427 
              case vBUScfg(i).mode is
428 
                when PART =>
429 
                  null;
430 
                when PREG =>
431 
                  vbus_srd(pv+sv+p*dv+mv-1 downto pv+sv+p*dv) <= vbus(pv+p*dv+mv-1 downto pv+p*dv);
432 
                when WORD =>
433 
                  if (p=0 and nv>1) then
434 
                    vbus_srd(pv+2*sv-dv-1 downto pv+sv) <= vbus(pv+sv-1 downto pv+dv);
435 
                  end if;
436 
                when WREG =>
437 
                  if (p=0) then
438 
                    vbus_srd(pv+2*sv-1 downto pv+1*sv) <= vbus(pv+1*sv-1 downto pv);
439 
                  end if;
440 
              end case;
441 
            end if;
442 
          end loop;
443 
        end if;
444 
      end loop;
445 
    end if;
446 
  end process;
447 
 
448 
  async_rd: process (enableN, readN, addr, vbus) is
449 
    variable bv                 :std_logic_vector(vbus'range);
450 
    variable dr, dp, dm         :std_logic_vector(vBUScfg(0).size-1 downto 0);
451 
    variable mv, dv, nv, pv, sv :natural;
452 
  begin
453 
    bv := (others => '0');
454 
    dr := (others => '0');
455 
    for i in 1 to vBUScfg'length-1 loop
456 
      if (vBUScfg(i).dir=INPUT) then
457 
        dv := vBUScfg(0).size; mv := dv;
458 
        nv := (vBUScfg(i).size-1)/vBUScfg(0).size+1;
459 
        pv := vBUScfg(i).vpos;
460 
        sv := vBUScfg(i).size;
461 
        dp := (others => '0');
462 
        for p in 0 to nv-1 loop
463 
          if (p=nv-1) then mv := sv-(nv-1)*vBUScfg(0).size; end if;
464 
          dm := (others => '0');
465 
          if (enableN='0' and readN='0' and vBUScfg(i).addr+p=unsigned(addr)) then dm := (others => '1'); end if;
466 
          case vBUScfg(i).mode is
467 
            when PART =>
468 
              bv(pv+sv+p) := dm(0);
469 
              dp(mv-1 downto 0) := vbus(pv+p*dv+mv-1 downto pv+p*dv);
470 
            when PREG =>
471 
              bv(pv+2*sv+p) := dm(0);
472 
              dp(mv-1 downto 0) := vbus(pv+sv+p*dv+mv-1 downto pv+sv+p*dv);
473 
            when WORD =>
474 
              if (p=0) then
475 
                if (nv=1) then
476 
                  bv(pv+sv) := dm(0);
477 
                else
478 
                  bv(pv+2*sv-dv) := dm(0);
479 
                end if;
480 
                dp(mv-1 downto 0) := vbus(pv+mv-1 downto pv);
481 
              else
482 
                dp(mv-1 downto 0) := vbus(pv+sv+(p-1)*dv+mv-1 downto pv+sv+(p-1)*dv);
483 
              end if;
484 
            when WREG =>
485 
              if (p=0) then
486 
                bv(pv+2*sv) := dm(0);
487 
              end if;
488 
              dp(mv-1 downto 0) := vbus(pv+sv+p*dv+mv-1 downto pv+sv+p*dv);
489 
          end case;
490 
          dr(mv-1 downto 0) := dr(mv-1 downto 0) or (dp(mv-1 downto 0) and dm(mv-1 downto 0));
491 
        end loop;
492 
      end if;
493 
    end loop;
494 
    vbus_ard <= bv;
495 
    data_rd  <= dr;
496 
  end process;
497 
 
498 
  async_vec: process (vbus_awr, vbus_swr, vbus_srd, vbus_ard, data_wr, enableN, strobeN, resetN) is
499 
    variable bv :std_logic_vector(vbus'range);
500 
  begin
501 
    bv := vbus_awr or vbus_ard or vbus_swr or vbus_srd;
502 
    for i in 1 to vBUScfg'length-1 loop
503 
      if (vBUScfg(i).dir=INPUT) then
504 
        bv(vBUScfg(i).size+vBUScfg(i).vpos-1 downto vBUScfg(i).vpos) := (others => 'Z');
505 
      end if;
506 
    end loop;
507 
    bv(bv'length-1 downto bv'length-vBUScfg(0).size) := data_wr;
508 
    vbus <= bv;
509 
  end process;
510 
 
511 
end behaviour;
512 
 
513 
---------------------------------------------------------------------------
514 
 
515 
library ieee;
516 
use ieee.std_logic_1164.all;
517 
use ieee.std_logic_arith.all;
518 
use work.vBUS.all;
519 
 
520 
entity vBUS_TEST_A_SUM is
521 
  generic (vBUScfg :TvBUScfg);
522 
  port    (vBUS    :inout std_logic_vector);
523 
end entity vBUS_TEST_A_SUM;
524 
 
525 
architecture behaviour of vBUS_TEST_A_SUM is
526 
  signal arg1D :std_logic_vector(vBUSnodeWordSize("arg1", vBUScfg)-1 downto 0);
527 
  signal arg2D :std_logic_vector(vBUSnodeWordSize("arg2", vBUScfg)-1 downto 0);
528 
  signal sumD  :std_logic_vector(vBUSnodeWordSize("sum",  vBUScfg)-1 downto 0);
529 
begin
530 
  sumD  <= unsigned(arg1D) + unsigned(arg2D);
531 
  arg1D <= vBUSnodeOutputData("arg1", vBUScfg, vBUS);
532 
  arg2D <= vBUSnodeOutputData("arg2", vBUScfg, vBUS);
533 
  vBUS  <= vBUSnodeInputData ("sum",  vBUScfg, vBUS, sumD);
534 
end behaviour;
535 
 
536 
---------------------------------------------------------------------------
537 
 
538 
library ieee;
539 
use ieee.std_logic_1164.all;
540 
use ieee.std_logic_arith.all;
541 
use work.vBUS.all;
542 
 
543 
entity vBUS_TEST_A_MULT is
544 
  generic (vBUScfg :TvBUScfg);
545 
  port    (vBUS    :inout std_logic_vector);
546 
end entity vBUS_TEST_A_MULT;
547 
 
548 
architecture behaviour of vBUS_TEST_A_MULT is
549 
  signal arg1D :std_logic_vector(vBUSnodeWordSize("arg1", vBUScfg)-1 downto 0);
550 
  signal arg2D :std_logic_vector(vBUSnodeWordSize("arg2", vBUScfg)-1 downto 0);
551 
  signal multD :std_logic_vector(vBUSnodeWordSize("mult", vBUScfg)-1 downto 0);
552 
begin
553 
  multD <= unsigned(arg1D) * unsigned(arg2D);
554 
  arg1D <= vBUSnodeOutputData("arg1", vBUScfg, vBUS);
555 
  arg2D <= vBUSnodeOutputData("arg2", vBUScfg, vBUS);
556 
  vBUS  <= vBUSnodeInputData ("mult", vBUScfg, vBUS, multD);
557 
end behaviour;
558 
 
559 
---------------------------------------------------------------------------
560 
 
561 
library ieee;
562 
use ieee.std_logic_1164.all;
563 
use ieee.std_logic_arith.all;
564 
use work.vBUS.all;
565 
 
566 
entity vBUS_TEST_B is
567 
  generic (
568 
    ADDR_WIDTH                  :natural := 4;
569 
    DATA_WIDTH                  :natural := 4
570 
  );
571 
  port(
572 
    resetN                      :in  std_logic;
573 
    enableN                     :in  std_logic;
574 
    strobeN                     :in  std_logic;
575 
    readN                       :in  std_logic;
576 
    addr                        :in  std_logic_vector(ADDR_WIDTH-1 downto 0);
577 
    data_wr                     :in  std_logic_vector(DATA_WIDTH-1 downto 0);
578 
    data_rd                     :out std_logic_vector(DATA_WIDTH-1 downto 0)
579 
  );
580 
end entity vBUS_TEST_B;
581 
 
582 
architecture behaviour of vBUS_TEST_B is
583 
 
584 
  constant vBUSdesc :TvBUSdesc := (vBUSnodeDesc("arg1", OUTPUT, WREG, 2*ADDR_WIDTH),
585 
                                   vBUSnodeDesc("arg2", OUTPUT, WREG, 2*ADDR_WIDTH),
586 
                                   vBUSnodeDesc("mult", INPUT,  PART, 4*ADDR_WIDTH),
587 
                                   vBUSnodeDesc("sum",  INPUT,  PART, 2*ADDR_WIDTH));
588 
  constant vBUScfg   :TvBUScfg := vBUScreator(ADDR_WIDTH, DATA_WIDTH, vBUSdesc, "C:\Home\Pozniak\Projekty\vhdl\tests\src\var\bus_config.xml");
589 
  signal   vBUS      :std_logic_vector(vBUSlength(vBUScfg)-1 downto 0);
590 
 
591 
begin
592 
  interf: vBUSinterface generic map (vBUScfg) port map (resetN, enableN, strobeN, readN, addr, data_wr, data_rd, vBUS);
593 
 
594 
  sum:  entity work.vBUS_TEST_A_SUM  generic map (vBUScfg) port map (vBUS);
595 
  mult: entity work.vBUS_TEST_A_MULT generic map (vBUScfg) port map (vBUS);
596 
end behaviour;
597 
 
598 
---------------------------------------------------------------------------
599 
 
600 
library ieee;
601 
use ieee.std_logic_1164.all;
602 
use ieee.std_logic_arith.all;
603 
use work.vBUS.all;
604 
 
605 
entity vBUS_TEST_A is
606 
  generic (
607 
    ADDR_WIDTH                  :natural := 3;
608 
    DATA_WIDTH                  :natural := 4;
609 
    ITEM_MODE                   :TvBUSnodeMode := PART
610 
  );
611 
  port(
612 
    resetN                      :in  std_logic;
613 
    enableN                     :in  std_logic;
614 
    strobeN                     :in  std_logic;
615 
    readN                       :in  std_logic;
616 
    addr                        :in  std_logic_vector(ADDR_WIDTH-1 downto 0);
617 
    data_wr                     :in  std_logic_vector(DATA_WIDTH-1 downto 0);
618 
    data_rd                     :out std_logic_vector(DATA_WIDTH-1 downto 0);
619 
    sdata_output                :out std_logic_vector(DATA_WIDTH/2-1 downto 0);
620 
    sena_output                 :out std_logic_vector(DATA_WIDTH/2-1 downto 0);
621 
    ldata_output                :out std_logic_vector(5*(DATA_WIDTH/2)-1 downto 0);
622 
    lena_output                 :out std_logic_vector(5*(DATA_WIDTH/2)-1 downto 0);
623 
    sdata_input                 :in  std_logic_vector(DATA_WIDTH/2-1 downto 0);
624 
    sena_input                  :out std_logic_vector(DATA_WIDTH/2-1 downto 0);
625 
    ldata_input                 :in  std_logic_vector(5*(DATA_WIDTH/2)-1 downto 0);
626 
    lena_input                  :out std_logic_vector(5*(DATA_WIDTH/2)-1 downto 0)
627 
  );
628 
end entity vBUS_TEST_A;
629 
 
630 
architecture behaviour of vBUS_TEST_A is
631 
  constant vBUSdesc :TvBUSdesc := (vBUSnodeDesc("soutput", OUTPUT, ITEM_MODE, sdata_output'length),
632 
                                   vBUSnodeDesc("loutput", OUTPUT, ITEM_MODE, ldata_output'length),
633 
                                   vBUSnodeDesc("sinput",  INPUT,  ITEM_MODE, sdata_input'length),
634 
                                   vBUSnodeDesc("linput",  INPUT,  ITEM_MODE, ldata_input'length));
635 
  constant vBUScfg   :TvBUScfg := vBUScreator(ADDR_WIDTH, DATA_WIDTH, vBUSdesc, "C:\Home\Pozniak\Projekty\vhdl\tests\src\var\bus_config.xml");
636 
  signal   vBUS      :std_logic_vector(vBUSlength(vBUScfg)-1 downto 0);
637 
begin
638 
  i: vBUSinterface generic map (vBUScfg) port map (resetN, enableN, strobeN, readN, addr, data_wr, data_rd, vBUS);
639 
 
640 
  sdata_output <= vBUSnodeOutputData  ("soutput", vBUScfg, vBUS);
641 
  sena_output  <= vBUSnodeOutputEnable("soutput", vBUScfg, vBUS);
642 
  ldata_output <= vBUSnodeOutputData  ("loutput", vBUScfg, vBUS);
643 
  lena_output  <= vBUSnodeOutputEnable("loutput", vBUScfg, vBUS);
644 
  vBUS         <= vBUSnodeInputData   ("sinput",  vBUScfg, vBUS, sdata_input);
645 
  sena_input   <= vBUSnodeInputEnable ("sinput",  vBUScfg, vBUS);
646 
  vBUS         <= vBUSnodeInputData   ("linput",  vBUScfg, vBUS, ldata_input);
647 
  lena_input   <= vBUSnodeInputEnable ("linput",  vBUScfg, vBUS);
648 
end behaviour;
649 
 

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