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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [Nexys2/] [ip/] [clock/] [rtl/] [xml/] [cde_clock_sys.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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digilentinc.com
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Nexys2
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clock
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sys
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      fs-syn
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        dest_dir
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        ../verilog/syn/
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        verilogSource
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        libraryDir
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              syn:*Synthesis:*
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              Verilog
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                            fs-syn
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