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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [Nexys2/] [ip/] [sram/] [rtl/] [xml/] [sram_def.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://digilentinc.com"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
digilentinc.com
Nexys2
sram
def
 

 
 
 
 

 
 
 

 
 
 
 
   
      fs-sim
 
 
 
       
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
 
 
  
 
 
   
      fs-syn
 
 
 
       
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
 
 
 
   
 
 
 
   
      fs-lint
 
 
       
        dest_dir../verilog/lint/
        verilogSourcelibraryDir
      
 
 
 
 
   
 
 
 
 
 

 
 
 
 
 
 

 
 
 
                
                        
                                verilog
                                verilog
                                cde_sram_def
                                
                                        
                                                ADDR
                                                8
                                        
                                        
                                                WIDTH
                                                8
                                        
                                        
                                                WORDS
                                                256
                                        
                                        
                                                WRITETHRU
                                                1
                                        
                                
                                
                                        fs-sim
                                
                        
                
 
 
 
  
 
        
        rtl
        verilog:Kactus2:
        verilog
        
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
 
 
 
 
 
 
      
 
 
 

ADDR10
WIDTH8
WORDS1024
WRITETHRU0

 

 
clk
wire
in

 
cs
wire
in

 
wr
wire
in

 
rd
wire
in

 
 
addr
wire
in
ADDR-10

 
 
wdata
wire
in
WIDTH-10

 
rdata
reg
out
WIDTH-10

 
 
 

 

 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [Nexys2/] [ip/] [sram/] [rtl/] [xml/] [sram_def.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5	135	jt_eaton
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://digilentinc.com"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11	131	jt_eaton
12	135	jt_eaton	`digilentinc.com`
13			`Nexys2`
14			`sram`
15			`def`
16	131	jt_eaton
17	135	jt_eaton
18	131	jt_eaton
19
20
21
22	135	jt_eaton
23	131	jt_eaton
24
25
26	135	jt_eaton
27	131	jt_eaton
28
29
30
31	135	jt_eaton
32			`fs-sim`
33	131	jt_eaton
34
35
36	135	jt_eaton
37			`dest_dir../verilog/`
38			`verilogSourcelibraryDir`
39
40	131	jt_eaton
41
42
43	135	jt_eaton
44	131	jt_eaton
45
46	135	jt_eaton
47			`fs-syn`
48	131	jt_eaton
49
50
51	135	jt_eaton
52			`dest_dir../verilog/`
53			`verilogSourcelibraryDir`
54
55	131	jt_eaton
56
57
58
59	135	jt_eaton
60	131	jt_eaton
61
62
63	135	jt_eaton
64			`fs-lint`
65	131	jt_eaton
66
67	135	jt_eaton
68			`dest_dir../verilog/lint/`
69			`verilogSourcelibraryDir`
70
71	131	jt_eaton
72
73
74
75	135	jt_eaton
76	131	jt_eaton
77
78
79
80
81	135	jt_eaton
82	131	jt_eaton
83
84
85
86
87
88	135	jt_eaton
89	131	jt_eaton
90
91
92	135	jt_eaton
93
94			`verilog`
95			`verilog`
96			`cde_sram_def`
97
98
99			`ADDR`
100			`8`
101
102
103			`WIDTH`
104			`8`
105
106
107			`WORDS`
108			`256`
109
110
111			`WRITETHRU`
112			`1`
113
114
115
116			`fs-sim`
117
118
119
120	131	jt_eaton
121
122
123	135	jt_eaton
124	131	jt_eaton
125	135	jt_eaton
126			`rtl`
127			`verilog:Kactus2:`
128			`verilog`
129
130	131	jt_eaton
131	135	jt_eaton
132
133			`sim:Simulation:`
134			`Verilog`
135
136
137			`fs-sim`
138
139
140	131	jt_eaton
141	135	jt_eaton
142			`syn:Synthesis:`
143			`Verilog`
144
145
146			`fs-syn`
147
148
149	131	jt_eaton
150
151	135	jt_eaton
152			`lint:Lint:`
153			`Verilog`
154
155
156			`fs-lint`
157
158
159	131	jt_eaton
160
161
162
163
164
165
166
167	135	jt_eaton
168	131	jt_eaton
169
170
171	135	jt_eaton
172			`ADDR10`
173			`WIDTH8`
174			`WORDS1024`
175			`WRITETHRU0`
176
177	131	jt_eaton
178	135	jt_eaton
179	131	jt_eaton
180	135	jt_eaton	`clk`
181			`wire`
182			`in`
183
184	131	jt_eaton
185	135	jt_eaton	`cs`
186			`wire`
187			`in`
188
189	131	jt_eaton
190	135	jt_eaton	`wr`
191			`wire`
192			`in`
193
194	131	jt_eaton
195	135	jt_eaton	`rd`
196			`wire`
197			`in`
198
199	131	jt_eaton
200
201	135	jt_eaton	`addr`
202			`wire`
203			`in`
204			`ADDR-10`
205
206	131	jt_eaton
207
208	135	jt_eaton	`wdata`
209			`wire`
210			`in`
211			`WIDTH-10`
212
213	131	jt_eaton
214	135	jt_eaton	`rdata`
215			`reg`
216			`out`
217			`WIDTH-10`
218
219	131	jt_eaton
220
221
222	135	jt_eaton
223	131	jt_eaton
224	135	jt_eaton
225	131	jt_eaton
226
227
228
229	135	jt_eaton
230
231
232
233
234
235
236