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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [doc/] [sch/] [core_def.sch] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
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C 2100 300 1 0 0 in_port_vector.sym
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{
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T 2100 300 5 10 1 1 0 6 1 1
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refdes=vec_int[7:0]
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}
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C 2100 700 1 0 0 in_port_vector.sym
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{
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T 2100 700 5 10 1 1 0 6 1 1
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refdes=stk_pull_data[15:0]
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}
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C 2100 1100 1 0 0 in_port_vector.sym
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{
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T 2100 1100 5 10 1 1 0 6 1 1
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refdes=rdata[15:0]
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}
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C 2100 1500 1 0 0 in_port_vector.sym
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{
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T 2100 1500 5 10 1 1 0 6 1 1
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refdes=prog_data[15:0]
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}
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C 2100 1900 1 0 0 in_port_vector.sym
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{
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T 2100 1900 5 10 1 1 0 6 1 1
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refdes=pg0_data[7:0]
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}
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C 2100 2300 1 0 0 in_port.sym
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{
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T 2100 2300 5 10 1 1 0 6 1 1
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refdes=reset
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}
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C 2100 2700 1 0 0 in_port.sym
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{
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T 2100 2700 5 10 1 1 0 6 1 1
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refdes=nmi
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}
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C 2100 3100 1 0 0 in_port.sym
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{
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T 2100 3100 5 10 1 1 0 6 1 1
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refdes=enable
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}
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C 2100 3500 1 0 0 in_port.sym
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{
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T 2100 3500 5 10 1 1 0 6 1 1
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refdes=clk
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}
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C 5300 300  1 0  0 out_port_vector.sym
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{
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T 6300 300 5  10 1 1 0 0 1 1
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refdes=wdata[7:0]
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}
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C 5300 700  1 0  0 out_port_vector.sym
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{
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T 6300 700 5  10 1 1 0 0 1 1
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refdes=stk_push_data[15:0]
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}
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C 5300 1100  1 0  0 out_port_vector.sym
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{
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T 6300 1100 5  10 1 1 0 0 1 1
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refdes=prog_counter[15:0]
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}
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C 5300 1500  1 0  0 out_port_vector.sym
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{
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T 6300 1500 5  10 1 1 0 0 1 1
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refdes=pg0_add[7:0]
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}
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C 5300 1900  1 0  0 out_port_vector.sym
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{
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T 6300 1900 5  10 1 1 0 0 1 1
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refdes=alu_status[7:0]
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}
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C 5300 2300  1 0  0 out_port_vector.sym
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{
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T 6300 2300 5  10 1 1 0 0 1 1
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refdes=addr[15:0]
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}
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C 5300 2700  1 0 0 out_port.sym
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{
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T 6300 2700 5  10 1 1 0 0 1 1
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refdes=wr
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}
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C 5300 3100  1 0 0 out_port.sym
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{
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T 6300 3100 5  10 1 1 0 0 1 1
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refdes=stk_push
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}
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C 5300 3500  1 0 0 out_port.sym
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{
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T 6300 3500 5  10 1 1 0 0 1 1
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refdes=stk_pull
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}
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C 5300 3900  1 0 0 out_port.sym
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{
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T 6300 3900 5  10 1 1 0 0 1 1
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refdes=rd
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}
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C 5300 4300  1 0 0 out_port.sym
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{
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T 6300 4300 5  10 1 1 0 0 1 1
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refdes=pg0_wr
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}
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C 5300 4700  1 0 0 out_port.sym
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{
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T 6300 4700 5  10 1 1 0 0 1 1
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refdes=pg0_rd
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}

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