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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [doc/] [sch/] [T6502_ctrl.sch] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
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C 1700 300 1 0 0 in_port_vector.sym
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{
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T 1700 300 5 10 1 1 0 6 1 1
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refdes=timer_irq[1:0]
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}
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C 1700 700 1 0 0 in_port_vector.sym
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{
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T 1700 700 5 10 1 1 0 6 1 1
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refdes=pg0_add[7:0]
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}
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C 1700 1100 1 0 0 in_port_vector.sym
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{
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T 1700 1100 5 10 1 1 0 6 1 1
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refdes=mem_wdata[15:0]
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}
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C 1700 1500 1 0 0 in_port_vector.sym
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{
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T 1700 1500 5 10 1 1 0 6 1 1
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refdes=mem_addr[0:0]
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}
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C 1700 1900 1 0 0 in_port_vector.sym
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{
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T 1700 1900 5 10 1 1 0 6 1 1
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refdes=ext_irq_in[2:0]
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}
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C 1700 2300 1 0 0 in_port.sym
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{
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T 1700 2300 5 10 1 1 0 6 1 1
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refdes=tx_irq
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}
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C 1700 2700 1 0 0 in_port.sym
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{
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T 1700 2700 5 10 1 1 0 6 1 1
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refdes=rx_irq
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}
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C 1700 3100 1 0 0 in_port.sym
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{
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T 1700 3100 5 10 1 1 0 6 1 1
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refdes=ps2_data_avail
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}
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C 1700 3500 1 0 0 in_port.sym
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{
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T 1700 3500 5 10 1 1 0 6 1 1
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refdes=pg0_wr
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}
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C 1700 3900 1 0 0 in_port.sym
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{
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T 1700 3900 5 10 1 1 0 6 1 1
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refdes=pg0_rd
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}
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C 1700 4300 1 0 0 in_port.sym
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{
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T 1700 4300 5 10 1 1 0 6 1 1
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refdes=mem_wr
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}
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C 1700 4700 1 0 0 in_port.sym
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{
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T 1700 4700 5 10 1 1 0 6 1 1
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refdes=mem_rd
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}
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C 1700 5100 1 0 0 in_port.sym
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{
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T 1700 5100 5 10 1 1 0 6 1 1
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refdes=mem_cs
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}
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C 1700 5500 1 0 0 in_port.sym
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{
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T 1700 5500 5 10 1 1 0 6 1 1
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refdes=clk
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}
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C 5500 300  1 0  0 out_port_vector.sym
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{
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T 6500 300 5  10 1 1 0 0 1 1
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refdes=mem_rdata[15:0]
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}
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C 5500 700  1 0  0 out_port_vector.sym
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{
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T 6500 700 5  10 1 1 0 0 1 1
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refdes=io_module_vic_irq_in[7:0]
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}
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C 5500 1100  1 0  0 out_port_vector.sym
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{
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T 6500 1100 5  10 1 1 0 0 1 1
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refdes=io_module_pic_irq_in[7:0]
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}
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C 5500 1500  1 0  0 out_port_vector.sym
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{
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T 6500 1500 5  10 1 1 0 0 1 1
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refdes=cpu_pg0_data[7:0]
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}

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